Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_upload.u_payloadptr_clr_psync	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.69	94.25	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.69	94.25	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.37	100.00	86.11		100.00	95.74	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T4,T8,T11
1	0	Covered	T4,T8,T11
1	1	Covered	T4,T11,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T8,T11
1	0	Covered	T4,T11,T12
1	1	Covered	T4,T8,T11

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1607441619	3466	0	0
SrcPulseCheck_M	566890416	3466	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1607441619	3466	0	0
T4	188429	6	0	0
T8	1058184	1	0	0
T9	78868	0	0	0
T10	10310	0	0	0
T11	378852	10	0	0
T12	0	7	0	0
T13	66920	0	0	0
T15	24824	9	0	0
T16	1568	0	0	0
T18	406262	22	0	0
T19	721877	0	0	0
T25	216531	5	0	0
T26	231290	16	0	0
T27	0	2	0	0
T28	0	15	0	0
T35	46129	12	0	0
T36	0	7	0	0
T37	19990	0	0	0
T52	2620	0	0	0
T53	841	0	0	0
T56	1104	0	0	0
T59	3448	0	0	0
T75	224450	0	0	0
T85	15175	0	0	0
T92	125399	0	0	0
T121	0	7	0	0
T122	0	7	0	0
T123	0	9	0	0
T124	0	7	0	0
T125	0	1	0	0
T126	0	7	0	0
T127	0	4	0	0
T128	0	2	0	0
T129	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	566890416	3466	0	0
T4	160312	6	0	0
T5	55554	0	0	0
T7	1775	0	0	0
T8	150664	1	0	0
T9	33486	0	0	0
T11	1272222	10	0	0
T12	1443210	7	0	0
T13	60334	0	0	0
T14	24976	0	0	0
T15	147172	9	0	0
T17	89264	0	0	0
T18	203642	22	0	0
T19	123666	0	0	0
T25	616428	5	0	0
T26	113542	16	0	0
T27	0	2	0	0
T28	0	15	0	0
T35	78214	12	0	0
T36	0	7	0	0
T37	60372	0	0	0
T75	42865	0	0	0
T85	12494	0	0	0
T92	40669	0	0	0
T121	0	7	0	0
T122	0	7	0	0
T123	0	9	0	0
T124	0	7	0	0
T125	0	1	0	0
T126	0	7	0	0
T127	0	4	0	0
T128	0	2	0	0
T129	0	2	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T8,T15,T35
1	0	Covered	T8,T15,T35
1	1	Covered	T15,T35,T36

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T15,T35
1	0	Covered	T15,T35,T36
1	1	Covered	T8,T15,T35

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	535813873	395	0	0
SrcPulseCheck_M	188963472	395	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535813873	395	0	0
T8	529092	1	0	0
T9	39434	0	0	0
T10	5155	0	0	0
T11	378852	0	0	0
T13	33460	0	0	0
T15	0	5	0	0
T16	1568	0	0	0
T35	0	6	0	0
T36	0	2	0	0
T52	1310	0	0	0
T53	841	0	0	0
T56	1104	0	0	0
T59	1724	0	0	0
T121	0	2	0	0
T122	0	2	0	0
T124	0	2	0	0
T126	0	2	0	0
T128	0	2	0	0
T129	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	395	0	0
T8	75332	1	0	0
T9	16743	0	0	0
T11	636111	0	0	0
T12	721605	0	0	0
T13	30167	0	0	0
T14	12488	0	0	0
T15	73586	5	0	0
T17	44632	0	0	0
T18	101821	0	0	0
T25	308214	0	0	0
T35	0	6	0	0
T36	0	2	0	0
T121	0	2	0	0
T122	0	2	0	0
T124	0	2	0	0
T126	0	2	0	0
T128	0	2	0	0
T129	0	2	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T15,T35,T36
1	0	Covered	T15,T35,T36
1	1	Covered	T15,T35,T36

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T35,T36
1	0	Covered	T15,T35,T36
1	1	Covered	T15,T35,T36

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	535813873	571	0	0
SrcPulseCheck_M	188963472	571	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535813873	571	0	0
T15	24824	4	0	0
T18	406262	0	0	0
T19	721877	0	0	0
T25	216531	0	0	0
T26	231290	0	0	0
T35	46129	6	0	0
T36	0	5	0	0
T37	19990	0	0	0
T75	224450	0	0	0
T85	15175	0	0	0
T92	125399	0	0	0
T121	0	5	0	0
T122	0	5	0	0
T123	0	9	0	0
T124	0	5	0	0
T125	0	1	0	0
T126	0	5	0	0
T127	0	4	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	571	0	0
T15	73586	4	0	0
T18	101821	0	0	0
T19	123666	0	0	0
T25	308214	0	0	0
T26	113542	0	0	0
T35	78214	6	0	0
T36	0	5	0	0
T37	60372	0	0	0
T75	42865	0	0	0
T85	12494	0	0	0
T92	40669	0	0	0
T121	0	5	0	0
T122	0	5	0	0
T123	0	9	0	0
T124	0	5	0	0
T125	0	1	0	0
T126	0	5	0	0
T127	0	4	0	0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T4,T11,T12
1	0	Covered	T4,T11,T12
1	1	Covered	T4,T11,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T4,T11,T12
1	1	Covered	T4,T11,T12

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	535813873	2500	0	0
SrcPulseCheck_M	188963472	2500	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535813873	2500	0	0
T4	188429	6	0	0
T5	279988	0	0	0
T6	1127	0	0	0
T7	5329	0	0	0
T8	529092	0	0	0
T9	39434	0	0	0
T10	5155	0	0	0
T11	0	10	0	0
T12	0	7	0	0
T13	33460	0	0	0
T18	0	22	0	0
T25	0	5	0	0
T26	0	16	0	0
T27	0	2	0	0
T28	0	15	0	0
T30	0	12	0	0
T39	0	4	0	0
T52	1310	0	0	0
T59	1724	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	2500	0	0
T4	160312	6	0	0
T5	55554	0	0	0
T7	1775	0	0	0
T8	75332	0	0	0
T9	16743	0	0	0
T11	636111	10	0	0
T12	721605	7	0	0
T13	30167	0	0	0
T14	12488	0	0	0
T17	44632	0	0	0
T18	0	22	0	0
T25	0	5	0	0
T26	0	16	0	0
T27	0	2	0	0
T28	0	15	0	0
T30	0	12	0	0
T39	0	4	0	0