Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T11,T12
1	0	Covered	T3,T11,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T7
1	0	Unreachable
1	1	Covered	T3,T11,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T11,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T4,T11,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Unreachable
1	1	Covered	T4,T11,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	913740817	722796143	0	0
CheckNGreaterZero_A	2826	2826	0	0
GntImpliesReady_A	913740817	4346633	0	0
GntImpliesValid_A	913740817	4346633	0	0
GrantKnown_A	913740817	722796143	0	0
IdxKnown_A	913740817	722796143	0	0
IndexIsCorrect_A	913740817	4346633	0	0
LockArbDecision_A	913740817	0	0	0
NoReadyValidNoGrant_A	913740817	0	0	0
ReadyAndValidImplyGrant_A	913740817	4346633	0	0
ReqAndReadyImplyGrant_A	913740817	4346633	0	0
ReqImpliesValid_A	913740817	4346633	0	0
ReqStaysHighUntilGranted0_M	913740817	0	0	0
RoundRobin_A	913740817	3	0	942
ValidKnown_A	913740817	722796143	0	0
gen_data_port_assertion.DataFlow_A	913740817	4346633	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	913740817	722796143	0	0
T1	1454	1396	0	0
T2	206135	205362	0	0
T3	52883	46904	0	0
T4	509053	348118	0	0
T5	391096	335250	0	0
T6	1127	1046	0	0
T7	8879	6620	0	0
T8	679756	603746	0	0
T9	72920	56020	0	0
T10	5155	4887	0	0
T11	1272222	622944	0	0
T12	721605	714218	0	0
T13	60334	30080	0	0
T14	0	12488	0	0
T15	0	73080	0	0
T17	89264	42032	0	0
T18	0	161656	0	0
T19	0	114736	0	0
T26	0	101088	0	0
T37	0	57616	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2826	2826	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	913740817	4346633	0	0
T1	1454	200	0	0
T2	108257	832	0	0
T3	47533	453	0	0
T4	509053	5109	0	0
T5	391096	832	0	0
T6	1127	0	0	0
T7	8879	0	0	0
T8	679756	832	0	0
T9	72920	832	0	0
T10	5155	0	0	0
T11	1272222	22394	0	0
T12	1443210	20430	0	0
T13	60334	832	0	0
T14	12488	0	0	0
T17	89264	0	0	0
T18	0	10933	0	0
T25	0	2677	0	0
T26	0	4501	0	0
T27	0	4222	0	0
T28	0	6042	0	0
T30	0	7122	0	0
T31	0	6928	0	0
T38	0	15	0	0
T39	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	913740817	4346633	0	0
T1	1454	200	0	0
T2	108257	832	0	0
T3	47533	453	0	0
T4	509053	5109	0	0
T5	391096	832	0	0
T6	1127	0	0	0
T7	8879	0	0	0
T8	679756	832	0	0
T9	72920	832	0	0
T10	5155	0	0	0
T11	1272222	22394	0	0
T12	1443210	20430	0	0
T13	60334	832	0	0
T14	12488	0	0	0
T17	89264	0	0	0
T18	0	10933	0	0
T25	0	2677	0	0
T26	0	4501	0	0
T27	0	4222	0	0
T28	0	6042	0	0
T30	0	7122	0	0
T31	0	6928	0	0
T38	0	15	0	0
T39	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	913740817	722796143	0	0
T1	1454	1396	0	0
T2	206135	205362	0	0
T3	52883	46904	0	0
T4	509053	348118	0	0
T5	391096	335250	0	0
T6	1127	1046	0	0
T7	8879	6620	0	0
T8	679756	603746	0	0
T9	72920	56020	0	0
T10	5155	4887	0	0
T11	1272222	622944	0	0
T12	721605	714218	0	0
T13	60334	30080	0	0
T14	0	12488	0	0
T15	0	73080	0	0
T17	89264	42032	0	0
T18	0	161656	0	0
T19	0	114736	0	0
T26	0	101088	0	0
T37	0	57616	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	913740817	722796143	0	0
T1	1454	1396	0	0
T2	206135	205362	0	0
T3	52883	46904	0	0
T4	509053	348118	0	0
T5	391096	335250	0	0
T6	1127	1046	0	0
T7	8879	6620	0	0
T8	679756	603746	0	0
T9	72920	56020	0	0
T10	5155	4887	0	0
T11	1272222	622944	0	0
T12	721605	714218	0	0
T13	60334	30080	0	0
T14	0	12488	0	0
T15	0	73080	0	0
T17	89264	42032	0	0
T18	0	161656	0	0
T19	0	114736	0	0
T26	0	101088	0	0
T37	0	57616	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	913740817	4346633	0	0
T1	1454	200	0	0
T2	108257	832	0	0
T3	47533	453	0	0
T4	509053	5109	0	0
T5	391096	832	0	0
T6	1127	0	0	0
T7	8879	0	0	0
T8	679756	832	0	0
T9	72920	832	0	0
T10	5155	0	0	0
T11	1272222	22394	0	0
T12	1443210	20430	0	0
T13	60334	832	0	0
T14	12488	0	0	0
T17	89264	0	0	0
T18	0	10933	0	0
T25	0	2677	0	0
T26	0	4501	0	0
T27	0	4222	0	0
T28	0	6042	0	0
T30	0	7122	0	0
T31	0	6928	0	0
T38	0	15	0	0
T39	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	913740817	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	913740817	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	913740817	4346633	0	0
T1	1454	200	0	0
T2	108257	832	0	0
T3	47533	453	0	0
T4	509053	5109	0	0
T5	391096	832	0	0
T6	1127	0	0	0
T7	8879	0	0	0
T8	679756	832	0	0
T9	72920	832	0	0
T10	5155	0	0	0
T11	1272222	22394	0	0
T12	1443210	20430	0	0
T13	60334	832	0	0
T14	12488	0	0	0
T17	89264	0	0	0
T18	0	10933	0	0
T25	0	2677	0	0
T26	0	4501	0	0
T27	0	4222	0	0
T28	0	6042	0	0
T30	0	7122	0	0
T31	0	6928	0	0
T38	0	15	0	0
T39	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	913740817	4346633	0	0
T1	1454	200	0	0
T2	108257	832	0	0
T3	47533	453	0	0
T4	509053	5109	0	0
T5	391096	832	0	0
T6	1127	0	0	0
T7	8879	0	0	0
T8	679756	832	0	0
T9	72920	832	0	0
T10	5155	0	0	0
T11	1272222	22394	0	0
T12	1443210	20430	0	0
T13	60334	832	0	0
T14	12488	0	0	0
T17	89264	0	0	0
T18	0	10933	0	0
T25	0	2677	0	0
T26	0	4501	0	0
T27	0	4222	0	0
T28	0	6042	0	0
T30	0	7122	0	0
T31	0	6928	0	0
T38	0	15	0	0
T39	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	913740817	4346633	0	0
T1	1454	200	0	0
T2	108257	832	0	0
T3	47533	453	0	0
T4	509053	5109	0	0
T5	391096	832	0	0
T6	1127	0	0	0
T7	8879	0	0	0
T8	679756	832	0	0
T9	72920	832	0	0
T10	5155	0	0	0
T11	1272222	22394	0	0
T12	1443210	20430	0	0
T13	60334	832	0	0
T14	12488	0	0	0
T17	89264	0	0	0
T18	0	10933	0	0
T25	0	2677	0	0
T26	0	4501	0	0
T27	0	4222	0	0
T28	0	6042	0	0
T30	0	7122	0	0
T31	0	6928	0	0
T38	0	15	0	0
T39	0	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	913740817	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	913740817	3	0	942
T40	106403	1	0	1
T41	0	1	0	0
T42	0	1	0	0
T43	332930	0	0	1
T44	49433	0	0	1
T45	22633	0	0	1
T46	113995	0	0	1
T47	47768	0	0	1
T48	5590	0	0	1
T49	681522	0	0	1
T50	380027	0	0	1
T51	12830	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	913740817	722796143	0	0
T1	1454	1396	0	0
T2	206135	205362	0	0
T3	52883	46904	0	0
T4	509053	348118	0	0
T5	391096	335250	0	0
T6	1127	1046	0	0
T7	8879	6620	0	0
T8	679756	603746	0	0
T9	72920	56020	0	0
T10	5155	4887	0	0
T11	1272222	622944	0	0
T12	721605	714218	0	0
T13	60334	30080	0	0
T14	0	12488	0	0
T15	0	73080	0	0
T17	89264	42032	0	0
T18	0	161656	0	0
T19	0	114736	0	0
T26	0	101088	0	0
T37	0	57616	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	913740817	4346633	0	0
T1	1454	200	0	0
T2	108257	832	0	0
T3	47533	453	0	0
T4	509053	5109	0	0
T5	391096	832	0	0
T6	1127	0	0	0
T7	8879	0	0	0
T8	679756	832	0	0
T9	72920	832	0	0
T10	5155	0	0	0
T11	1272222	22394	0	0
T12	1443210	20430	0	0
T13	60334	832	0	0
T14	12488	0	0	0
T17	89264	0	0	0
T18	0	10933	0	0
T25	0	2677	0	0
T26	0	4501	0	0
T27	0	4222	0	0
T28	0	6042	0	0
T30	0	7122	0	0
T31	0	6928	0	0
T38	0	15	0	0
T39	0	8	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T11,T12
1	0	Covered	T3,T11,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T7
1	0	Unreachable
1	1	Covered	T3,T11,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T11,T12
0	0	1	Unreachable
0	0	0	Covered	T3,T4,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T11,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	188963472	42345565	0	0
CheckNGreaterZero_A	942	942	0	0
GntImpliesReady_A	188963472	926125	0	0
GntImpliesValid_A	188963472	926125	0	0
GrantKnown_A	188963472	42345565	0	0
IdxKnown_A	188963472	42345565	0	0
IndexIsCorrect_A	188963472	926125	0	0
LockArbDecision_A	188963472	0	0	0
NoReadyValidNoGrant_A	188963472	0	0	0
ReadyAndValidImplyGrant_A	188963472	926125	0	0
ReqAndReadyImplyGrant_A	188963472	926125	0	0
ReqImpliesValid_A	188963472	926125	0	0
ReqStaysHighUntilGranted0_M	188963472	0	0	0
RoundRobin_A	188963472	0	0	0
ValidKnown_A	188963472	42345565	0	0
gen_data_port_assertion.DataFlow_A	188963472	926125	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	42345565	0	0
T3	5350	4776	0	0
T4	160312	7	0	0
T5	55554	0	0	0
T7	1775	1368	0	0
T8	75332	0	0	0
T9	16743	0	0	0
T11	636111	86496	0	0
T12	721605	119800	0	0
T13	30167	0	0	0
T17	44632	42032	0	0
T18	0	161656	0	0
T19	0	114736	0	0
T26	0	101088	0	0
T37	0	57616	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	926125	0	0
T3	5350	321	0	0
T4	160312	0	0	0
T5	55554	0	0	0
T7	1775	0	0	0
T8	75332	0	0	0
T9	16743	0	0	0
T11	636111	4236	0	0
T12	721605	5460	0	0
T13	30167	0	0	0
T17	44632	0	0	0
T18	0	6641	0	0
T26	0	3442	0	0
T27	0	4090	0	0
T28	0	3133	0	0
T30	0	4370	0	0
T31	0	6928	0	0
T38	0	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	926125	0	0
T3	5350	321	0	0
T4	160312	0	0	0
T5	55554	0	0	0
T7	1775	0	0	0
T8	75332	0	0	0
T9	16743	0	0	0
T11	636111	4236	0	0
T12	721605	5460	0	0
T13	30167	0	0	0
T17	44632	0	0	0
T18	0	6641	0	0
T26	0	3442	0	0
T27	0	4090	0	0
T28	0	3133	0	0
T30	0	4370	0	0
T31	0	6928	0	0
T38	0	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	42345565	0	0
T3	5350	4776	0	0
T4	160312	7	0	0
T5	55554	0	0	0
T7	1775	1368	0	0
T8	75332	0	0	0
T9	16743	0	0	0
T11	636111	86496	0	0
T12	721605	119800	0	0
T13	30167	0	0	0
T17	44632	42032	0	0
T18	0	161656	0	0
T19	0	114736	0	0
T26	0	101088	0	0
T37	0	57616	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	42345565	0	0
T3	5350	4776	0	0
T4	160312	7	0	0
T5	55554	0	0	0
T7	1775	1368	0	0
T8	75332	0	0	0
T9	16743	0	0	0
T11	636111	86496	0	0
T12	721605	119800	0	0
T13	30167	0	0	0
T17	44632	42032	0	0
T18	0	161656	0	0
T19	0	114736	0	0
T26	0	101088	0	0
T37	0	57616	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	926125	0	0
T3	5350	321	0	0
T4	160312	0	0	0
T5	55554	0	0	0
T7	1775	0	0	0
T8	75332	0	0	0
T9	16743	0	0	0
T11	636111	4236	0	0
T12	721605	5460	0	0
T13	30167	0	0	0
T17	44632	0	0	0
T18	0	6641	0	0
T26	0	3442	0	0
T27	0	4090	0	0
T28	0	3133	0	0
T30	0	4370	0	0
T31	0	6928	0	0
T38	0	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	926125	0	0
T3	5350	321	0	0
T4	160312	0	0	0
T5	55554	0	0	0
T7	1775	0	0	0
T8	75332	0	0	0
T9	16743	0	0	0
T11	636111	4236	0	0
T12	721605	5460	0	0
T13	30167	0	0	0
T17	44632	0	0	0
T18	0	6641	0	0
T26	0	3442	0	0
T27	0	4090	0	0
T28	0	3133	0	0
T30	0	4370	0	0
T31	0	6928	0	0
T38	0	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	926125	0	0
T3	5350	321	0	0
T4	160312	0	0	0
T5	55554	0	0	0
T7	1775	0	0	0
T8	75332	0	0	0
T9	16743	0	0	0
T11	636111	4236	0	0
T12	721605	5460	0	0
T13	30167	0	0	0
T17	44632	0	0	0
T18	0	6641	0	0
T26	0	3442	0	0
T27	0	4090	0	0
T28	0	3133	0	0
T30	0	4370	0	0
T31	0	6928	0	0
T38	0	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	926125	0	0
T3	5350	321	0	0
T4	160312	0	0	0
T5	55554	0	0	0
T7	1775	0	0	0
T8	75332	0	0	0
T9	16743	0	0	0
T11	636111	4236	0	0
T12	721605	5460	0	0
T13	30167	0	0	0
T17	44632	0	0	0
T18	0	6641	0	0
T26	0	3442	0	0
T27	0	4090	0	0
T28	0	3133	0	0
T30	0	4370	0	0
T31	0	6928	0	0
T38	0	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	42345565	0	0
T3	5350	4776	0	0
T4	160312	7	0	0
T5	55554	0	0	0
T7	1775	1368	0	0
T8	75332	0	0	0
T9	16743	0	0	0
T11	636111	86496	0	0
T12	721605	119800	0	0
T13	30167	0	0	0
T17	44632	42032	0	0
T18	0	161656	0	0
T19	0	114736	0	0
T26	0	101088	0	0
T37	0	57616	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	926125	0	0
T3	5350	321	0	0
T4	160312	0	0	0
T5	55554	0	0	0
T7	1775	0	0	0
T8	75332	0	0	0
T9	16743	0	0	0
T11	636111	4236	0	0
T12	721605	5460	0	0
T13	30167	0	0	0
T17	44632	0	0	0
T18	0	6641	0	0
T26	0	3442	0	0
T27	0	4090	0	0
T28	0	3133	0	0
T30	0	4370	0	0
T31	0	6928	0	0
T38	0	15	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T11,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T4,T11,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Unreachable
1	1	Covered	T4,T11,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T11,T12
0	0	1	Unreachable
0	0	0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	188963472	144724134	0	0
CheckNGreaterZero_A	942	942	0	0
GntImpliesReady_A	188963472	667081	0	0
GntImpliesValid_A	188963472	667081	0	0
GrantKnown_A	188963472	144724134	0	0
IdxKnown_A	188963472	144724134	0	0
IndexIsCorrect_A	188963472	667081	0	0
LockArbDecision_A	188963472	0	0	0
NoReadyValidNoGrant_A	188963472	0	0	0
ReadyAndValidImplyGrant_A	188963472	667081	0	0
ReqAndReadyImplyGrant_A	188963472	667081	0	0
ReqImpliesValid_A	188963472	667081	0	0
ReqStaysHighUntilGranted0_M	188963472	0	0	0
RoundRobin_A	188963472	0	0	0
ValidKnown_A	188963472	144724134	0	0
gen_data_port_assertion.DataFlow_A	188963472	667081	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	144724134	0	0
T2	97878	97164	0	0
T3	5350	0	0	0
T4	160312	159738	0	0
T5	55554	55332	0	0
T7	1775	0	0	0
T8	75332	74731	0	0
T9	16743	16656	0	0
T11	636111	536448	0	0
T12	0	594418	0	0
T13	30167	30080	0	0
T14	0	12488	0	0
T15	0	73080	0	0
T17	44632	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	667081	0	0
T4	160312	806	0	0
T5	55554	0	0	0
T7	1775	0	0	0
T8	75332	0	0	0
T9	16743	0	0	0
T11	636111	2688	0	0
T12	721605	5570	0	0
T13	30167	0	0	0
T14	12488	0	0	0
T17	44632	0	0	0
T18	0	4292	0	0
T25	0	2677	0	0
T26	0	1059	0	0
T27	0	132	0	0
T28	0	2909	0	0
T30	0	2752	0	0
T39	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	667081	0	0
T4	160312	806	0	0
T5	55554	0	0	0
T7	1775	0	0	0
T8	75332	0	0	0
T9	16743	0	0	0
T11	636111	2688	0	0
T12	721605	5570	0	0
T13	30167	0	0	0
T14	12488	0	0	0
T17	44632	0	0	0
T18	0	4292	0	0
T25	0	2677	0	0
T26	0	1059	0	0
T27	0	132	0	0
T28	0	2909	0	0
T30	0	2752	0	0
T39	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	144724134	0	0
T2	97878	97164	0	0
T3	5350	0	0	0
T4	160312	159738	0	0
T5	55554	55332	0	0
T7	1775	0	0	0
T8	75332	74731	0	0
T9	16743	16656	0	0
T11	636111	536448	0	0
T12	0	594418	0	0
T13	30167	30080	0	0
T14	0	12488	0	0
T15	0	73080	0	0
T17	44632	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	144724134	0	0
T2	97878	97164	0	0
T3	5350	0	0	0
T4	160312	159738	0	0
T5	55554	55332	0	0
T7	1775	0	0	0
T8	75332	74731	0	0
T9	16743	16656	0	0
T11	636111	536448	0	0
T12	0	594418	0	0
T13	30167	30080	0	0
T14	0	12488	0	0
T15	0	73080	0	0
T17	44632	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	667081	0	0
T4	160312	806	0	0
T5	55554	0	0	0
T7	1775	0	0	0
T8	75332	0	0	0
T9	16743	0	0	0
T11	636111	2688	0	0
T12	721605	5570	0	0
T13	30167	0	0	0
T14	12488	0	0	0
T17	44632	0	0	0
T18	0	4292	0	0
T25	0	2677	0	0
T26	0	1059	0	0
T27	0	132	0	0
T28	0	2909	0	0
T30	0	2752	0	0
T39	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	667081	0	0
T4	160312	806	0	0
T5	55554	0	0	0
T7	1775	0	0	0
T8	75332	0	0	0
T9	16743	0	0	0
T11	636111	2688	0	0
T12	721605	5570	0	0
T13	30167	0	0	0
T14	12488	0	0	0
T17	44632	0	0	0
T18	0	4292	0	0
T25	0	2677	0	0
T26	0	1059	0	0
T27	0	132	0	0
T28	0	2909	0	0
T30	0	2752	0	0
T39	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	667081	0	0
T4	160312	806	0	0
T5	55554	0	0	0
T7	1775	0	0	0
T8	75332	0	0	0
T9	16743	0	0	0
T11	636111	2688	0	0
T12	721605	5570	0	0
T13	30167	0	0	0
T14	12488	0	0	0
T17	44632	0	0	0
T18	0	4292	0	0
T25	0	2677	0	0
T26	0	1059	0	0
T27	0	132	0	0
T28	0	2909	0	0
T30	0	2752	0	0
T39	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	667081	0	0
T4	160312	806	0	0
T5	55554	0	0	0
T7	1775	0	0	0
T8	75332	0	0	0
T9	16743	0	0	0
T11	636111	2688	0	0
T12	721605	5570	0	0
T13	30167	0	0	0
T14	12488	0	0	0
T17	44632	0	0	0
T18	0	4292	0	0
T25	0	2677	0	0
T26	0	1059	0	0
T27	0	132	0	0
T28	0	2909	0	0
T30	0	2752	0	0
T39	0	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	144724134	0	0
T2	97878	97164	0	0
T3	5350	0	0	0
T4	160312	159738	0	0
T5	55554	55332	0	0
T7	1775	0	0	0
T8	75332	74731	0	0
T9	16743	16656	0	0
T11	636111	536448	0	0
T12	0	594418	0	0
T13	30167	30080	0	0
T14	0	12488	0	0
T15	0	73080	0	0
T17	44632	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188963472	667081	0	0
T4	160312	806	0	0
T5	55554	0	0	0
T7	1775	0	0	0
T8	75332	0	0	0
T9	16743	0	0	0
T11	636111	2688	0	0
T12	721605	5570	0	0
T13	30167	0	0	0
T14	12488	0	0	0
T17	44632	0	0	0
T18	0	4292	0	0
T25	0	2677	0	0
T26	0	1059	0	0
T27	0	132	0	0
T28	0	2909	0	0
T30	0	2752	0	0
T39	0	8	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	535813873	535726444	0	0
CheckNGreaterZero_A	942	942	0	0
GntImpliesReady_A	535813873	2753427	0	0
GntImpliesValid_A	535813873	2753427	0	0
GrantKnown_A	535813873	535726444	0	0
IdxKnown_A	535813873	535726444	0	0
IndexIsCorrect_A	535813873	2753427	0	0
LockArbDecision_A	535813873	0	0	0
NoReadyValidNoGrant_A	535813873	0	0	0
ReadyAndValidImplyGrant_A	535813873	2753427	0	0
ReqAndReadyImplyGrant_A	535813873	2753427	0	0
ReqImpliesValid_A	535813873	2753427	0	0
ReqStaysHighUntilGranted0_M	535813873	0	0	0
RoundRobin_A	535813873	3	0	942
ValidKnown_A	535813873	535726444	0	0
gen_data_port_assertion.DataFlow_A	535813873	2753427	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535813873	535726444	0	0
T1	1454	1396	0	0
T2	108257	108198	0	0
T3	42183	42128	0	0
T4	188429	188373	0	0
T5	279988	279918	0	0
T6	1127	1046	0	0
T7	5329	5252	0	0
T8	529092	529015	0	0
T9	39434	39364	0	0
T10	5155	4887	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535813873	2753427	0	0
T1	1454	200	0	0
T2	108257	832	0	0
T3	42183	132	0	0
T4	188429	4303	0	0
T5	279988	832	0	0
T6	1127	0	0	0
T7	5329	0	0	0
T8	529092	832	0	0
T9	39434	832	0	0
T10	5155	0	0	0
T11	0	15470	0	0
T12	0	9400	0	0
T13	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535813873	2753427	0	0
T1	1454	200	0	0
T2	108257	832	0	0
T3	42183	132	0	0
T4	188429	4303	0	0
T5	279988	832	0	0
T6	1127	0	0	0
T7	5329	0	0	0
T8	529092	832	0	0
T9	39434	832	0	0
T10	5155	0	0	0
T11	0	15470	0	0
T12	0	9400	0	0
T13	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535813873	535726444	0	0
T1	1454	1396	0	0
T2	108257	108198	0	0
T3	42183	42128	0	0
T4	188429	188373	0	0
T5	279988	279918	0	0
T6	1127	1046	0	0
T7	5329	5252	0	0
T8	529092	529015	0	0
T9	39434	39364	0	0
T10	5155	4887	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535813873	535726444	0	0
T1	1454	1396	0	0
T2	108257	108198	0	0
T3	42183	42128	0	0
T4	188429	188373	0	0
T5	279988	279918	0	0
T6	1127	1046	0	0
T7	5329	5252	0	0
T8	529092	529015	0	0
T9	39434	39364	0	0
T10	5155	4887	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535813873	2753427	0	0
T1	1454	200	0	0
T2	108257	832	0	0
T3	42183	132	0	0
T4	188429	4303	0	0
T5	279988	832	0	0
T6	1127	0	0	0
T7	5329	0	0	0
T8	529092	832	0	0
T9	39434	832	0	0
T10	5155	0	0	0
T11	0	15470	0	0
T12	0	9400	0	0
T13	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535813873	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535813873	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535813873	2753427	0	0
T1	1454	200	0	0
T2	108257	832	0	0
T3	42183	132	0	0
T4	188429	4303	0	0
T5	279988	832	0	0
T6	1127	0	0	0
T7	5329	0	0	0
T8	529092	832	0	0
T9	39434	832	0	0
T10	5155	0	0	0
T11	0	15470	0	0
T12	0	9400	0	0
T13	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535813873	2753427	0	0
T1	1454	200	0	0
T2	108257	832	0	0
T3	42183	132	0	0
T4	188429	4303	0	0
T5	279988	832	0	0
T6	1127	0	0	0
T7	5329	0	0	0
T8	529092	832	0	0
T9	39434	832	0	0
T10	5155	0	0	0
T11	0	15470	0	0
T12	0	9400	0	0
T13	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535813873	2753427	0	0
T1	1454	200	0	0
T2	108257	832	0	0
T3	42183	132	0	0
T4	188429	4303	0	0
T5	279988	832	0	0
T6	1127	0	0	0
T7	5329	0	0	0
T8	529092	832	0	0
T9	39434	832	0	0
T10	5155	0	0	0
T11	0	15470	0	0
T12	0	9400	0	0
T13	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	535813873	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535813873	3	0	942
T40	106403	1	0	1
T41	0	1	0	0
T42	0	1	0	0
T43	332930	0	0	1
T44	49433	0	0	1
T45	22633	0	0	1
T46	113995	0	0	1
T47	47768	0	0	1
T48	5590	0	0	1
T49	681522	0	0	1
T50	380027	0	0	1
T51	12830	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535813873	535726444	0	0
T1	1454	1396	0	0
T2	108257	108198	0	0
T3	42183	42128	0	0
T4	188429	188373	0	0
T5	279988	279918	0	0
T6	1127	1046	0	0
T7	5329	5252	0	0
T8	529092	529015	0	0
T9	39434	39364	0	0
T10	5155	4887	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535813873	2753427	0	0
T1	1454	200	0	0
T2	108257	832	0	0
T3	42183	132	0	0
T4	188429	4303	0	0
T5	279988	832	0	0
T6	1127	0	0	0
T7	5329	0	0	0
T8	529092	832	0	0
T9	39434	832	0	0
T10	5155	0	0	0
T11	0	15470	0	0
T12	0	9400	0	0
T13	0	832	0	0