Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
3775 |
0 |
0 |
T86 |
29600 |
5 |
0 |
0 |
T87 |
4922 |
241 |
0 |
0 |
T88 |
33958 |
1 |
0 |
0 |
T89 |
6426 |
327 |
0 |
0 |
T90 |
3695 |
225 |
0 |
0 |
T91 |
70577 |
4 |
0 |
0 |
T93 |
16137 |
187 |
0 |
0 |
T94 |
4940 |
8 |
0 |
0 |
T99 |
5290 |
7 |
0 |
0 |
T100 |
28846 |
5 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
1060 |
0 |
0 |
T78 |
3311 |
5 |
0 |
0 |
T88 |
33958 |
6 |
0 |
0 |
T91 |
70577 |
76 |
0 |
0 |
T104 |
7540 |
2 |
0 |
0 |
T107 |
7547 |
5 |
0 |
0 |
T130 |
12222 |
3 |
0 |
0 |
T131 |
71173 |
72 |
0 |
0 |
T132 |
12641 |
37 |
0 |
0 |
T133 |
13215 |
20 |
0 |
0 |
T134 |
95099 |
96 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
1182 |
0 |
0 |
T78 |
3311 |
9 |
0 |
0 |
T88 |
33958 |
25 |
0 |
0 |
T91 |
70577 |
81 |
0 |
0 |
T104 |
7540 |
16 |
0 |
0 |
T106 |
4394 |
8 |
0 |
0 |
T107 |
7547 |
15 |
0 |
0 |
T130 |
12222 |
24 |
0 |
0 |
T131 |
71173 |
82 |
0 |
0 |
T132 |
12641 |
23 |
0 |
0 |
T133 |
13215 |
36 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
1605 |
0 |
0 |
T78 |
3311 |
4 |
0 |
0 |
T88 |
33958 |
54 |
0 |
0 |
T91 |
70577 |
148 |
0 |
0 |
T104 |
7540 |
23 |
0 |
0 |
T106 |
4394 |
1 |
0 |
0 |
T107 |
7547 |
11 |
0 |
0 |
T130 |
12222 |
35 |
0 |
0 |
T131 |
71173 |
113 |
0 |
0 |
T132 |
12641 |
27 |
0 |
0 |
T133 |
13215 |
56 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
7606 |
0 |
0 |
T78 |
3311 |
9 |
0 |
0 |
T88 |
33958 |
333 |
0 |
0 |
T91 |
70577 |
1082 |
0 |
0 |
T104 |
7540 |
219 |
0 |
0 |
T107 |
7547 |
249 |
0 |
0 |
T130 |
12222 |
50 |
0 |
0 |
T131 |
71173 |
1479 |
0 |
0 |
T132 |
12641 |
25 |
0 |
0 |
T133 |
13215 |
40 |
0 |
0 |
T134 |
95099 |
1726 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
7497 |
0 |
0 |
T78 |
3311 |
4 |
0 |
0 |
T88 |
33958 |
320 |
0 |
0 |
T91 |
70577 |
1245 |
0 |
0 |
T104 |
7540 |
115 |
0 |
0 |
T106 |
4394 |
138 |
0 |
0 |
T107 |
7547 |
214 |
0 |
0 |
T130 |
12222 |
19 |
0 |
0 |
T131 |
71173 |
919 |
0 |
0 |
T132 |
12641 |
35 |
0 |
0 |
T133 |
13215 |
22 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
7100 |
0 |
0 |
T78 |
3311 |
4 |
0 |
0 |
T88 |
33958 |
545 |
0 |
0 |
T91 |
70577 |
1436 |
0 |
0 |
T104 |
7540 |
6 |
0 |
0 |
T106 |
4394 |
98 |
0 |
0 |
T107 |
7547 |
205 |
0 |
0 |
T130 |
12222 |
5 |
0 |
0 |
T131 |
71173 |
1162 |
0 |
0 |
T132 |
12641 |
16 |
0 |
0 |
T133 |
13215 |
112 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
6961 |
0 |
0 |
T78 |
3311 |
5 |
0 |
0 |
T88 |
33958 |
306 |
0 |
0 |
T91 |
70577 |
1299 |
0 |
0 |
T104 |
7540 |
142 |
0 |
0 |
T106 |
4394 |
105 |
0 |
0 |
T107 |
7547 |
115 |
0 |
0 |
T130 |
12222 |
32 |
0 |
0 |
T131 |
71173 |
925 |
0 |
0 |
T132 |
12641 |
42 |
0 |
0 |
T133 |
13215 |
23 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
7205 |
0 |
0 |
T78 |
3311 |
7 |
0 |
0 |
T88 |
33958 |
487 |
0 |
0 |
T91 |
70577 |
1307 |
0 |
0 |
T104 |
7540 |
234 |
0 |
0 |
T106 |
4394 |
5 |
0 |
0 |
T130 |
12222 |
12 |
0 |
0 |
T131 |
71173 |
919 |
0 |
0 |
T132 |
12641 |
49 |
0 |
0 |
T133 |
13215 |
33 |
0 |
0 |
T134 |
95099 |
1475 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
8122 |
0 |
0 |
T78 |
3311 |
7 |
0 |
0 |
T88 |
33958 |
340 |
0 |
0 |
T91 |
70577 |
1696 |
0 |
0 |
T104 |
7540 |
210 |
0 |
0 |
T106 |
4394 |
117 |
0 |
0 |
T107 |
7547 |
135 |
0 |
0 |
T130 |
12222 |
14 |
0 |
0 |
T131 |
71173 |
1784 |
0 |
0 |
T132 |
12641 |
23 |
0 |
0 |
T133 |
13215 |
26 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
7772 |
0 |
0 |
T78 |
3311 |
4 |
0 |
0 |
T88 |
33958 |
458 |
0 |
0 |
T91 |
70577 |
1151 |
0 |
0 |
T104 |
7540 |
118 |
0 |
0 |
T106 |
4394 |
1 |
0 |
0 |
T107 |
7547 |
17 |
0 |
0 |
T130 |
12222 |
28 |
0 |
0 |
T131 |
71173 |
1118 |
0 |
0 |
T132 |
12641 |
40 |
0 |
0 |
T133 |
13215 |
26 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
6277 |
0 |
0 |
T78 |
3311 |
10 |
0 |
0 |
T88 |
33958 |
379 |
0 |
0 |
T91 |
70577 |
871 |
0 |
0 |
T104 |
7540 |
109 |
0 |
0 |
T106 |
4394 |
141 |
0 |
0 |
T107 |
7547 |
118 |
0 |
0 |
T130 |
12222 |
13 |
0 |
0 |
T131 |
71173 |
1369 |
0 |
0 |
T132 |
12641 |
15 |
0 |
0 |
T133 |
13215 |
21 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
3317 |
0 |
0 |
T78 |
3311 |
2 |
0 |
0 |
T88 |
33958 |
100 |
0 |
0 |
T91 |
70577 |
672 |
0 |
0 |
T93 |
16137 |
2 |
0 |
0 |
T104 |
7540 |
52 |
0 |
0 |
T107 |
7547 |
51 |
0 |
0 |
T130 |
12222 |
29 |
0 |
0 |
T131 |
71173 |
560 |
0 |
0 |
T132 |
12641 |
7 |
0 |
0 |
T133 |
13215 |
17 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
3406 |
0 |
0 |
T78 |
3311 |
6 |
0 |
0 |
T88 |
33958 |
81 |
0 |
0 |
T91 |
70577 |
422 |
0 |
0 |
T104 |
7540 |
72 |
0 |
0 |
T106 |
4394 |
31 |
0 |
0 |
T107 |
7547 |
108 |
0 |
0 |
T130 |
12222 |
43 |
0 |
0 |
T131 |
71173 |
502 |
0 |
0 |
T132 |
12641 |
3 |
0 |
0 |
T133 |
13215 |
31 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
4083 |
0 |
0 |
T78 |
3311 |
1 |
0 |
0 |
T88 |
33958 |
215 |
0 |
0 |
T91 |
70577 |
599 |
0 |
0 |
T104 |
7540 |
9 |
0 |
0 |
T106 |
4394 |
51 |
0 |
0 |
T107 |
7547 |
88 |
0 |
0 |
T130 |
12222 |
36 |
0 |
0 |
T131 |
71173 |
705 |
0 |
0 |
T132 |
12641 |
12 |
0 |
0 |
T133 |
13215 |
25 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
3801 |
0 |
0 |
T78 |
3311 |
13 |
0 |
0 |
T88 |
33958 |
112 |
0 |
0 |
T91 |
70577 |
556 |
0 |
0 |
T104 |
7540 |
48 |
0 |
0 |
T106 |
4394 |
5 |
0 |
0 |
T107 |
7547 |
7 |
0 |
0 |
T130 |
12222 |
35 |
0 |
0 |
T131 |
71173 |
609 |
0 |
0 |
T132 |
12641 |
21 |
0 |
0 |
T133 |
13215 |
43 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
3464 |
0 |
0 |
T78 |
3311 |
8 |
0 |
0 |
T88 |
33958 |
153 |
0 |
0 |
T91 |
70577 |
421 |
0 |
0 |
T104 |
7540 |
40 |
0 |
0 |
T106 |
4394 |
1 |
0 |
0 |
T107 |
7547 |
35 |
0 |
0 |
T130 |
12222 |
29 |
0 |
0 |
T131 |
71173 |
705 |
0 |
0 |
T132 |
12641 |
70 |
0 |
0 |
T133 |
13215 |
67 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
3855 |
0 |
0 |
T78 |
3311 |
11 |
0 |
0 |
T88 |
33958 |
148 |
0 |
0 |
T91 |
70577 |
372 |
0 |
0 |
T104 |
7540 |
95 |
0 |
0 |
T106 |
4394 |
5 |
0 |
0 |
T107 |
7547 |
44 |
0 |
0 |
T130 |
12222 |
55 |
0 |
0 |
T131 |
71173 |
676 |
0 |
0 |
T132 |
12641 |
23 |
0 |
0 |
T133 |
13215 |
1 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
3467 |
0 |
0 |
T78 |
3311 |
4 |
0 |
0 |
T88 |
33958 |
116 |
0 |
0 |
T91 |
70577 |
551 |
0 |
0 |
T104 |
7540 |
3 |
0 |
0 |
T106 |
4394 |
2 |
0 |
0 |
T107 |
7547 |
32 |
0 |
0 |
T130 |
12222 |
31 |
0 |
0 |
T131 |
71173 |
637 |
0 |
0 |
T132 |
12641 |
25 |
0 |
0 |
T133 |
13215 |
34 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
3290 |
0 |
0 |
T78 |
3311 |
2 |
0 |
0 |
T88 |
33958 |
154 |
0 |
0 |
T91 |
70577 |
474 |
0 |
0 |
T104 |
7540 |
43 |
0 |
0 |
T106 |
4394 |
36 |
0 |
0 |
T107 |
7547 |
13 |
0 |
0 |
T130 |
12222 |
50 |
0 |
0 |
T131 |
71173 |
515 |
0 |
0 |
T132 |
12641 |
6 |
0 |
0 |
T133 |
13215 |
78 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
3664 |
0 |
0 |
T78 |
3311 |
6 |
0 |
0 |
T88 |
33958 |
122 |
0 |
0 |
T91 |
70577 |
500 |
0 |
0 |
T104 |
7540 |
76 |
0 |
0 |
T106 |
4394 |
36 |
0 |
0 |
T107 |
7547 |
32 |
0 |
0 |
T131 |
71173 |
548 |
0 |
0 |
T132 |
12641 |
31 |
0 |
0 |
T133 |
13215 |
58 |
0 |
0 |
T134 |
95099 |
881 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
3858 |
0 |
0 |
T78 |
3311 |
6 |
0 |
0 |
T88 |
33958 |
218 |
0 |
0 |
T91 |
70577 |
384 |
0 |
0 |
T104 |
7540 |
6 |
0 |
0 |
T106 |
4394 |
56 |
0 |
0 |
T107 |
7547 |
114 |
0 |
0 |
T130 |
12222 |
45 |
0 |
0 |
T131 |
71173 |
410 |
0 |
0 |
T132 |
12641 |
49 |
0 |
0 |
T133 |
13215 |
70 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
3861 |
0 |
0 |
T78 |
3311 |
7 |
0 |
0 |
T88 |
33958 |
93 |
0 |
0 |
T91 |
70577 |
320 |
0 |
0 |
T104 |
7540 |
44 |
0 |
0 |
T106 |
4394 |
4 |
0 |
0 |
T107 |
7547 |
44 |
0 |
0 |
T130 |
12222 |
24 |
0 |
0 |
T131 |
71173 |
648 |
0 |
0 |
T132 |
12641 |
28 |
0 |
0 |
T133 |
13215 |
48 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
3405 |
0 |
0 |
T78 |
3311 |
10 |
0 |
0 |
T88 |
33958 |
156 |
0 |
0 |
T91 |
70577 |
497 |
0 |
0 |
T104 |
7540 |
73 |
0 |
0 |
T106 |
4394 |
4 |
0 |
0 |
T107 |
7547 |
32 |
0 |
0 |
T130 |
12222 |
19 |
0 |
0 |
T131 |
71173 |
352 |
0 |
0 |
T132 |
12641 |
2 |
0 |
0 |
T133 |
13215 |
17 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
3412 |
0 |
0 |
T78 |
3311 |
5 |
0 |
0 |
T88 |
33958 |
97 |
0 |
0 |
T91 |
70577 |
532 |
0 |
0 |
T104 |
7540 |
64 |
0 |
0 |
T106 |
4394 |
3 |
0 |
0 |
T107 |
7547 |
111 |
0 |
0 |
T130 |
12222 |
32 |
0 |
0 |
T131 |
71173 |
356 |
0 |
0 |
T132 |
12641 |
33 |
0 |
0 |
T133 |
13215 |
11 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
3612 |
0 |
0 |
T78 |
3311 |
3 |
0 |
0 |
T88 |
33958 |
130 |
0 |
0 |
T91 |
70577 |
559 |
0 |
0 |
T93 |
16137 |
3 |
0 |
0 |
T104 |
7540 |
30 |
0 |
0 |
T106 |
4394 |
33 |
0 |
0 |
T107 |
7547 |
49 |
0 |
0 |
T130 |
12222 |
9 |
0 |
0 |
T131 |
71173 |
570 |
0 |
0 |
T132 |
12641 |
46 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
3411 |
0 |
0 |
T78 |
3311 |
12 |
0 |
0 |
T88 |
33958 |
164 |
0 |
0 |
T91 |
70577 |
540 |
0 |
0 |
T104 |
7540 |
56 |
0 |
0 |
T106 |
4394 |
44 |
0 |
0 |
T107 |
7547 |
58 |
0 |
0 |
T130 |
12222 |
19 |
0 |
0 |
T131 |
71173 |
635 |
0 |
0 |
T132 |
12641 |
14 |
0 |
0 |
T133 |
13215 |
38 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
3850 |
0 |
0 |
T88 |
33958 |
171 |
0 |
0 |
T91 |
70577 |
684 |
0 |
0 |
T104 |
7540 |
10 |
0 |
0 |
T106 |
4394 |
29 |
0 |
0 |
T107 |
7547 |
4 |
0 |
0 |
T130 |
12222 |
5 |
0 |
0 |
T131 |
71173 |
609 |
0 |
0 |
T132 |
12641 |
19 |
0 |
0 |
T133 |
13215 |
42 |
0 |
0 |
T134 |
95099 |
927 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
3650 |
0 |
0 |
T78 |
3311 |
6 |
0 |
0 |
T88 |
33958 |
100 |
0 |
0 |
T91 |
70577 |
607 |
0 |
0 |
T104 |
7540 |
47 |
0 |
0 |
T106 |
4394 |
46 |
0 |
0 |
T107 |
7547 |
79 |
0 |
0 |
T130 |
12222 |
26 |
0 |
0 |
T131 |
71173 |
482 |
0 |
0 |
T132 |
12641 |
50 |
0 |
0 |
T133 |
13215 |
82 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
3827 |
0 |
0 |
T78 |
3311 |
6 |
0 |
0 |
T88 |
33958 |
144 |
0 |
0 |
T91 |
70577 |
552 |
0 |
0 |
T104 |
7540 |
47 |
0 |
0 |
T106 |
4394 |
49 |
0 |
0 |
T107 |
7547 |
87 |
0 |
0 |
T130 |
12222 |
2 |
0 |
0 |
T131 |
71173 |
520 |
0 |
0 |
T132 |
12641 |
7 |
0 |
0 |
T133 |
13215 |
49 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
3784 |
0 |
0 |
T78 |
3311 |
8 |
0 |
0 |
T88 |
33958 |
47 |
0 |
0 |
T91 |
70577 |
556 |
0 |
0 |
T104 |
7540 |
96 |
0 |
0 |
T107 |
7547 |
80 |
0 |
0 |
T130 |
12222 |
38 |
0 |
0 |
T131 |
71173 |
503 |
0 |
0 |
T132 |
12641 |
28 |
0 |
0 |
T133 |
13215 |
71 |
0 |
0 |
T134 |
95099 |
766 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
3608 |
0 |
0 |
T78 |
3311 |
6 |
0 |
0 |
T88 |
33958 |
186 |
0 |
0 |
T91 |
70577 |
473 |
0 |
0 |
T104 |
7540 |
7 |
0 |
0 |
T106 |
4394 |
47 |
0 |
0 |
T107 |
7547 |
91 |
0 |
0 |
T130 |
12222 |
4 |
0 |
0 |
T131 |
71173 |
601 |
0 |
0 |
T132 |
12641 |
6 |
0 |
0 |
T133 |
13215 |
64 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
3786 |
0 |
0 |
T78 |
3311 |
8 |
0 |
0 |
T88 |
33958 |
144 |
0 |
0 |
T91 |
70577 |
527 |
0 |
0 |
T104 |
7540 |
4 |
0 |
0 |
T107 |
7547 |
35 |
0 |
0 |
T130 |
12222 |
6 |
0 |
0 |
T131 |
71173 |
482 |
0 |
0 |
T132 |
12641 |
35 |
0 |
0 |
T133 |
13215 |
91 |
0 |
0 |
T134 |
95099 |
941 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
3701 |
0 |
0 |
T78 |
3311 |
12 |
0 |
0 |
T88 |
33958 |
200 |
0 |
0 |
T91 |
70577 |
551 |
0 |
0 |
T104 |
7540 |
8 |
0 |
0 |
T106 |
4394 |
5 |
0 |
0 |
T107 |
7547 |
2 |
0 |
0 |
T130 |
12222 |
29 |
0 |
0 |
T131 |
71173 |
447 |
0 |
0 |
T132 |
12641 |
39 |
0 |
0 |
T133 |
13215 |
39 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
3294 |
0 |
0 |
T78 |
3311 |
4 |
0 |
0 |
T88 |
33958 |
179 |
0 |
0 |
T91 |
70577 |
500 |
0 |
0 |
T101 |
5007 |
4 |
0 |
0 |
T104 |
7540 |
16 |
0 |
0 |
T106 |
4394 |
1 |
0 |
0 |
T107 |
7547 |
42 |
0 |
0 |
T130 |
12222 |
31 |
0 |
0 |
T131 |
71173 |
580 |
0 |
0 |
T132 |
12641 |
20 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
3475 |
0 |
0 |
T78 |
3311 |
7 |
0 |
0 |
T88 |
33958 |
160 |
0 |
0 |
T91 |
70577 |
487 |
0 |
0 |
T104 |
7540 |
42 |
0 |
0 |
T106 |
4394 |
3 |
0 |
0 |
T107 |
7547 |
71 |
0 |
0 |
T130 |
12222 |
11 |
0 |
0 |
T131 |
71173 |
472 |
0 |
0 |
T132 |
12641 |
49 |
0 |
0 |
T133 |
13215 |
27 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
1397 |
0 |
0 |
T78 |
3311 |
1 |
0 |
0 |
T88 |
33958 |
10 |
0 |
0 |
T91 |
70577 |
100 |
0 |
0 |
T104 |
7540 |
22 |
0 |
0 |
T106 |
4394 |
8 |
0 |
0 |
T130 |
12222 |
39 |
0 |
0 |
T131 |
71173 |
100 |
0 |
0 |
T132 |
12641 |
32 |
0 |
0 |
T133 |
13215 |
74 |
0 |
0 |
T134 |
95099 |
155 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
1432 |
0 |
0 |
T78 |
3311 |
6 |
0 |
0 |
T88 |
33958 |
26 |
0 |
0 |
T91 |
70577 |
133 |
0 |
0 |
T104 |
7540 |
11 |
0 |
0 |
T106 |
4394 |
7 |
0 |
0 |
T107 |
7547 |
16 |
0 |
0 |
T130 |
12222 |
30 |
0 |
0 |
T131 |
71173 |
128 |
0 |
0 |
T132 |
12641 |
37 |
0 |
0 |
T133 |
13215 |
44 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
1469 |
0 |
0 |
T78 |
3311 |
9 |
0 |
0 |
T88 |
33958 |
57 |
0 |
0 |
T91 |
70577 |
94 |
0 |
0 |
T104 |
7540 |
11 |
0 |
0 |
T106 |
4394 |
5 |
0 |
0 |
T107 |
7547 |
14 |
0 |
0 |
T130 |
12222 |
38 |
0 |
0 |
T131 |
71173 |
113 |
0 |
0 |
T132 |
12641 |
29 |
0 |
0 |
T133 |
13215 |
49 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
1378 |
0 |
0 |
T78 |
3311 |
2 |
0 |
0 |
T88 |
33958 |
24 |
0 |
0 |
T91 |
70577 |
126 |
0 |
0 |
T104 |
7540 |
15 |
0 |
0 |
T107 |
7547 |
14 |
0 |
0 |
T130 |
12222 |
17 |
0 |
0 |
T131 |
71173 |
92 |
0 |
0 |
T132 |
12641 |
40 |
0 |
0 |
T133 |
13215 |
44 |
0 |
0 |
T134 |
95099 |
163 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
1793 |
0 |
0 |
T78 |
3311 |
5 |
0 |
0 |
T88 |
33958 |
27 |
0 |
0 |
T91 |
70577 |
258 |
0 |
0 |
T104 |
7540 |
23 |
0 |
0 |
T106 |
4394 |
5 |
0 |
0 |
T107 |
7547 |
10 |
0 |
0 |
T130 |
12222 |
7 |
0 |
0 |
T131 |
71173 |
147 |
0 |
0 |
T132 |
12641 |
18 |
0 |
0 |
T133 |
13215 |
23 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
3651 |
0 |
0 |
T20 |
254215 |
0 |
0 |
0 |
T21 |
0 |
31 |
0 |
0 |
T23 |
1724 |
0 |
0 |
0 |
T31 |
870691 |
18 |
0 |
0 |
T32 |
157858 |
0 |
0 |
0 |
T40 |
0 |
4 |
0 |
0 |
T57 |
138964 |
66 |
0 |
0 |
T58 |
0 |
16 |
0 |
0 |
T102 |
531436 |
0 |
0 |
0 |
T121 |
6132 |
0 |
0 |
0 |
T135 |
0 |
14 |
0 |
0 |
T136 |
0 |
70 |
0 |
0 |
T137 |
0 |
7 |
0 |
0 |
T138 |
0 |
38 |
0 |
0 |
T139 |
0 |
10 |
0 |
0 |
T140 |
54082 |
0 |
0 |
0 |
T141 |
27033 |
0 |
0 |
0 |
T142 |
200698 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
1400 |
0 |
0 |
T78 |
3311 |
7 |
0 |
0 |
T88 |
33958 |
27 |
0 |
0 |
T91 |
70577 |
148 |
0 |
0 |
T104 |
7540 |
5 |
0 |
0 |
T106 |
4394 |
5 |
0 |
0 |
T107 |
7547 |
8 |
0 |
0 |
T130 |
12222 |
37 |
0 |
0 |
T131 |
71173 |
106 |
0 |
0 |
T132 |
12641 |
23 |
0 |
0 |
T133 |
13215 |
47 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
1478 |
0 |
0 |
T78 |
3311 |
9 |
0 |
0 |
T88 |
33958 |
30 |
0 |
0 |
T91 |
70577 |
103 |
0 |
0 |
T104 |
7540 |
10 |
0 |
0 |
T106 |
4394 |
6 |
0 |
0 |
T107 |
7547 |
13 |
0 |
0 |
T130 |
12222 |
8 |
0 |
0 |
T131 |
71173 |
123 |
0 |
0 |
T132 |
12641 |
17 |
0 |
0 |
T133 |
13215 |
49 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
1162 |
0 |
0 |
T78 |
3311 |
5 |
0 |
0 |
T88 |
33958 |
34 |
0 |
0 |
T91 |
70577 |
117 |
0 |
0 |
T104 |
7540 |
6 |
0 |
0 |
T106 |
4394 |
7 |
0 |
0 |
T130 |
12222 |
44 |
0 |
0 |
T131 |
71173 |
68 |
0 |
0 |
T132 |
12641 |
2 |
0 |
0 |
T133 |
13215 |
3 |
0 |
0 |
T134 |
95099 |
95 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
1230 |
0 |
0 |
T78 |
3311 |
1 |
0 |
0 |
T88 |
33958 |
7 |
0 |
0 |
T91 |
70577 |
78 |
0 |
0 |
T104 |
7540 |
10 |
0 |
0 |
T106 |
4394 |
1 |
0 |
0 |
T107 |
7547 |
9 |
0 |
0 |
T130 |
12222 |
6 |
0 |
0 |
T131 |
71173 |
83 |
0 |
0 |
T132 |
12641 |
28 |
0 |
0 |
T133 |
13215 |
78 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
1125 |
0 |
0 |
T78 |
3311 |
5 |
0 |
0 |
T88 |
33958 |
28 |
0 |
0 |
T91 |
70577 |
86 |
0 |
0 |
T104 |
7540 |
14 |
0 |
0 |
T106 |
4394 |
3 |
0 |
0 |
T107 |
7547 |
3 |
0 |
0 |
T130 |
12222 |
23 |
0 |
0 |
T131 |
71173 |
54 |
0 |
0 |
T132 |
12641 |
20 |
0 |
0 |
T133 |
13215 |
59 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
1187 |
0 |
0 |
T78 |
3311 |
8 |
0 |
0 |
T88 |
33958 |
12 |
0 |
0 |
T91 |
70577 |
63 |
0 |
0 |
T104 |
7540 |
6 |
0 |
0 |
T106 |
4394 |
3 |
0 |
0 |
T107 |
7547 |
8 |
0 |
0 |
T130 |
12222 |
46 |
0 |
0 |
T131 |
71173 |
101 |
0 |
0 |
T132 |
12641 |
10 |
0 |
0 |
T133 |
13215 |
32 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
1860 |
0 |
0 |
T78 |
3311 |
2 |
0 |
0 |
T88 |
33958 |
101 |
0 |
0 |
T91 |
70577 |
176 |
0 |
0 |
T106 |
4394 |
24 |
0 |
0 |
T107 |
7547 |
9 |
0 |
0 |
T130 |
12222 |
20 |
0 |
0 |
T131 |
71173 |
228 |
0 |
0 |
T132 |
12641 |
8 |
0 |
0 |
T133 |
13215 |
58 |
0 |
0 |
T134 |
95099 |
263 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
1271 |
0 |
0 |
T78 |
3311 |
7 |
0 |
0 |
T88 |
33958 |
29 |
0 |
0 |
T91 |
70577 |
68 |
0 |
0 |
T104 |
7540 |
7 |
0 |
0 |
T106 |
4394 |
3 |
0 |
0 |
T107 |
7547 |
7 |
0 |
0 |
T130 |
12222 |
23 |
0 |
0 |
T131 |
71173 |
65 |
0 |
0 |
T132 |
12641 |
49 |
0 |
0 |
T133 |
13215 |
42 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
1999 |
0 |
0 |
T78 |
3311 |
13 |
0 |
0 |
T88 |
33958 |
50 |
0 |
0 |
T91 |
70577 |
217 |
0 |
0 |
T104 |
7540 |
27 |
0 |
0 |
T106 |
4394 |
25 |
0 |
0 |
T107 |
7547 |
11 |
0 |
0 |
T130 |
12222 |
53 |
0 |
0 |
T131 |
71173 |
302 |
0 |
0 |
T132 |
12641 |
37 |
0 |
0 |
T133 |
13215 |
51 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
1318 |
0 |
0 |
T78 |
3311 |
4 |
0 |
0 |
T88 |
33958 |
31 |
0 |
0 |
T91 |
70577 |
144 |
0 |
0 |
T104 |
7540 |
5 |
0 |
0 |
T106 |
4394 |
5 |
0 |
0 |
T107 |
7547 |
9 |
0 |
0 |
T130 |
12222 |
17 |
0 |
0 |
T131 |
71173 |
108 |
0 |
0 |
T132 |
12641 |
23 |
0 |
0 |
T133 |
13215 |
51 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
1113 |
0 |
0 |
T78 |
3311 |
4 |
0 |
0 |
T88 |
33958 |
11 |
0 |
0 |
T91 |
70577 |
58 |
0 |
0 |
T104 |
7540 |
12 |
0 |
0 |
T106 |
4394 |
9 |
0 |
0 |
T107 |
7547 |
5 |
0 |
0 |
T130 |
12222 |
23 |
0 |
0 |
T131 |
71173 |
67 |
0 |
0 |
T132 |
12641 |
23 |
0 |
0 |
T133 |
13215 |
19 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
1089 |
0 |
0 |
T78 |
3311 |
1 |
0 |
0 |
T88 |
33958 |
23 |
0 |
0 |
T91 |
70577 |
91 |
0 |
0 |
T104 |
7540 |
3 |
0 |
0 |
T106 |
4394 |
4 |
0 |
0 |
T107 |
7547 |
6 |
0 |
0 |
T130 |
12222 |
32 |
0 |
0 |
T131 |
71173 |
87 |
0 |
0 |
T132 |
12641 |
7 |
0 |
0 |
T133 |
13215 |
21 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
1255 |
0 |
0 |
T78 |
3311 |
7 |
0 |
0 |
T88 |
33958 |
17 |
0 |
0 |
T91 |
70577 |
97 |
0 |
0 |
T104 |
7540 |
9 |
0 |
0 |
T106 |
4394 |
6 |
0 |
0 |
T107 |
7547 |
5 |
0 |
0 |
T130 |
12222 |
36 |
0 |
0 |
T131 |
71173 |
64 |
0 |
0 |
T132 |
12641 |
33 |
0 |
0 |
T133 |
13215 |
54 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
1156 |
0 |
0 |
T78 |
3311 |
7 |
0 |
0 |
T88 |
33958 |
23 |
0 |
0 |
T91 |
70577 |
74 |
0 |
0 |
T104 |
7540 |
5 |
0 |
0 |
T106 |
4394 |
4 |
0 |
0 |
T107 |
7547 |
15 |
0 |
0 |
T130 |
12222 |
27 |
0 |
0 |
T131 |
71173 |
67 |
0 |
0 |
T132 |
12641 |
14 |
0 |
0 |
T133 |
13215 |
3 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
1108 |
0 |
0 |
T78 |
3311 |
3 |
0 |
0 |
T88 |
33958 |
8 |
0 |
0 |
T91 |
70577 |
91 |
0 |
0 |
T104 |
7540 |
8 |
0 |
0 |
T106 |
4394 |
5 |
0 |
0 |
T107 |
7547 |
6 |
0 |
0 |
T130 |
12222 |
18 |
0 |
0 |
T131 |
71173 |
54 |
0 |
0 |
T132 |
12641 |
35 |
0 |
0 |
T133 |
13215 |
18 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
537899477 |
1184 |
0 |
0 |
T78 |
3311 |
5 |
0 |
0 |
T88 |
33958 |
20 |
0 |
0 |
T91 |
70577 |
67 |
0 |
0 |
T104 |
7540 |
9 |
0 |
0 |
T106 |
4394 |
1 |
0 |
0 |
T107 |
7547 |
12 |
0 |
0 |
T130 |
12222 |
24 |
0 |
0 |
T131 |
71173 |
66 |
0 |
0 |
T132 |
12641 |
10 |
0 |
0 |
T133 |
13215 |
43 |
0 |
0 |