Group : spi_device_env_pkg::tpm_read_hw_reg_cg_wrap::tpm_read_hw_reg_cg
Group Instance : tpm_access_0
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_access_0
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_access_0
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_access_1
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_access_1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_access_1
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_access_2
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_access_2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_access_2
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_access_3
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_access_3
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_access_3
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_access_4
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_access_4
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_access_4
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_did_vid
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_did_vid
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_did_vid
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_hash_start
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_hash_start
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_hash_start
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_int_enable
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_int_enable
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_int_enable
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_int_status
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_int_status
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_int_status
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_int_vector
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_int_vector
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_int_vector
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_intf_capability
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_intf_capability
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_intf_capability
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_rid
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_rid
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_rid
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Group Instance : tpm_sts
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 |
1 |
100 |
1 |
64 |
64 |
Summary for Group Instance tpm_sts
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
1 |
0 |
1 |
100.00 |
Variables for Group Instance tpm_sts
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_hit |
1 |
0 |
1 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_hit
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
done |
1610 |
1 |
|
|
T18 |
2 |
|
T38 |
6 |
|
T93 |
12 |
Summary for Variable cp_hit
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
done |
1566 |
1 |
|
|
T38 |
18 |
|
T93 |
6 |
|
T98 |
18 |
Summary for Variable cp_hit
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
done |
1504 |
1 |
|
|
T18 |
4 |
|
T38 |
6 |
|
T93 |
10 |
Summary for Variable cp_hit
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
done |
1542 |
1 |
|
|
T18 |
4 |
|
T38 |
10 |
|
T93 |
10 |
Summary for Variable cp_hit
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
done |
1540 |
1 |
|
|
T18 |
4 |
|
T38 |
12 |
|
T93 |
16 |
Summary for Variable cp_hit
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
done |
8388 |
1 |
|
|
T18 |
12 |
|
T38 |
92 |
|
T93 |
74 |
Summary for Variable cp_hit
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
done |
8216 |
1 |
|
|
T18 |
12 |
|
T38 |
120 |
|
T20 |
4 |
Summary for Variable cp_hit
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
done |
8016 |
1 |
|
|
T18 |
14 |
|
T38 |
104 |
|
T20 |
4 |
Summary for Variable cp_hit
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
done |
8070 |
1 |
|
|
T18 |
16 |
|
T38 |
90 |
|
T93 |
70 |
Summary for Variable cp_hit
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
done |
7964 |
1 |
|
|
T18 |
10 |
|
T38 |
94 |
|
T20 |
4 |
Summary for Variable cp_hit
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
done |
22 |
1 |
|
|
T94 |
2 |
|
T95 |
2 |
|
T96 |
2 |
Summary for Variable cp_hit
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
done |
7980 |
1 |
|
|
T18 |
16 |
|
T38 |
94 |
|
T93 |
72 |
Summary for Variable cp_hit
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_hit
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
done |
6775 |
1 |
|
|
T18 |
4 |
|
T38 |
67 |
|
T93 |
38 |
0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |