Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13944178	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

14352821

1

T1

22908

T2

1828

T3

897

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	18566107	1			T1	27914		T2	361		T3	9
values[0x0]	4864114	1			T1	9054		T2	786		T3	435
values[0x1]	4866778	1			T1	8949		T2	875		T3	460

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	10107049	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

18189950

1

T1

29592

T2

1878

T3

898

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	111157	1			T1	207		T4	10		T8	523
valid_sources[0x01]	106610	1			T1	169		T4	9		T5	14
valid_sources[0x02]	113535	1			T1	177		T4	9		T8	540
valid_sources[0x03]	111904	1			T1	171		T4	9		T5	2
valid_sources[0x04]	108161	1			T1	185		T4	7		T5	2
valid_sources[0x05]	113828	1			T1	209		T4	9		T5	1793
valid_sources[0x06]	106856	1			T1	194		T4	4		T5	1
valid_sources[0x07]	110536	1			T1	168		T4	10		T5	52
valid_sources[0x08]	114385	1			T1	204		T4	12		T5	36
valid_sources[0x09]	110146	1			T1	154		T4	5		T8	536
valid_sources[0x0a]	113496	1			T1	186		T5	151		T8	491
valid_sources[0x0b]	107953	1			T1	160		T4	5		T7	2
valid_sources[0x0c]	110114	1			T1	178		T4	11		T8	368
valid_sources[0x0d]	113628	1			T1	185		T4	8		T5	416
valid_sources[0x0e]	107683	1			T1	170		T4	13		T5	3
valid_sources[0x0f]	113753	1			T1	184		T4	8		T5	5831
valid_sources[0x10]	113375	1			T1	183		T4	8		T5	1
valid_sources[0x11]	110622	1			T1	190		T4	8		T5	1
valid_sources[0x12]	106829	1			T1	143		T4	8		T7	1
valid_sources[0x13]	111659	1			T1	209		T4	5		T5	154
valid_sources[0x14]	108626	1			T1	183		T4	4		T5	193
valid_sources[0x15]	110722	1			T1	200		T5	368		T8	551
valid_sources[0x16]	107483	1			T1	199		T4	6		T5	1
valid_sources[0x17]	108135	1			T1	195		T4	16		T7	2
valid_sources[0x18]	109009	1			T1	210		T4	5		T7	1
valid_sources[0x19]	107520	1			T1	153		T4	4		T5	13
valid_sources[0x1a]	111111	1			T1	156		T4	7		T5	3
valid_sources[0x1b]	108583	1			T1	206		T4	11		T5	1497
valid_sources[0x1c]	109410	1			T1	201		T4	5		T5	1
valid_sources[0x1d]	112243	1			T1	210		T4	9		T5	2
valid_sources[0x1e]	110390	1			T1	169		T4	4		T5	2
valid_sources[0x1f]	105055	1			T1	170		T4	13		T8	476
valid_sources[0x20]	111247	1			T1	201		T4	7		T5	142
valid_sources[0x21]	111195	1			T1	155		T4	5		T5	47
valid_sources[0x22]	115586	1			T1	162		T4	9		T5	4
valid_sources[0x23]	105699	1			T1	180		T4	11		T5	75
valid_sources[0x24]	112155	1			T1	202		T4	7		T5	2
valid_sources[0x25]	114757	1			T1	150		T4	12		T5	2
valid_sources[0x26]	107768	1			T1	129		T4	10		T7	1
valid_sources[0x27]	103703	1			T1	166		T4	3		T7	2
valid_sources[0x28]	114535	1			T1	168		T4	6		T5	1
valid_sources[0x29]	115785	1			T1	159		T4	9		T5	9492
valid_sources[0x2a]	107609	1			T1	176		T4	4		T5	167
valid_sources[0x2b]	109843	1			T1	168		T4	8		T7	3
valid_sources[0x2c]	108137	1			T1	170		T4	11		T5	2
valid_sources[0x2d]	112608	1			T1	189		T4	5		T8	678
valid_sources[0x2e]	105740	1			T1	184		T4	3		T5	71
valid_sources[0x2f]	105511	1			T1	158		T4	12		T8	444
valid_sources[0x30]	112839	1			T1	168		T4	13		T8	380
valid_sources[0x31]	105935	1			T1	149		T4	17		T7	1
valid_sources[0x32]	112839	1			T1	205		T4	7		T5	2
valid_sources[0x33]	109870	1			T1	207		T4	6		T5	194
valid_sources[0x34]	108611	1			T1	156		T4	3		T5	417
valid_sources[0x35]	105819	1			T1	153		T4	2		T8	487
valid_sources[0x36]	106405	1			T1	146		T4	13		T8	583
valid_sources[0x37]	109279	1			T1	161		T4	5		T5	941
valid_sources[0x38]	108309	1			T1	212		T4	8		T5	1
valid_sources[0x39]	109743	1			T1	184		T4	3		T8	595
valid_sources[0x3a]	123827	1			T1	204		T4	3		T5	2646
valid_sources[0x3b]	112704	1			T1	218		T4	11		T8	580
valid_sources[0x3c]	111985	1			T1	156		T4	2		T5	1
valid_sources[0x3d]	105467	1			T1	165		T4	13		T5	27
valid_sources[0x3e]	111845	1			T1	178		T4	6		T7	3
valid_sources[0x3f]	111674	1			T1	160		T4	15		T8	511
valid_sources[0x40]	116889	1			T1	245		T4	2		T5	29
valid_sources[0x41]	109900	1			T1	188		T4	11		T5	112
valid_sources[0x42]	112906	1			T1	204		T4	5		T5	45
valid_sources[0x43]	110379	1			T1	186		T4	15		T5	144
valid_sources[0x44]	110287	1			T1	213		T4	5		T5	85
valid_sources[0x45]	111919	1			T1	183		T4	10		T5	29
valid_sources[0x46]	117514	1			T1	188		T4	15		T5	2
valid_sources[0x47]	111226	1			T1	173		T4	5		T5	2
valid_sources[0x48]	108275	1			T1	204		T4	8		T5	2
valid_sources[0x49]	113022	1			T1	180		T4	3		T5	1
valid_sources[0x4a]	115583	1			T1	198		T4	7		T8	543
valid_sources[0x4b]	108152	1			T1	194		T4	8		T5	92
valid_sources[0x4c]	112253	1			T1	185		T4	8		T5	2
valid_sources[0x4d]	114072	1			T1	189		T4	6		T7	2
valid_sources[0x4e]	112084	1			T1	203		T4	5		T5	432
valid_sources[0x4f]	108718	1			T1	165		T4	7		T7	1
valid_sources[0x50]	111539	1			T1	176		T4	2		T5	340
valid_sources[0x51]	110309	1			T1	150		T3	451		T4	6
valid_sources[0x52]	111429	1			T1	208		T4	8		T5	1
valid_sources[0x53]	111041	1			T1	158		T4	6		T5	1
valid_sources[0x54]	107763	1			T1	162		T2	1		T4	17
valid_sources[0x55]	106456	1			T1	176		T4	10		T5	132
valid_sources[0x56]	108773	1			T1	152		T4	6		T5	9
valid_sources[0x57]	112551	1			T1	184		T4	8		T5	792
valid_sources[0x58]	110920	1			T1	169		T4	5		T8	478
valid_sources[0x59]	110237	1			T1	180		T4	5		T5	86
valid_sources[0x5a]	107887	1			T1	165		T4	4		T8	531
valid_sources[0x5b]	107384	1			T1	184		T4	19		T5	2
valid_sources[0x5c]	113311	1			T1	142		T2	1		T4	8
valid_sources[0x5d]	107032	1			T1	178		T4	7		T5	301
valid_sources[0x5e]	112102	1			T1	179		T4	7		T5	1
valid_sources[0x5f]	114483	1			T1	202		T4	11		T5	1
valid_sources[0x60]	107811	1			T1	186		T4	13		T5	67
valid_sources[0x61]	107563	1			T1	204		T4	4		T5	1
valid_sources[0x62]	105345	1			T1	197		T4	7		T7	1
valid_sources[0x63]	110975	1			T1	161		T4	4		T5	418
valid_sources[0x64]	107789	1			T1	188		T4	4		T5	3
valid_sources[0x65]	108369	1			T1	184		T4	5		T8	573
valid_sources[0x66]	110524	1			T1	123		T4	8		T5	36
valid_sources[0x67]	107766	1			T1	189		T4	7		T5	1
valid_sources[0x68]	110359	1			T1	176		T4	6		T5	1
valid_sources[0x69]	110995	1			T1	161		T4	3		T8	667
valid_sources[0x6a]	108439	1			T1	170		T2	474		T4	4
valid_sources[0x6b]	110049	1			T1	195		T4	7		T5	2
valid_sources[0x6c]	109495	1			T1	138		T4	4		T5	22
valid_sources[0x6d]	111080	1			T1	235		T4	11		T8	643
valid_sources[0x6e]	110350	1			T1	201		T4	14		T7	2
valid_sources[0x6f]	118897	1			T1	191		T4	9		T5	8467
valid_sources[0x70]	113161	1			T1	147		T4	11		T8	456
valid_sources[0x71]	103902	1			T1	196		T2	416		T4	4
valid_sources[0x72]	115322	1			T1	113		T4	13		T5	425
valid_sources[0x73]	107482	1			T1	180		T4	6		T5	1
valid_sources[0x74]	111263	1			T1	217		T2	285		T4	6
valid_sources[0x75]	110393	1			T1	170		T4	9		T5	1
valid_sources[0x76]	112120	1			T1	145		T2	154		T4	2
valid_sources[0x77]	110934	1			T1	157		T4	4		T8	513
valid_sources[0x78]	112289	1			T1	195		T4	7		T5	2
valid_sources[0x79]	115645	1			T1	196		T4	4		T5	2
valid_sources[0x7a]	106906	1			T1	195		T4	5		T5	1
valid_sources[0x7b]	107795	1			T1	183		T4	7		T5	50
valid_sources[0x7c]	107979	1			T1	189		T4	9		T5	3
valid_sources[0x7d]	110541	1			T1	171		T4	4		T5	1
valid_sources[0x7e]	109042	1			T1	192		T4	1		T5	2
valid_sources[0x7f]	107869	1			T1	145		T4	11		T5	56
valid_sources[0x80]	113426	1			T1	176		T4	8		T5	202

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5667269

1

T1

7083

T2

179

T3

5

values[0x0]

all_enables

biggest_size

4377140

1

T1

8033

T2

783

T3

434

values[0x1]

all_enables

biggest_size

4308412

1

T1

7792

T2

866

T3

458