Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13984748

1

T1

23009

T2

194

T3

7

full_word

14352998

1

T1

22908

T2

1828

T3

897

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	28336926	1			T1	45917		T2	2022		T3	904
auto[TlIntgErrCmd]	266	1			T104	10		T106	7		T107	10
auto[TlIntgErrData]	277	1			T104	11		T106	6		T107	10
auto[TlIntgErrBoth]	277	1			T104	9		T106	7		T107	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18571429

1

T1

27914

T2

361

T3

9

auto[1]

9766317

1

T1

18003

T2

1661

T3

895

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	12903449	1			T1	20831		T2	182		T3	4
auto[TlIntgErrNone]	partial	auto[1]	1080533	1			T1	2178		T2	12		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	5667615	1			T1	7083		T2	179		T3	5
auto[TlIntgErrNone]	full_word	auto[1]	8685329	1			T1	15825		T2	1649		T3	892
auto[TlIntgErrCmd]	partial	auto[0]	100	1			T104	4		T106	1		T107	4
auto[TlIntgErrCmd]	partial	auto[1]	152	1			T104	6		T106	6		T107	5
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T176	1		T177	1		T178	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T107	1		T179	1		T180	1
auto[TlIntgErrData]	partial	auto[0]	127	1			T104	4		T106	4		T107	4
auto[TlIntgErrData]	partial	auto[1]	127	1			T104	6		T106	2		T107	5
auto[TlIntgErrData]	full_word	auto[0]	14	1			T104	1		T107	1		T181	1
auto[TlIntgErrData]	full_word	auto[1]	9	1			T181	1		T174	1		T180	2
auto[TlIntgErrBoth]	partial	auto[0]	111	1			T104	5		T106	1		T107	3
auto[TlIntgErrBoth]	partial	auto[1]	149	1			T104	3		T106	5		T107	7
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T104	1		T181	1		T182	1
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T106	1		T183	1		T174	1