Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.fifo_h.reqfifo

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1280856937	33028353	0	0
DepthKnown_A	1280856937	1280592758	0	0
RvalidKnown_A	1280856937	1280592758	0	0
WreadyKnown_A	1280856937	1280592758	0	0
gen_passthru_fifo.paramCheckPass	2211	2211	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280856937	33028353	0	0
T1	138619	49723	0	0
T2	40515	3621	0	0
T3	426034	1735	0	0
T4	19411	1866	0	0
T5	728289	94867	0	0
T6	5231	8	0	0
T7	1392	201	0	0
T8	711547	156017	0	0
T9	317420	47385	0	0
T10	142177	1936	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280856937	1280592758	0	0
T1	138619	138613	0	0
T2	40515	40448	0	0
T3	426034	425949	0	0
T4	19411	19351	0	0
T5	728289	728279	0	0
T6	5231	5170	0	0
T7	1392	1303	0	0
T8	711547	711522	0	0
T9	317420	317415	0	0
T10	142177	142090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280856937	1280592758	0	0
T1	138619	138613	0	0
T2	40515	40448	0	0
T3	426034	425949	0	0
T4	19411	19351	0	0
T5	728289	728279	0	0
T6	5231	5170	0	0
T7	1392	1303	0	0
T8	711547	711522	0	0
T9	317420	317415	0	0
T10	142177	142090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280856937	1280592758	0	0
T1	138619	138613	0	0
T2	40515	40448	0	0
T3	426034	425949	0	0
T4	19411	19351	0	0
T5	728289	728279	0	0
T6	5231	5170	0	0
T7	1392	1303	0	0
T8	711547	711522	0	0
T9	317420	317415	0	0
T10	142177	142090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2211	2211	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1280856937	66473418	0	0
DepthKnown_A	1280856937	1280592758	0	0
RvalidKnown_A	1280856937	1280592758	0	0
WreadyKnown_A	1280856937	1280592758	0	0
gen_passthru_fifo.paramCheckPass	2211	2211	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280856937	66473418	0	0
T1	138619	45917	0	0
T2	40515	2022	0	0
T3	426034	904	0	0
T4	19411	5858	0	0
T5	728289	235116	0	0
T6	5231	22	0	0
T7	1392	201	0	0
T8	711547	563768	0	0
T9	317420	43155	0	0
T10	142177	1935	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280856937	1280592758	0	0
T1	138619	138613	0	0
T2	40515	40448	0	0
T3	426034	425949	0	0
T4	19411	19351	0	0
T5	728289	728279	0	0
T6	5231	5170	0	0
T7	1392	1303	0	0
T8	711547	711522	0	0
T9	317420	317415	0	0
T10	142177	142090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280856937	1280592758	0	0
T1	138619	138613	0	0
T2	40515	40448	0	0
T3	426034	425949	0	0
T4	19411	19351	0	0
T5	728289	728279	0	0
T6	5231	5170	0	0
T7	1392	1303	0	0
T8	711547	711522	0	0
T9	317420	317415	0	0
T10	142177	142090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280856937	1280592758	0	0
T1	138619	138613	0	0
T2	40515	40448	0	0
T3	426034	425949	0	0
T4	19411	19351	0	0
T5	728289	728279	0	0
T6	5231	5170	0	0
T7	1392	1303	0	0
T8	711547	711522	0	0
T9	317420	317415	0	0
T10	142177	142090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2211	2211	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1280856937	7066321	0	0
DepthKnown_A	1280856937	1280592758	0	0
RvalidKnown_A	1280856937	1280592758	0	0
WreadyKnown_A	1280856937	1280592758	0	0
gen_passthru_fifo.paramCheckPass	2211	2211	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280856937	7066321	0	0
T1	138619	10812	0	0
T2	40515	3196	0	0
T3	426034	1663	0	0
T4	19411	0	0	0
T5	728289	17484	0	0
T6	5231	0	0	0
T7	1392	100	0	0
T8	711547	24143	0	0
T9	317420	13307	0	0
T10	142177	1663	0	0
T11	0	832	0	0
T12	0	1663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280856937	1280592758	0	0
T1	138619	138613	0	0
T2	40515	40448	0	0
T3	426034	425949	0	0
T4	19411	19351	0	0
T5	728289	728279	0	0
T6	5231	5170	0	0
T7	1392	1303	0	0
T8	711547	711522	0	0
T9	317420	317415	0	0
T10	142177	142090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280856937	1280592758	0	0
T1	138619	138613	0	0
T2	40515	40448	0	0
T3	426034	425949	0	0
T4	19411	19351	0	0
T5	728289	728279	0	0
T6	5231	5170	0	0
T7	1392	1303	0	0
T8	711547	711522	0	0
T9	317420	317415	0	0
T10	142177	142090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280856937	1280592758	0	0
T1	138619	138613	0	0
T2	40515	40448	0	0
T3	426034	425949	0	0
T4	19411	19351	0	0
T5	728289	728279	0	0
T6	5231	5170	0	0
T7	1392	1303	0	0
T8	711547	711522	0	0
T9	317420	317415	0	0
T10	142177	142090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2211	2211	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1280856937	8074180	0	0
DepthKnown_A	1280856937	1280592758	0	0
RvalidKnown_A	1280856937	1280592758	0	0
WreadyKnown_A	1280856937	1280592758	0	0
gen_passthru_fifo.paramCheckPass	2211	2211	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280856937	8074180	0	0
T1	138619	7488	0	0
T2	40515	1600	0	0
T3	426034	832	0	0
T4	19411	0	0	0
T5	728289	17395	0	0
T6	5231	0	0	0
T7	1392	100	0	0
T8	711547	49903	0	0
T9	317420	9152	0	0
T10	142177	832	0	0
T11	0	832	0	0
T12	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280856937	1280592758	0	0
T1	138619	138613	0	0
T2	40515	40448	0	0
T3	426034	425949	0	0
T4	19411	19351	0	0
T5	728289	728279	0	0
T6	5231	5170	0	0
T7	1392	1303	0	0
T8	711547	711522	0	0
T9	317420	317415	0	0
T10	142177	142090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280856937	1280592758	0	0
T1	138619	138613	0	0
T2	40515	40448	0	0
T3	426034	425949	0	0
T4	19411	19351	0	0
T5	728289	728279	0	0
T6	5231	5170	0	0
T7	1392	1303	0	0
T8	711547	711522	0	0
T9	317420	317415	0	0
T10	142177	142090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280856937	1280592758	0	0
T1	138619	138613	0	0
T2	40515	40448	0	0
T3	426034	425949	0	0
T4	19411	19351	0	0
T5	728289	728279	0	0
T6	5231	5170	0	0
T7	1392	1303	0	0
T8	711547	711522	0	0
T9	317420	317415	0	0
T10	142177	142090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2211	2211	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1280856937	470497	0	0
DepthKnown_A	1280856937	1280592758	0	0
RvalidKnown_A	1280856937	1280592758	0	0
WreadyKnown_A	1280856937	1280592758	0	0
gen_passthru_fifo.paramCheckPass	2211	2211	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280856937	470497	0	0
T1	138619	1254	0	0
T2	40515	0	0	0
T3	426034	0	0	0
T4	19411	61	0	0
T5	728289	130	0	0
T6	5231	0	0	0
T7	1392	100	0	0
T8	711547	1637	0	0
T9	317420	580	0	0
T10	142177	0	0	0
T15	0	829	0	0
T17	0	1388	0	0
T18	0	947	0	0
T25	0	257	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280856937	1280592758	0	0
T1	138619	138613	0	0
T2	40515	40448	0	0
T3	426034	425949	0	0
T4	19411	19351	0	0
T5	728289	728279	0	0
T6	5231	5170	0	0
T7	1392	1303	0	0
T8	711547	711522	0	0
T9	317420	317415	0	0
T10	142177	142090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280856937	1280592758	0	0
T1	138619	138613	0	0
T2	40515	40448	0	0
T3	426034	425949	0	0
T4	19411	19351	0	0
T5	728289	728279	0	0
T6	5231	5170	0	0
T7	1392	1303	0	0
T8	711547	711522	0	0
T9	317420	317415	0	0
T10	142177	142090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280856937	1280592758	0	0
T1	138619	138613	0	0
T2	40515	40448	0	0
T3	426034	425949	0	0
T4	19411	19351	0	0
T5	728289	728279	0	0
T6	5231	5170	0	0
T7	1392	1303	0	0
T8	711547	711522	0	0
T9	317420	317415	0	0
T10	142177	142090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2211	2211	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1280856937	1124175	0	0
DepthKnown_A	1280856937	1280592758	0	0
RvalidKnown_A	1280856937	1280592758	0	0
WreadyKnown_A	1280856937	1280592758	0	0
gen_passthru_fifo.paramCheckPass	2211	2211	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280856937	1124175	0	0
T1	138619	1253	0	0
T2	40515	0	0	0
T3	426034	0	0	0
T4	19411	160	0	0
T5	728289	615	0	0
T6	5231	0	0	0
T7	1392	100	0	0
T8	711547	7574	0	0
T9	317420	580	0	0
T10	142177	0	0	0
T15	0	829	0	0
T17	0	4322	0	0
T18	0	947	0	0
T25	0	822	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280856937	1280592758	0	0
T1	138619	138613	0	0
T2	40515	40448	0	0
T3	426034	425949	0	0
T4	19411	19351	0	0
T5	728289	728279	0	0
T6	5231	5170	0	0
T7	1392	1303	0	0
T8	711547	711522	0	0
T9	317420	317415	0	0
T10	142177	142090	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280856937	1280592758	0	0
T1	138619	138613	0	0
T2	40515	40448	0	0
T3	426034	425949	0	0
T4	19411	19351	0	0
T5	728289	728279	0	0
T6	5231	5170	0	0
T7	1392	1303	0	0
T8	711547	711522	0	0
T9	317420	317415	0	0
T10	142177	142090	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1280856937	1280592758	0	0
T1	138619	138613	0	0
T2	40515	40448	0	0
T3	426034	425949	0	0
T4	19411	19351	0	0
T5	728289	728279	0	0
T6	5231	5170	0	0
T7	1392	1303	0	0
T8	711547	711522	0	0
T9	317420	317415	0	0
T10	142177	142090	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2211	2211	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0