Unified Coverage Report :: Module :: prim_onehot_check

Module : prim_onehot_check

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_onehot_check_0/rtl/prim_onehot_check.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_reg_we_check

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : prim_onehot_check

	Total	Covered	Percent
Totals	5	5	100.00
Total Bits	138	138	100.00
Total Bits 0->1	69	69	100.00
Total Bits 1->0	69	69	100.00

Ports	5	5	100.00
Port Bits	138	138	100.00
Port Bits 0->1	69	69	100.00
Port Bits 1->0	69	69	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T8,T16,T17	Yes	T1,T2,T3	INPUT
oh_i[5:0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	INPUT
oh_i[6]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[8:7]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	INPUT
oh_i[9]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[14:10]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	INPUT
oh_i[18:15]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[58:19]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	INPUT
oh_i[59]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[70:60]	Yes	Yes	T1,*T4,*T6	Yes	T1,T4,T6	INPUT
oh_i[71]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[72]	Yes	Yes	T1,T4,T8	Yes	T1,T4,T8	INPUT
addr_i[6:0]	Unreachable	Unreachable		Unreachable		INPUT
en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
err_o	Yes	Yes	T66,T67,T68	Yes	T66,T67,T68	OUTPUT

*Tests covering at least one bit in the range