Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T8
1	0	Covered	T1,T4,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Unreachable
1	1	Covered	T1,T4,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T8
1	0	Covered	T1,T5,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T5,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2051036817	1659681685	0	0
CheckNGreaterZero_A	5583	5583	0	0
GntImpliesReady_A	2051036817	9066752	0	0
GntImpliesValid_A	2051036817	9066752	0	0
GrantKnown_A	2051036817	1659681685	0	0
IdxKnown_A	2051036817	1659681685	0	0
IndexIsCorrect_A	2051036817	9066752	0	0
LockArbDecision_A	2051036817	0	0	0
NoReadyValidNoGrant_A	2051036817	0	0	0
ReadyAndValidImplyGrant_A	2051036817	9066752	0	0
ReqAndReadyImplyGrant_A	2051036817	9066752	0	0
ReqImpliesValid_A	2051036817	9066752	0	0
ReqStaysHighUntilGranted0_M	2051036817	0	0	0
RoundRobin_A	2051036817	6	0	1861
ValidKnown_A	2051036817	1659681685	0	0
gen_data_port_assertion.DataFlow_A	2051036817	9066752	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2051036817	1659681685	0	0
T1	1058639	589067	0	0
T2	252101	146150	0	0
T3	638120	531459	0	0
T4	24307	21799	0	0
T5	935169	831392	0	0
T6	6073	5314	0	0
T7	1392	1303	0	0
T8	2471511	1577018	0	0
T9	1098168	705037	0	0
T10	411365	276344	0	0
T11	62754	30784	0	0
T12	0	15078	0	0
T13	0	76260	0	0
T15	0	312024	0	0
T17	0	320912	0	0
T18	0	326792	0	0
T20	0	11240	0	0
T38	0	142119	0	0
T39	0	1376	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5583	5583	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2051036817	9066752	0	0
T1	1058639	18649	0	0
T2	252101	1600	0	0
T3	638120	832	0	0
T4	24307	313	0	0
T5	935169	14330	0	0
T6	6073	0	0	0
T7	1392	200	0	0
T8	2471511	30737	0	0
T9	1098168	12894	0	0
T10	411365	832	0	0
T11	62754	832	0	0
T15	0	5110	0	0
T17	0	8121	0	0
T18	0	4927	0	0
T20	0	5445	0	0
T25	0	3647	0	0
T26	0	1028	0	0
T39	0	86	0	0
T40	0	3610	0	0
T41	0	4	0	0
T42	0	232	0	0
T43	0	3008	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2051036817	9066752	0	0
T1	1058639	18649	0	0
T2	252101	1600	0	0
T3	638120	832	0	0
T4	24307	313	0	0
T5	935169	14330	0	0
T6	6073	0	0	0
T7	1392	200	0	0
T8	2471511	30737	0	0
T9	1098168	12894	0	0
T10	411365	832	0	0
T11	62754	832	0	0
T15	0	5110	0	0
T17	0	8121	0	0
T18	0	4927	0	0
T20	0	5445	0	0
T25	0	3647	0	0
T26	0	1028	0	0
T39	0	86	0	0
T40	0	3610	0	0
T41	0	4	0	0
T42	0	232	0	0
T43	0	3008	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2051036817	1659681685	0	0
T1	1058639	589067	0	0
T2	252101	146150	0	0
T3	638120	531459	0	0
T4	24307	21799	0	0
T5	935169	831392	0	0
T6	6073	5314	0	0
T7	1392	1303	0	0
T8	2471511	1577018	0	0
T9	1098168	705037	0	0
T10	411365	276344	0	0
T11	62754	30784	0	0
T12	0	15078	0	0
T13	0	76260	0	0
T15	0	312024	0	0
T17	0	320912	0	0
T18	0	326792	0	0
T20	0	11240	0	0
T38	0	142119	0	0
T39	0	1376	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2051036817	1659681685	0	0
T1	1058639	589067	0	0
T2	252101	146150	0	0
T3	638120	531459	0	0
T4	24307	21799	0	0
T5	935169	831392	0	0
T6	6073	5314	0	0
T7	1392	1303	0	0
T8	2471511	1577018	0	0
T9	1098168	705037	0	0
T10	411365	276344	0	0
T11	62754	30784	0	0
T12	0	15078	0	0
T13	0	76260	0	0
T15	0	312024	0	0
T17	0	320912	0	0
T18	0	326792	0	0
T20	0	11240	0	0
T38	0	142119	0	0
T39	0	1376	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2051036817	9066752	0	0
T1	1058639	18649	0	0
T2	252101	1600	0	0
T3	638120	832	0	0
T4	24307	313	0	0
T5	935169	14330	0	0
T6	6073	0	0	0
T7	1392	200	0	0
T8	2471511	30737	0	0
T9	1098168	12894	0	0
T10	411365	832	0	0
T11	62754	832	0	0
T15	0	5110	0	0
T17	0	8121	0	0
T18	0	4927	0	0
T20	0	5445	0	0
T25	0	3647	0	0
T26	0	1028	0	0
T39	0	86	0	0
T40	0	3610	0	0
T41	0	4	0	0
T42	0	232	0	0
T43	0	3008	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2051036817	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2051036817	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2051036817	9066752	0	0
T1	1058639	18649	0	0
T2	252101	1600	0	0
T3	638120	832	0	0
T4	24307	313	0	0
T5	935169	14330	0	0
T6	6073	0	0	0
T7	1392	200	0	0
T8	2471511	30737	0	0
T9	1098168	12894	0	0
T10	411365	832	0	0
T11	62754	832	0	0
T15	0	5110	0	0
T17	0	8121	0	0
T18	0	4927	0	0
T20	0	5445	0	0
T25	0	3647	0	0
T26	0	1028	0	0
T39	0	86	0	0
T40	0	3610	0	0
T41	0	4	0	0
T42	0	232	0	0
T43	0	3008	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2051036817	9066752	0	0
T1	1058639	18649	0	0
T2	252101	1600	0	0
T3	638120	832	0	0
T4	24307	313	0	0
T5	935169	14330	0	0
T6	6073	0	0	0
T7	1392	200	0	0
T8	2471511	30737	0	0
T9	1098168	12894	0	0
T10	411365	832	0	0
T11	62754	832	0	0
T15	0	5110	0	0
T17	0	8121	0	0
T18	0	4927	0	0
T20	0	5445	0	0
T25	0	3647	0	0
T26	0	1028	0	0
T39	0	86	0	0
T40	0	3610	0	0
T41	0	4	0	0
T42	0	232	0	0
T43	0	3008	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2051036817	9066752	0	0
T1	1058639	18649	0	0
T2	252101	1600	0	0
T3	638120	832	0	0
T4	24307	313	0	0
T5	935169	14330	0	0
T6	6073	0	0	0
T7	1392	200	0	0
T8	2471511	30737	0	0
T9	1098168	12894	0	0
T10	411365	832	0	0
T11	62754	832	0	0
T15	0	5110	0	0
T17	0	8121	0	0
T18	0	4927	0	0
T20	0	5445	0	0
T25	0	3647	0	0
T26	0	1028	0	0
T39	0	86	0	0
T40	0	3610	0	0
T41	0	4	0	0
T42	0	232	0	0
T43	0	3008	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2051036817	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2051036817	6	0	1861
T44	472308	1	0	1
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	103197	0	0	1
T51	755	0	0	1
T52	21353	0	0	1
T53	20813	0	0	1
T54	13680	0	0	1
T55	860893	0	0	1
T56	972957	0	0	1
T57	195611	0	0	1
T58	2667	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2051036817	1659681685	0	0
T1	1058639	589067	0	0
T2	252101	146150	0	0
T3	638120	531459	0	0
T4	24307	21799	0	0
T5	935169	831392	0	0
T6	6073	5314	0	0
T7	1392	1303	0	0
T8	2471511	1577018	0	0
T9	1098168	705037	0	0
T10	411365	276344	0	0
T11	62754	30784	0	0
T12	0	15078	0	0
T13	0	76260	0	0
T15	0	312024	0	0
T17	0	320912	0	0
T18	0	326792	0	0
T20	0	11240	0	0
T38	0	142119	0	0
T39	0	1376	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2051036817	9066752	0	0
T1	1058639	18649	0	0
T2	252101	1600	0	0
T3	638120	832	0	0
T4	24307	313	0	0
T5	935169	14330	0	0
T6	6073	0	0	0
T7	1392	200	0	0
T8	2471511	30737	0	0
T9	1098168	12894	0	0
T10	411365	832	0	0
T11	62754	832	0	0
T15	0	5110	0	0
T17	0	8121	0	0
T18	0	4927	0	0
T20	0	5445	0	0
T25	0	3647	0	0
T26	0	1028	0	0
T39	0	86	0	0
T40	0	3610	0	0
T41	0	4	0	0
T42	0	232	0	0
T43	0	3008	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T8
1	0	Covered	T1,T4,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Unreachable
1	1	Covered	T1,T4,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T8
0	0	1	Unreachable
0	0	0	Covered	T1,T4,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	387241826	85895520	0	0
CheckNGreaterZero_A	1861	1861	0	0
GntImpliesReady_A	387241826	1975151	0	0
GntImpliesValid_A	387241826	1975151	0	0
GrantKnown_A	387241826	85895520	0	0
IdxKnown_A	387241826	85895520	0	0
IndexIsCorrect_A	387241826	1975151	0	0
LockArbDecision_A	387241826	0	0	0
NoReadyValidNoGrant_A	387241826	0	0	0
ReadyAndValidImplyGrant_A	387241826	1975151	0	0
ReqAndReadyImplyGrant_A	387241826	1975151	0	0
ReqImpliesValid_A	387241826	1975151	0	0
ReqStaysHighUntilGranted0_M	387241826	0	0	0
RoundRobin_A	387241826	0	0	0
ValidKnown_A	387241826	85895520	0	0
gen_data_port_assertion.DataFlow_A	387241826	1975151	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387241826	85895520	0	0
T1	460010	167768	0	0
T2	105793	0	0	0
T3	106043	0	0	0
T4	2448	2448	0	0
T5	103440	0	0	0
T6	421	144	0	0
T8	879982	175864	0	0
T9	390374	0	0	0
T10	134594	0	0	0
T11	31377	0	0	0
T15	0	312024	0	0
T17	0	320912	0	0
T18	0	326792	0	0
T20	0	11240	0	0
T38	0	142119	0	0
T39	0	1376	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1861	1861	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387241826	1975151	0	0
T1	460010	6527	0	0
T2	105793	0	0	0
T3	106043	0	0	0
T4	2448	248	0	0
T5	103440	0	0	0
T6	421	0	0	0
T8	879982	8215	0	0
T9	390374	0	0	0
T10	134594	0	0	0
T11	31377	0	0	0
T15	0	5110	0	0
T17	0	8121	0	0
T18	0	4927	0	0
T20	0	698	0	0
T39	0	86	0	0
T40	0	3610	0	0
T42	0	232	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387241826	1975151	0	0
T1	460010	6527	0	0
T2	105793	0	0	0
T3	106043	0	0	0
T4	2448	248	0	0
T5	103440	0	0	0
T6	421	0	0	0
T8	879982	8215	0	0
T9	390374	0	0	0
T10	134594	0	0	0
T11	31377	0	0	0
T15	0	5110	0	0
T17	0	8121	0	0
T18	0	4927	0	0
T20	0	698	0	0
T39	0	86	0	0
T40	0	3610	0	0
T42	0	232	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387241826	85895520	0	0
T1	460010	167768	0	0
T2	105793	0	0	0
T3	106043	0	0	0
T4	2448	2448	0	0
T5	103440	0	0	0
T6	421	144	0	0
T8	879982	175864	0	0
T9	390374	0	0	0
T10	134594	0	0	0
T11	31377	0	0	0
T15	0	312024	0	0
T17	0	320912	0	0
T18	0	326792	0	0
T20	0	11240	0	0
T38	0	142119	0	0
T39	0	1376	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387241826	85895520	0	0
T1	460010	167768	0	0
T2	105793	0	0	0
T3	106043	0	0	0
T4	2448	2448	0	0
T5	103440	0	0	0
T6	421	144	0	0
T8	879982	175864	0	0
T9	390374	0	0	0
T10	134594	0	0	0
T11	31377	0	0	0
T15	0	312024	0	0
T17	0	320912	0	0
T18	0	326792	0	0
T20	0	11240	0	0
T38	0	142119	0	0
T39	0	1376	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387241826	1975151	0	0
T1	460010	6527	0	0
T2	105793	0	0	0
T3	106043	0	0	0
T4	2448	248	0	0
T5	103440	0	0	0
T6	421	0	0	0
T8	879982	8215	0	0
T9	390374	0	0	0
T10	134594	0	0	0
T11	31377	0	0	0
T15	0	5110	0	0
T17	0	8121	0	0
T18	0	4927	0	0
T20	0	698	0	0
T39	0	86	0	0
T40	0	3610	0	0
T42	0	232	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387241826	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387241826	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387241826	1975151	0	0
T1	460010	6527	0	0
T2	105793	0	0	0
T3	106043	0	0	0
T4	2448	248	0	0
T5	103440	0	0	0
T6	421	0	0	0
T8	879982	8215	0	0
T9	390374	0	0	0
T10	134594	0	0	0
T11	31377	0	0	0
T15	0	5110	0	0
T17	0	8121	0	0
T18	0	4927	0	0
T20	0	698	0	0
T39	0	86	0	0
T40	0	3610	0	0
T42	0	232	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387241826	1975151	0	0
T1	460010	6527	0	0
T2	105793	0	0	0
T3	106043	0	0	0
T4	2448	248	0	0
T5	103440	0	0	0
T6	421	0	0	0
T8	879982	8215	0	0
T9	390374	0	0	0
T10	134594	0	0	0
T11	31377	0	0	0
T15	0	5110	0	0
T17	0	8121	0	0
T18	0	4927	0	0
T20	0	698	0	0
T39	0	86	0	0
T40	0	3610	0	0
T42	0	232	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387241826	1975151	0	0
T1	460010	6527	0	0
T2	105793	0	0	0
T3	106043	0	0	0
T4	2448	248	0	0
T5	103440	0	0	0
T6	421	0	0	0
T8	879982	8215	0	0
T9	390374	0	0	0
T10	134594	0	0	0
T11	31377	0	0	0
T15	0	5110	0	0
T17	0	8121	0	0
T18	0	4927	0	0
T20	0	698	0	0
T39	0	86	0	0
T40	0	3610	0	0
T42	0	232	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	387241826	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387241826	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387241826	85895520	0	0
T1	460010	167768	0	0
T2	105793	0	0	0
T3	106043	0	0	0
T4	2448	2448	0	0
T5	103440	0	0	0
T6	421	144	0	0
T8	879982	175864	0	0
T9	390374	0	0	0
T10	134594	0	0	0
T11	31377	0	0	0
T15	0	312024	0	0
T17	0	320912	0	0
T18	0	326792	0	0
T20	0	11240	0	0
T38	0	142119	0	0
T39	0	1376	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387241826	1975151	0	0
T1	460010	6527	0	0
T2	105793	0	0	0
T3	106043	0	0	0
T4	2448	248	0	0
T5	103440	0	0	0
T6	421	0	0	0
T8	879982	8215	0	0
T9	390374	0	0	0
T10	134594	0	0	0
T11	31377	0	0	0
T15	0	5110	0	0
T17	0	8121	0	0
T18	0	4927	0	0
T20	0	698	0	0
T39	0	86	0	0
T40	0	3610	0	0
T42	0	232	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T8
1	0	Covered	T1,T5,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T5,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T5,T8
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	387241826	297405158	0	0
CheckNGreaterZero_A	1861	1861	0	0
GntImpliesReady_A	387241826	1387882	0	0
GntImpliesValid_A	387241826	1387882	0	0
GrantKnown_A	387241826	297405158	0	0
IdxKnown_A	387241826	297405158	0	0
IndexIsCorrect_A	387241826	1387882	0	0
LockArbDecision_A	387241826	0	0	0
NoReadyValidNoGrant_A	387241826	0	0	0
ReadyAndValidImplyGrant_A	387241826	1387882	0	0
ReqAndReadyImplyGrant_A	387241826	1387882	0	0
ReqImpliesValid_A	387241826	1387882	0	0
ReqStaysHighUntilGranted0_M	387241826	0	0	0
RoundRobin_A	387241826	0	0	0
ValidKnown_A	387241826	297405158	0	0
gen_data_port_assertion.DataFlow_A	387241826	1387882	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387241826	297405158	0	0
T1	460010	282686	0	0
T2	105793	105702	0	0
T3	106043	105510	0	0
T4	2448	0	0	0
T5	103440	103113	0	0
T6	421	0	0	0
T8	879982	689632	0	0
T9	390374	387622	0	0
T10	134594	134254	0	0
T11	31377	30784	0	0
T12	0	15078	0	0
T13	0	76260	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1861	1861	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387241826	1387882	0	0
T1	460010	1287	0	0
T2	105793	0	0	0
T3	106043	0	0	0
T4	2448	0	0	0
T5	103440	2540	0	0
T6	421	0	0	0
T8	879982	1610	0	0
T9	390374	3127	0	0
T10	134594	0	0	0
T11	31377	0	0	0
T20	0	4747	0	0
T25	0	3647	0	0
T26	0	1028	0	0
T41	0	4	0	0
T43	0	3008	0	0
T59	0	646	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387241826	1387882	0	0
T1	460010	1287	0	0
T2	105793	0	0	0
T3	106043	0	0	0
T4	2448	0	0	0
T5	103440	2540	0	0
T6	421	0	0	0
T8	879982	1610	0	0
T9	390374	3127	0	0
T10	134594	0	0	0
T11	31377	0	0	0
T20	0	4747	0	0
T25	0	3647	0	0
T26	0	1028	0	0
T41	0	4	0	0
T43	0	3008	0	0
T59	0	646	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387241826	297405158	0	0
T1	460010	282686	0	0
T2	105793	105702	0	0
T3	106043	105510	0	0
T4	2448	0	0	0
T5	103440	103113	0	0
T6	421	0	0	0
T8	879982	689632	0	0
T9	390374	387622	0	0
T10	134594	134254	0	0
T11	31377	30784	0	0
T12	0	15078	0	0
T13	0	76260	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387241826	297405158	0	0
T1	460010	282686	0	0
T2	105793	105702	0	0
T3	106043	105510	0	0
T4	2448	0	0	0
T5	103440	103113	0	0
T6	421	0	0	0
T8	879982	689632	0	0
T9	390374	387622	0	0
T10	134594	134254	0	0
T11	31377	30784	0	0
T12	0	15078	0	0
T13	0	76260	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387241826	1387882	0	0
T1	460010	1287	0	0
T2	105793	0	0	0
T3	106043	0	0	0
T4	2448	0	0	0
T5	103440	2540	0	0
T6	421	0	0	0
T8	879982	1610	0	0
T9	390374	3127	0	0
T10	134594	0	0	0
T11	31377	0	0	0
T20	0	4747	0	0
T25	0	3647	0	0
T26	0	1028	0	0
T41	0	4	0	0
T43	0	3008	0	0
T59	0	646	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387241826	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387241826	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387241826	1387882	0	0
T1	460010	1287	0	0
T2	105793	0	0	0
T3	106043	0	0	0
T4	2448	0	0	0
T5	103440	2540	0	0
T6	421	0	0	0
T8	879982	1610	0	0
T9	390374	3127	0	0
T10	134594	0	0	0
T11	31377	0	0	0
T20	0	4747	0	0
T25	0	3647	0	0
T26	0	1028	0	0
T41	0	4	0	0
T43	0	3008	0	0
T59	0	646	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387241826	1387882	0	0
T1	460010	1287	0	0
T2	105793	0	0	0
T3	106043	0	0	0
T4	2448	0	0	0
T5	103440	2540	0	0
T6	421	0	0	0
T8	879982	1610	0	0
T9	390374	3127	0	0
T10	134594	0	0	0
T11	31377	0	0	0
T20	0	4747	0	0
T25	0	3647	0	0
T26	0	1028	0	0
T41	0	4	0	0
T43	0	3008	0	0
T59	0	646	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387241826	1387882	0	0
T1	460010	1287	0	0
T2	105793	0	0	0
T3	106043	0	0	0
T4	2448	0	0	0
T5	103440	2540	0	0
T6	421	0	0	0
T8	879982	1610	0	0
T9	390374	3127	0	0
T10	134594	0	0	0
T11	31377	0	0	0
T20	0	4747	0	0
T25	0	3647	0	0
T26	0	1028	0	0
T41	0	4	0	0
T43	0	3008	0	0
T59	0	646	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	387241826	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387241826	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387241826	297405158	0	0
T1	460010	282686	0	0
T2	105793	105702	0	0
T3	106043	105510	0	0
T4	2448	0	0	0
T5	103440	103113	0	0
T6	421	0	0	0
T8	879982	689632	0	0
T9	390374	387622	0	0
T10	134594	134254	0	0
T11	31377	30784	0	0
T12	0	15078	0	0
T13	0	76260	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387241826	1387882	0	0
T1	460010	1287	0	0
T2	105793	0	0	0
T3	106043	0	0	0
T4	2448	0	0	0
T5	103440	2540	0	0
T6	421	0	0	0
T8	879982	1610	0	0
T9	390374	3127	0	0
T10	134594	0	0	0
T11	31377	0	0	0
T20	0	4747	0	0
T25	0	3647	0	0
T26	0	1028	0	0
T41	0	4	0	0
T43	0	3008	0	0
T59	0	646	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1276553165	1276381007	0	0
CheckNGreaterZero_A	1861	1861	0	0
GntImpliesReady_A	1276553165	5703719	0	0
GntImpliesValid_A	1276553165	5703719	0	0
GrantKnown_A	1276553165	1276381007	0	0
IdxKnown_A	1276553165	1276381007	0	0
IndexIsCorrect_A	1276553165	5703719	0	0
LockArbDecision_A	1276553165	0	0	0
NoReadyValidNoGrant_A	1276553165	0	0	0
ReadyAndValidImplyGrant_A	1276553165	5703719	0	0
ReqAndReadyImplyGrant_A	1276553165	5703719	0	0
ReqImpliesValid_A	1276553165	5703719	0	0
ReqStaysHighUntilGranted0_M	1276553165	0	0	0
RoundRobin_A	1276553165	6	0	1861
ValidKnown_A	1276553165	1276381007	0	0
gen_data_port_assertion.DataFlow_A	1276553165	5703719	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1276553165	1276381007	0	0
T1	138619	138613	0	0
T2	40515	40448	0	0
T3	426034	425949	0	0
T4	19411	19351	0	0
T5	728289	728279	0	0
T6	5231	5170	0	0
T7	1392	1303	0	0
T8	711547	711522	0	0
T9	317420	317415	0	0
T10	142177	142090	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1861	1861	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1276553165	5703719	0	0
T1	138619	10835	0	0
T2	40515	1600	0	0
T3	426034	832	0	0
T4	19411	65	0	0
T5	728289	11790	0	0
T6	5231	0	0	0
T7	1392	200	0	0
T8	711547	20912	0	0
T9	317420	9767	0	0
T10	142177	832	0	0
T11	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1276553165	5703719	0	0
T1	138619	10835	0	0
T2	40515	1600	0	0
T3	426034	832	0	0
T4	19411	65	0	0
T5	728289	11790	0	0
T6	5231	0	0	0
T7	1392	200	0	0
T8	711547	20912	0	0
T9	317420	9767	0	0
T10	142177	832	0	0
T11	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1276553165	1276381007	0	0
T1	138619	138613	0	0
T2	40515	40448	0	0
T3	426034	425949	0	0
T4	19411	19351	0	0
T5	728289	728279	0	0
T6	5231	5170	0	0
T7	1392	1303	0	0
T8	711547	711522	0	0
T9	317420	317415	0	0
T10	142177	142090	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1276553165	1276381007	0	0
T1	138619	138613	0	0
T2	40515	40448	0	0
T3	426034	425949	0	0
T4	19411	19351	0	0
T5	728289	728279	0	0
T6	5231	5170	0	0
T7	1392	1303	0	0
T8	711547	711522	0	0
T9	317420	317415	0	0
T10	142177	142090	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1276553165	5703719	0	0
T1	138619	10835	0	0
T2	40515	1600	0	0
T3	426034	832	0	0
T4	19411	65	0	0
T5	728289	11790	0	0
T6	5231	0	0	0
T7	1392	200	0	0
T8	711547	20912	0	0
T9	317420	9767	0	0
T10	142177	832	0	0
T11	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1276553165	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1276553165	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1276553165	5703719	0	0
T1	138619	10835	0	0
T2	40515	1600	0	0
T3	426034	832	0	0
T4	19411	65	0	0
T5	728289	11790	0	0
T6	5231	0	0	0
T7	1392	200	0	0
T8	711547	20912	0	0
T9	317420	9767	0	0
T10	142177	832	0	0
T11	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1276553165	5703719	0	0
T1	138619	10835	0	0
T2	40515	1600	0	0
T3	426034	832	0	0
T4	19411	65	0	0
T5	728289	11790	0	0
T6	5231	0	0	0
T7	1392	200	0	0
T8	711547	20912	0	0
T9	317420	9767	0	0
T10	142177	832	0	0
T11	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1276553165	5703719	0	0
T1	138619	10835	0	0
T2	40515	1600	0	0
T3	426034	832	0	0
T4	19411	65	0	0
T5	728289	11790	0	0
T6	5231	0	0	0
T7	1392	200	0	0
T8	711547	20912	0	0
T9	317420	9767	0	0
T10	142177	832	0	0
T11	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1276553165	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1276553165	6	0	1861
T44	472308	1	0	1
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	103197	0	0	1
T51	755	0	0	1
T52	21353	0	0	1
T53	20813	0	0	1
T54	13680	0	0	1
T55	860893	0	0	1
T56	972957	0	0	1
T57	195611	0	0	1
T58	2667	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1276553165	1276381007	0	0
T1	138619	138613	0	0
T2	40515	40448	0	0
T3	426034	425949	0	0
T4	19411	19351	0	0
T5	728289	728279	0	0
T6	5231	5170	0	0
T7	1392	1303	0	0
T8	711547	711522	0	0
T9	317420	317415	0	0
T10	142177	142090	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1276553165	5703719	0	0
T1	138619	10835	0	0
T2	40515	1600	0	0
T3	426034	832	0	0
T4	19411	65	0	0
T5	728289	11790	0	0
T6	5231	0	0	0
T7	1392	200	0	0
T8	711547	20912	0	0
T9	317420	9767	0	0
T10	142177	832	0	0
T11	0	832	0	0