Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	14955422	1			T1	3901		T2	1		T3	104309
all_values[1]	14955422	1			T1	3901		T2	1		T3	104309
all_values[2]	14955422	1			T1	3901		T2	1		T3	104309
all_values[3]	14955422	1			T1	3901		T2	1		T3	104309
all_values[4]	14955422	1			T1	3901		T2	1		T3	104309
all_values[5]	14955422	1			T1	3901		T2	1		T3	104309
all_values[6]	14955422	1			T1	3901		T2	1		T3	104309
all_values[7]	14955422	1			T1	3901		T2	1		T3	104309

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

117349766

1

T1

31208

T2

8

T3

515161

auto[1]

2293610

1

T3

319311

T58

40

T33

39

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

119485365

1

T1

31208

T2

8

T3

833256

auto[1]

158011

1

T3

1216

T4

8

T9

2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	14652489	1			T1	3901		T2	1		T3	103544
all_values[0]	auto[0]	auto[1]	89362	1			T3	764		T14	244		T18	232
all_values[0]	auto[1]	auto[0]	210965	1			T3	1		T58	4		T33	4
all_values[0]	auto[1]	auto[1]	2606	1			T58	3		T33	2		T59	1
all_values[1]	auto[0]	auto[0]	14564949	1			T1	3901		T2	1		T3	40351
all_values[1]	auto[0]	auto[1]	43812	1			T3	99		T14	44		T18	130
all_values[1]	auto[1]	auto[0]	345365	1			T3	63658		T58	6		T33	3
all_values[1]	auto[1]	auto[1]	1296	1			T3	201		T136	169		T150	3
all_values[2]	auto[0]	auto[0]	14562209	1			T1	3901		T2	1		T3	40430
all_values[2]	auto[0]	auto[1]	16142	1			T3	19		T14	42		T18	82
all_values[2]	auto[1]	auto[0]	376377	1			T3	63751		T58	1		T59	2
all_values[2]	auto[1]	auto[1]	694	1			T3	109		T58	1		T33	3
all_values[3]	auto[0]	auto[0]	14640415	1			T1	3901		T2	1		T3	40449
all_values[3]	auto[0]	auto[1]	381	1			T58	2		T33	1		T59	3
all_values[3]	auto[1]	auto[0]	314257	1			T3	63857		T58	2		T33	5
all_values[3]	auto[1]	auto[1]	369	1			T3	3		T58	2		T33	1
all_values[4]	auto[0]	auto[0]	14617066	1			T1	3901		T2	1		T3	40446
all_values[4]	auto[0]	auto[1]	364	1			T3	1		T9	2		T58	3
all_values[4]	auto[1]	auto[0]	337596	1			T3	63857		T58	2		T33	3
all_values[4]	auto[1]	auto[1]	396	1			T3	5		T58	4		T33	1
all_values[5]	auto[0]	auto[0]	14757854	1			T1	3901		T2	1		T3	104305
all_values[5]	auto[0]	auto[1]	825	1			T3	2		T4	8		T17	9
all_values[5]	auto[1]	auto[0]	196447	1			T33	4		T59	1		T46	1
all_values[5]	auto[1]	auto[1]	296	1			T3	2		T58	2		T33	1
all_values[6]	auto[0]	auto[0]	14727955	1			T1	3901		T2	1		T3	40446
all_values[6]	auto[0]	auto[1]	340	1			T58	1		T33	2		T59	1
all_values[6]	auto[1]	auto[0]	226762	1			T3	63858		T58	6		T33	6
all_values[6]	auto[1]	auto[1]	365	1			T3	5		T58	2		T33	1
all_values[7]	auto[0]	auto[0]	14675203	1			T1	3901		T2	1		T3	104302
all_values[7]	auto[0]	auto[1]	400	1			T3	3		T58	1		T33	1
all_values[7]	auto[1]	auto[0]	279456	1			T3	1		T58	2		T33	4
all_values[7]	auto[1]	auto[1]	363	1			T3	3		T58	3		T33	1