Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	81389	1			T2	2		T3	463		T6	8
auto[SpiFlashAddrCfg]	18426	1			T3	95		T11	2		T13	6
auto[SpiFlashAddr3b]	22259	1			T2	6		T3	141		T6	6
auto[SpiFlashAddr4b]	18157	1			T2	4		T3	97		T6	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

80840

1

T2

12

T3

405

T6

16

auto[1]

59391

1

T3

391

T11

14

T12

4

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

74700

1

T2

8

T3

468

T6

2

auto[1]

65531

1

T2

4

T3

328

T6

14

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	92676	1			T2	6		T3	529		T6	8
values[1]	2671	1			T3	18		T11	2		T13	1
values[2]	3436	1			T3	12		T11	2		T13	1
values[3]	3482	1			T2	4		T3	20		T8	2
values[4]	3560	1			T3	34		T9	5		T11	2
values[5]	3422	1			T3	13		T9	8		T13	2
values[6]	3494	1			T3	18		T6	2		T14	12
values[7]	3458	1			T3	10		T13	3		T14	6
values[8]	24032	1			T2	2		T3	142		T6	6

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

70865

1

T2

12

T3

399

T6

16

auto[1]

69366

1

T3

397

T9

24

T18

391

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

135143

1

T2

12

T3

764

T6

16

write

5088

1

T3

32

T8

10

T14

12

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

47415

1

T2

2

T3

262

T6

6

valids[0x1]

92816

1

T2

10

T3

534

T6

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	3894	1			T3	17		T8	2		T13	2
internal_process_ops[0x5a]	3832	1			T3	33		T14	10		T18	16
internal_process_ops[0x05]	48174	1			T3	263		T6	4		T14	24
internal_process_ops[0x35]	3726	1			T3	21		T14	8		T18	11
internal_process_ops[0x15]	3824	1			T2	2		T3	27		T6	4
internal_process_ops[0x03]	2627	1			T2	4		T3	20		T6	2
internal_process_ops[0x0b]	2636	1			T2	4		T3	11		T14	2
internal_process_ops[0x3b]	2664	1			T3	10		T6	4		T9	6
internal_process_ops[0x6b]	2543	1			T3	11		T8	2		T9	5
internal_process_ops[0xbb]	2644	1			T3	18		T6	2		T9	8
internal_process_ops[0xeb]	2570	1			T2	2		T3	9		T8	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

137752

1

T2

12

T3

779

T6

16

auto[1]

2479

1

T3

17

T14

6

T18

6

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

135269

1

T2

12

T3

757

T6

16

auto[1]

4962

1

T3

39

T14

9

T18

10

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

24625

1

T2

2

T3

124

T6

8

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

14018

1

T3

96

T11

4

T14

19

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

5003

1

T3

18

T13

1

T14

43

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

4382

1

T3

21

T11

2

T13

5

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

6041

1

T2

6

T3

39

T6

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

5209

1

T3

34

T11

6

T14

27

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

5078

1

T2

4

T3

15

T6

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

4144

1

T3

34

T11

2

T12

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

170

1

T3

1

T8

8

T27

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

131

1

T3

2

T27

1

T21

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

120

1

T31

4

T32

1

T166

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

146

1

T3

2

T14

3

T26

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

155

1

T3

1

T167

2

T168

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

121

1

T3

3

T27

1

T28

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

117

1

T28

2

T160

2

T169

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

143

1

T29

4

T31

4

T160

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

197

1

T14

1

T21

1

T170

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

138

1

T14

2

T27

1

T21

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

141

1

T27

4

T42

2

T21

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

167

1

T28

2

T31

1

T32

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

180

1

T3

6

T8

2

T14

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

129

1

T21

2

T168

2

T30

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

126

1

T14

3

T27

1

T42

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

184

1

T3

3

T14

1

T132

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

24155

1

T3

111

T18

137

T19

145

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

17346

1

T3

124

T18

52

T19

80

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

4257

1

T3

26

T18

27

T19

17

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

3593

1

T3

18

T18

24

T19

29

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

5078

1

T3

27

T9

13

T18

36

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

4588

1

T3

39

T18

26

T19

36

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

3981

1

T3

23

T9

11

T18

42

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

3645

1

T3

15

T18

33

T19

20

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

170

1

T3

2

T45

1

T38

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

170

1

T18

1

T19

1

T38

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

186

1

T18

1

T19

1

T38

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

152

1

T3

1

T45

3

T54

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

171

1

T19

1

T91

4

T134

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

159

1

T3

5

T45

1

T134

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

154

1

T3

3

T18

2

T19

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

171

1

T18

2

T45

2

T91

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

203

1

T3

1

T18

1

T44

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

152

1

T45

2

T91

1

T171

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

173

1

T18

2

T19

1

T45

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

172

1

T3

1

T45

2

T91

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

188

1

T3

1

T18

2

T19

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

188

1

T18

2

T19

3

T38

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

158

1

T19

6

T33

4

T59

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

156

1

T18

1

T45

4

T38

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	9642	1			T3	59		T8	2		T10	2
auto[0]	values[0]	valids[0x1]	35374	1			T2	6		T3	199		T6	8
auto[0]	values[1]	valids[0x1]	1320	1			T3	7		T11	2		T13	1
auto[0]	values[2]	valids[0x0]	1229	1			T3	3		T11	2		T13	1
auto[0]	values[2]	valids[0x1]	665	1			T3	2		T27	3		T42	5
auto[0]	values[3]	valids[0x0]	1168	1			T3	4		T8	2		T14	1
auto[0]	values[3]	valids[0x1]	738	1			T2	4		T3	5		T14	4
auto[0]	values[4]	valids[0x0]	1269	1			T3	12		T13	2		T14	3
auto[0]	values[4]	valids[0x1]	713	1			T3	3		T11	2		T14	1
auto[0]	values[5]	valids[0x0]	1200	1			T3	6		T13	2		T14	5
auto[0]	values[5]	valids[0x1]	687	1			T14	5		T27	11		T42	4
auto[0]	values[6]	valids[0x0]	1203	1			T3	6		T14	7		T26	6
auto[0]	values[6]	valids[0x1]	682	1			T3	7		T6	2		T14	5
auto[0]	values[7]	valids[0x0]	1191	1			T13	3		T14	6		T27	7
auto[0]	values[7]	valids[0x1]	725	1			T3	3		T27	1		T42	1
auto[0]	values[8]	valids[0x0]	8227	1			T2	2		T3	51		T6	6
auto[0]	values[8]	valids[0x1]	4832	1			T3	32		T11	2		T13	1
auto[1]	values[0]	valids[0x0]	10206	1			T3	59		T18	81		T19	79
auto[1]	values[0]	valids[0x1]	37454	1			T3	212		T9	5		T18	141
auto[1]	values[1]	valids[0x1]	1351	1			T3	11		T18	13		T19	13
auto[1]	values[2]	valids[0x0]	919	1			T3	4		T18	13		T19	3
auto[1]	values[2]	valids[0x1]	623	1			T3	3		T18	4		T19	4
auto[1]	values[3]	valids[0x0]	964	1			T3	3		T18	2		T19	6
auto[1]	values[3]	valids[0x1]	612	1			T3	8		T18	5		T19	8
auto[1]	values[4]	valids[0x0]	991	1			T3	8		T9	5		T18	4
auto[1]	values[4]	valids[0x1]	587	1			T3	11		T18	7		T19	6
auto[1]	values[5]	valids[0x0]	884	1			T3	4		T9	8		T18	10
auto[1]	values[5]	valids[0x1]	651	1			T3	3		T18	5		T19	2
auto[1]	values[6]	valids[0x0]	961	1			T3	2		T18	12		T19	6
auto[1]	values[6]	valids[0x1]	648	1			T3	3		T18	6		T19	7
auto[1]	values[7]	valids[0x0]	851	1			T3	3		T18	11		T19	2
auto[1]	values[7]	valids[0x1]	691	1			T3	4		T18	6		T19	6
auto[1]	values[8]	valids[0x0]	6510	1			T3	38		T9	6		T18	28
auto[1]	values[8]	valids[0x1]	4463	1			T3	21		T18	43		T19	22