Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38761

1

T2

12

T3

237

T6

12

auto[1]

48890

1

T3

273

T14

22

T18

41

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32743

1

T2

10

T3

199

T6

12

auto[1]

54908

1

T2

2

T3

311

T13

2

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	14094	1			T2	2		T3	68		T6	4
auto[524288:1048575]	10477	1			T3	47		T6	1		T14	13
auto[1048576:1572863]	9605	1			T3	77		T13	1		T14	13
auto[1572864:2097151]	11014	1			T2	3		T3	18		T6	1
auto[2097152:2621439]	9851	1			T3	107		T6	3		T14	10
auto[2621440:3145727]	11084	1			T3	60		T6	3		T9	2
auto[3145728:3670015]	10628	1			T2	2		T3	79		T14	25
auto[3670016:4194303]	10898	1			T2	5		T3	54		T9	6

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

85768

1

T2

12

T3

489

T6

12

auto[1]

1883

1

T3

21

T19

1

T27

7

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

69431

1

T2

12

T3

404

T6

12

auto[1]

18220

1

T3

106

T14

7

T18

60

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	3941	1			T2	1		T3	16		T6	4
auto[0]	auto[0]	auto[0:524287]	auto[1]	1494	1			T2	1		T3	5		T13	1
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	2688	1			T3	17		T6	1		T14	8
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	1098	1			T3	9		T14	5		T18	4
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	2520	1			T3	23		T14	7		T18	3
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	972	1			T3	20		T13	1		T14	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	2793	1			T2	3		T3	9		T6	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	979	1			T3	2		T14	1		T18	11
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	2466	1			T3	31		T6	3		T14	6
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	920	1			T3	11		T14	2		T18	3
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	2655	1			T3	14		T6	3		T9	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	1035	1			T3	8		T14	2		T18	5
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	2682	1			T2	2		T3	10		T14	11
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	993	1			T3	4		T14	5		T18	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	2687	1			T2	4		T3	16		T9	6
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	1030	1			T2	1		T3	2		T14	3
auto[0]	auto[1]	auto[0:524287]	auto[0]	714	1			T3	6		T14	2		T18	7
auto[0]	auto[1]	auto[0:524287]	auto[1]	299	1			T3	1		T14	1		T18	3
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	581	1			T3	2		T19	1		T27	3
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	277	1			T3	1		T19	1		T27	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	609	1			T3	3		T14	3		T18	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	287	1			T3	1		T14	1		T19	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	716	1			T3	1		T18	1		T19	5
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	315	1			T3	1		T19	3		T38	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	665	1			T3	2		T18	5		T27	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	330	1			T3	3		T18	3		T27	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	684	1			T3	5		T27	1		T42	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	307	1			T3	3		T27	1		T42	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	721	1			T3	2		T18	6		T19	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	328	1			T3	2		T18	3		T19	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	655	1			T3	3		T18	9		T218	4
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	320	1			T3	4		T18	7		T21	5
auto[1]	auto[0]	auto[0:524287]	auto[0]	634	1			T3	2		T14	1		T18	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	5541	1			T3	27		T14	2		T18	7
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	475	1			T3	6		T19	1		T27	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	4085	1			T3	12		T19	1		T27	20
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	437	1			T3	6		T19	4		T27	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	3753	1			T3	24		T19	12		T27	21
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	491	1			T3	2		T14	1		T19	8
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	4327	1			T3	3		T14	1		T19	29
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	448	1			T3	9		T14	1		T19	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	3890	1			T3	36		T14	1		T19	5
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	463	1			T3	1		T18	1		T19	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	4647	1			T3	24		T18	2		T19	9
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	500	1			T3	1		T14	3		T18	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	4056	1			T3	25		T14	6		T18	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	475	1			T3	5		T14	3		T18	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	4256	1			T3	24		T14	3		T18	8
auto[1]	auto[1]	auto[0:524287]	auto[0]	133	1			T3	3		T18	1		T45	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	1338	1			T3	8		T18	2		T45	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	126	1			T19	1		T45	1		T38	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	1147	1			T19	11		T45	1		T38	3
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	119	1			T19	3		T45	2		T31	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	908	1			T19	7		T45	7		T31	17
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	152	1			T19	1		T54	2		T31	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	1241	1			T19	4		T54	29		T31	29
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	109	1			T3	1		T18	1		T27	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	1023	1			T3	14		T18	1		T27	4
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	140	1			T3	2		T45	1		T30	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	1153	1			T3	3		T45	1		T30	4
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	129	1			T3	1		T18	2		T45	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	1219	1			T3	34		T18	8		T45	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	135	1			T28	1		T168	1		T30	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	1340	1			T28	3		T168	3		T30	2

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	30191	1			T2	12		T3	190		T6	12
auto[0]	auto[0]	auto[1]	762	1			T3	7		T19	1		T27	5
auto[0]	auto[1]	auto[0]	7592	1			T3	36		T14	7		T18	45
auto[0]	auto[1]	auto[1]	216	1			T3	4		T27	1		T54	4
auto[1]	auto[0]	auto[0]	37771	1			T3	198		T14	22		T18	26
auto[1]	auto[0]	auto[1]	707	1			T3	9		T27	1		T42	2
auto[1]	auto[1]	auto[0]	10214	1			T3	65		T18	15		T19	27
auto[1]	auto[1]	auto[1]	198	1			T3	1		T45	1		T54	1