Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

41968

1

T2

12

T3

209

T6

16

auto[1]

28897

1

T3

190

T11

14

T12

4

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	9304	1			T3	22		T12	4		T14	20
values[1]	8182	1			T14	20		T27	40		T42	20
values[2]	8050	1			T3	89		T14	44		T36	4
values[3]	9967	1			T3	25		T13	20		T14	46
values[4]	8564	1			T2	12		T3	65		T8	20
values[5]	8367	1			T3	54		T10	2		T14	43
values[6]	9629	1			T11	14		T14	20		T210	12
values[7]	8802	1			T3	144		T6	16		T14	40

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	8532	1			T3	21		T14	60		T37	6
values[1]	7768	1			T3	42		T14	20		T197	12
values[2]	8372	1			T3	76		T11	14		T14	20
values[3]	8909	1			T10	2		T26	20		T27	196
values[4]	8690	1			T3	62		T27	80		T42	29
values[5]	9636	1			T3	99		T8	20		T14	63
values[6]	9280	1			T2	12		T3	25		T12	4
values[7]	9678	1			T3	74		T6	16		T13	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	586	1			T14	5		T37	6		T31	8
auto[0]	values[0]	values[1]	609	1			T3	14		T30	20		T78	26
auto[0]	values[0]	values[2]	762	1			T27	20		T21	27		T190	18
auto[0]	values[0]	values[3]	591	1			T28	10		T32	20		T160	54
auto[0]	values[0]	values[4]	508	1			T21	13		T31	22		T182	12
auto[0]	values[0]	values[5]	672	1			T27	11		T220	8		T76	8
auto[0]	values[0]	values[6]	905	1			T221	8		T32	13		T33	14
auto[0]	values[0]	values[7]	1050	1			T169	9		T203	6		T217	8
auto[0]	values[1]	values[0]	735	1			T222	18		T166	114		T76	9
auto[0]	values[1]	values[1]	441	1			T28	13		T31	26		T46	14
auto[0]	values[1]	values[2]	615	1			T28	15		T32	18		T46	23
auto[0]	values[1]	values[3]	936	1			T27	7		T223	6		T31	18
auto[0]	values[1]	values[4]	560	1			T27	13		T21	13		T160	20
auto[0]	values[1]	values[5]	709	1			T42	17		T21	7		T166	6
auto[0]	values[1]	values[6]	522	1			T224	2		T30	28		T169	14
auto[0]	values[1]	values[7]	448	1			T14	11		T28	12		T33	16
auto[0]	values[2]	values[0]	455	1			T3	14		T14	12		T28	70
auto[0]	values[2]	values[1]	535	1			T3	12		T197	12		T21	12
auto[0]	values[2]	values[2]	544	1			T27	10		T170	30		T85	14
auto[0]	values[2]	values[3]	568	1			T21	10		T32	18		T33	10
auto[0]	values[2]	values[4]	689	1			T3	14		T27	54		T31	14
auto[0]	values[2]	values[5]	443	1			T3	17		T36	4		T218	14
auto[0]	values[2]	values[6]	701	1			T14	16		T27	11		T28	79
auto[0]	values[2]	values[7]	552	1			T30	24		T166	12		T136	16
auto[0]	values[3]	values[0]	967	1			T27	14		T21	8		T225	4
auto[0]	values[3]	values[1]	546	1			T42	34		T182	10		T73	14
auto[0]	values[3]	values[2]	647	1			T226	4		T132	14		T168	17
auto[0]	values[3]	values[3]	648	1			T27	25		T42	14		T200	14
auto[0]	values[3]	values[4]	586	1			T46	25		T199	22		T184	17
auto[0]	values[3]	values[5]	1005	1			T14	17		T21	13		T158	18
auto[0]	values[3]	values[6]	701	1			T3	16		T30	14		T166	10
auto[0]	values[3]	values[7]	805	1			T13	11		T14	16		T136	12
auto[0]	values[4]	values[0]	550	1			T161	64		T182	10		T76	12
auto[0]	values[4]	values[1]	506	1			T14	11		T201	24		T31	12
auto[0]	values[4]	values[2]	552	1			T42	18		T21	10		T227	2
auto[0]	values[4]	values[3]	818	1			T21	15		T205	30		T32	76
auto[0]	values[4]	values[4]	493	1			T3	13		T228	8		T169	12
auto[0]	values[4]	values[5]	884	1			T3	15		T8	20		T182	15
auto[0]	values[4]	values[6]	615	1			T2	12		T34	2		T21	15
auto[0]	values[4]	values[7]	647	1			T3	11		T32	14		T85	10
auto[0]	values[5]	values[0]	689	1			T21	27		T133	10		T229	4
auto[0]	values[5]	values[1]	656	1			T85	13		T182	15		T230	6
auto[0]	values[5]	values[2]	341	1			T27	3		T42	13		T231	11
auto[0]	values[5]	values[3]	844	1			T10	2		T21	9		T32	14
auto[0]	values[5]	values[4]	741	1			T232	4		T127	26		T168	12
auto[0]	values[5]	values[5]	591	1			T14	14		T31	9		T33	9
auto[0]	values[5]	values[6]	529	1			T14	14		T168	25		T30	11
auto[0]	values[5]	values[7]	673	1			T3	10		T32	9		T182	14
auto[0]	values[6]	values[0]	642	1			T14	12		T233	2		T32	14
auto[0]	values[6]	values[1]	445	1			T28	10		T30	8		T31	12
auto[0]	values[6]	values[2]	844	1			T31	12		T234	6		T76	10
auto[0]	values[6]	values[3]	635	1			T27	9		T42	11		T21	18
auto[0]	values[6]	values[4]	836	1			T42	16		T21	11		T33	14
auto[0]	values[6]	values[5]	731	1			T210	12		T27	7		T32	11
auto[0]	values[6]	values[6]	800	1			T27	13		T30	16		T76	66
auto[0]	values[6]	values[7]	734	1			T21	13		T166	6		T169	10
auto[0]	values[7]	values[0]	429	1			T32	16		T169	35		T136	27
auto[0]	values[7]	values[1]	615	1			T27	21		T235	4		T168	12
auto[0]	values[7]	values[2]	782	1			T3	23		T14	13		T27	12
auto[0]	values[7]	values[3]	350	1			T30	13		T31	25		T160	22
auto[0]	values[7]	values[4]	634	1			T3	11		T21	11		T32	13
auto[0]	values[7]	values[5]	741	1			T3	39		T14	15		T167	20
auto[0]	values[7]	values[6]	707	1			T28	11		T31	11		T85	15
auto[0]	values[7]	values[7]	873	1			T6	16		T27	16		T42	16
auto[1]	values[0]	values[0]	557	1			T14	15		T31	29		T33	13
auto[1]	values[0]	values[1]	531	1			T3	8		T30	26		T236	14
auto[1]	values[0]	values[2]	474	1			T27	20		T21	13		T33	13
auto[1]	values[0]	values[3]	277	1			T28	10		T32	20		T160	10
auto[1]	values[0]	values[4]	502	1			T21	11		T31	18		T182	8
auto[1]	values[0]	values[5]	557	1			T27	59		T237	16		T76	12
auto[1]	values[0]	values[6]	377	1			T12	4		T32	7		T33	6
auto[1]	values[0]	values[7]	346	1			T169	11		T203	14		T217	12
auto[1]	values[1]	values[0]	408	1			T166	8		T76	52		T47	9
auto[1]	values[1]	values[1]	422	1			T28	7		T31	61		T238	10
auto[1]	values[1]	values[2]	382	1			T28	48		T32	9		T46	30
auto[1]	values[1]	values[3]	360	1			T27	13		T31	12		T33	8
auto[1]	values[1]	values[4]	495	1			T27	7		T21	7		T160	6
auto[1]	values[1]	values[5]	577	1			T42	3		T21	13		T166	18
auto[1]	values[1]	values[6]	240	1			T30	4		T169	6		T239	18
auto[1]	values[1]	values[7]	332	1			T14	9		T28	34		T33	12
auto[1]	values[2]	values[0]	311	1			T3	7		T14	8		T28	19
auto[1]	values[2]	values[1]	529	1			T3	8		T21	8		T28	10
auto[1]	values[2]	values[2]	431	1			T27	17		T85	8		T166	8
auto[1]	values[2]	values[3]	381	1			T26	20		T21	10		T32	5
auto[1]	values[2]	values[4]	532	1			T3	8		T27	6		T31	32
auto[1]	values[2]	values[5]	416	1			T3	9		T28	5		T29	28
auto[1]	values[2]	values[6]	522	1			T14	8		T27	45		T28	4
auto[1]	values[2]	values[7]	441	1			T30	89		T166	8		T136	4
auto[1]	values[3]	values[0]	455	1			T27	6		T21	15		T166	5
auto[1]	values[3]	values[1]	533	1			T42	7		T182	10		T73	6
auto[1]	values[3]	values[2]	288	1			T132	6		T168	7		T51	7
auto[1]	values[3]	values[3]	689	1			T27	131		T42	6		T31	7
auto[1]	values[3]	values[4]	379	1			T46	19		T199	8		T184	10
auto[1]	values[3]	values[5]	396	1			T14	3		T21	8		T160	13
auto[1]	values[3]	values[6]	680	1			T3	9		T30	10		T166	136
auto[1]	values[3]	values[7]	642	1			T13	9		T14	10		T136	12
auto[1]	values[4]	values[0]	251	1			T182	10		T76	8		T136	10
auto[1]	values[4]	values[1]	332	1			T14	9		T31	33		T240	6
auto[1]	values[4]	values[2]	444	1			T42	2		T21	19		T28	10
auto[1]	values[4]	values[3]	486	1			T21	8		T32	7		T166	13
auto[1]	values[4]	values[4]	385	1			T3	7		T169	8		T231	10
auto[1]	values[4]	values[5]	464	1			T3	10		T241	2		T182	5
auto[1]	values[4]	values[6]	570	1			T21	5		T32	15		T182	11
auto[1]	values[4]	values[7]	567	1			T3	9		T32	6		T85	10
auto[1]	values[5]	values[0]	530	1			T21	18		T30	70		T182	18
auto[1]	values[5]	values[1]	365	1			T85	8		T182	5		T183	17
auto[1]	values[5]	values[2]	329	1			T27	17		T42	25		T242	26
auto[1]	values[5]	values[3]	337	1			T21	11		T32	6		T166	9
auto[1]	values[5]	values[4]	433	1			T168	8		T165	17		T184	37
auto[1]	values[5]	values[5]	356	1			T14	9		T31	11		T33	11
auto[1]	values[5]	values[6]	368	1			T14	6		T168	5		T30	9
auto[1]	values[5]	values[7]	585	1			T3	44		T32	16		T182	7
auto[1]	values[6]	values[0]	624	1			T14	8		T32	6		T85	4
auto[1]	values[6]	values[1]	280	1			T28	10		T30	12		T31	8
auto[1]	values[6]	values[2]	353	1			T11	14		T101	6		T31	8
auto[1]	values[6]	values[3]	538	1			T27	11		T42	9		T21	2
auto[1]	values[6]	values[4]	409	1			T42	13		T21	18		T208	20
auto[1]	values[6]	values[5]	655	1			T27	13		T32	9		T46	18
auto[1]	values[6]	values[6]	494	1			T27	7		T30	24		T76	11
auto[1]	values[6]	values[7]	609	1			T21	10		T166	14		T169	16
auto[1]	values[7]	values[0]	343	1			T32	4		T169	8		T136	13
auto[1]	values[7]	values[1]	423	1			T27	29		T168	8		T31	8
auto[1]	values[7]	values[2]	584	1			T3	53		T14	7		T27	47
auto[1]	values[7]	values[3]	451	1			T30	95		T31	8		T160	10
auto[1]	values[7]	values[4]	508	1			T3	9		T21	9		T32	7
auto[1]	values[7]	values[5]	439	1			T3	9		T14	5		T166	2
auto[1]	values[7]	values[6]	549	1			T28	9		T31	9		T85	7
auto[1]	values[7]	values[7]	374	1			T27	4		T42	4		T31	13