Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	917	1			T3	7		T14	3		T27	5
auto[ReadAddrCrossIntoMailbox]	652	1			T3	3		T14	4		T210	2
auto[ReadAddrCrossOutOfMailbox]	725	1			T3	1		T14	4		T34	2
auto[ReadAddrCrossAllMailbox]	478	1			T3	3		T14	3		T210	4
auto[ReadAddrOutsideMailbox]	8290	1			T2	10		T3	45		T6	8

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5513

1

T2

5

T3

31

T6

4

auto[1]

5549

1

T2

5

T3

28

T6

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	1861	1			T2	4		T3	12		T6	2
read_ops[0x0b]	1852	1			T2	4		T3	8		T14	2
read_ops[0x3b]	1928	1			T3	9		T6	4		T11	2
read_ops[0x6b]	1740	1			T3	8		T8	2		T13	1
read_ops[0xbb]	1865	1			T3	14		T6	2		T13	2
read_ops[0xeb]	1816	1			T2	2		T3	8		T8	4

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	82	1			T3	1		T27	1		T31	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	78	1			T14	1		T157	1		T166	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	64	1			T3	1		T14	1		T27	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	38	1			T27	1		T21	1		T200	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	65	1			T27	1		T21	1		T28	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	53	1			T14	1		T33	2		T160	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	38	1			T3	1		T166	1		T49	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	28	1			T21	1		T166	1		T182	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	704	1			T2	2		T3	2		T6	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	711	1			T2	2		T3	7		T6	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	87	1			T3	1		T14	1		T42	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	71	1			T3	2		T27	1		T30	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	44	1			T27	1		T21	2		T231	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	51	1			T27	2		T30	1		T160	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	57	1			T28	1		T160	1		T166	3
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	53	1			T21	1		T30	1		T31	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	42	1			T30	1		T32	1		T157	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	45	1			T28	1		T157	1		T46	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	675	1			T2	2		T3	1		T14	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	727	1			T2	2		T3	4		T197	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	78	1			T21	1		T28	1		T30	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	72	1			T14	1		T27	1		T21	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	46	1			T210	1		T21	1		T32	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	63	1			T210	1		T27	1		T42	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	56	1			T210	1		T42	1		T160	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	70	1			T210	1		T28	1		T30	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	42	1			T14	1		T21	1		T200	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	38	1			T14	1		T200	1		T166	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	744	1			T3	7		T6	2		T11	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	719	1			T3	2		T6	2		T11	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	59	1			T3	1		T232	2		T31	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	72	1			T27	1		T232	2		T28	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	48	1			T3	2		T27	1		T136	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	62	1			T14	2		T21	1		T160	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	46	1			T14	1		T197	1		T30	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	67	1			T197	1		T27	2		T32	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	29	1			T3	1		T42	1		T76	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	40	1			T166	1		T182	1		T46	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	631	1			T3	1		T8	1		T13	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	686	1			T3	3		T8	1		T14	3
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	79	1			T27	1		T76	2		T136	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	88	1			T168	1		T31	1		T85	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	70	1			T27	1		T30	1		T31	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	61	1			T14	1		T27	1		T168	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	60	1			T34	1		T32	1		T160	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	66	1			T3	1		T14	1		T34	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	43	1			T210	2		T42	1		T31	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	47	1			T210	2		T27	2		T28	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	699	1			T3	7		T6	1		T13	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	652	1			T3	6		T6	1		T14	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	76	1			T3	1		T28	1		T32	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	75	1			T3	1		T28	2		T168	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	56	1			T33	1		T76	1		T199	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	49	1			T28	2		T166	1		T136	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	63	1			T21	1		T233	1		T30	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	69	1			T14	1		T233	1		T160	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	42	1			T3	1		T42	1		T30	4
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	44	1			T14	1		T42	1		T28	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	688	1			T2	1		T3	3		T8	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	654	1			T2	1		T3	2		T8	2