Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	14955422	1			T1	3901		T2	1		T3	104309
all_pins[1]	14955422	1			T1	3901		T2	1		T3	104309
all_pins[2]	14955422	1			T1	3901		T2	1		T3	104309
all_pins[3]	14955422	1			T1	3901		T2	1		T3	104309
all_pins[4]	14955422	1			T1	3901		T2	1		T3	104309
all_pins[5]	14955422	1			T1	3901		T2	1		T3	104309
all_pins[6]	14955422	1			T1	3901		T2	1		T3	104309
all_pins[7]	14955422	1			T1	3901		T2	1		T3	104309

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	119408923	1			T1	31208		T2	8		T3	770284
values[0x1]	234453	1			T3	64188		T58	17		T33	10
transitions[0x0=>0x1]	232543	1			T3	64070		T58	13		T33	9
transitions[0x1=>0x0]	232567	1			T3	64070		T58	13		T33	9

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	14952710	1			T1	3901		T2	1		T3	104309
all_pins[0]	values[0x1]	2712	1			T58	3		T33	2		T59	1
all_pins[0]	transitions[0x0=>0x1]	2432	1			T58	3		T33	2		T59	1
all_pins[0]	transitions[0x1=>0x0]	1060	1			T3	212		T136	181		T150	3
all_pins[1]	values[0x0]	14954082	1			T1	3901		T2	1		T3	104097
all_pins[1]	values[0x1]	1340	1			T3	212		T136	182		T150	3
all_pins[1]	transitions[0x0=>0x1]	1127	1			T3	103		T136	181		T150	2
all_pins[1]	transitions[0x1=>0x0]	497	1			T3	3		T58	1		T33	3
all_pins[2]	values[0x0]	14954712	1			T1	3901		T2	1		T3	104197
all_pins[2]	values[0x1]	710	1			T3	112		T58	1		T33	3
all_pins[2]	transitions[0x0=>0x1]	608	1			T3	109		T58	1		T33	2
all_pins[2]	transitions[0x1=>0x0]	267	1			T58	2		T59	1		T46	1
all_pins[3]	values[0x0]	14955053	1			T1	3901		T2	1		T3	104306
all_pins[3]	values[0x1]	369	1			T3	3		T58	2		T33	1
all_pins[3]	transitions[0x0=>0x1]	268	1			T58	1		T33	1		T59	1
all_pins[3]	transitions[0x1=>0x0]	295	1			T3	2		T58	3		T33	1
all_pins[4]	values[0x0]	14955026	1			T1	3901		T2	1		T3	104304
all_pins[4]	values[0x1]	396	1			T3	5		T58	4		T33	1
all_pins[4]	transitions[0x0=>0x1]	320	1			T3	4		T58	3		T33	1
all_pins[4]	transitions[0x1=>0x0]	2427	1			T3	1		T58	1		T33	1
all_pins[5]	values[0x0]	14952919	1			T1	3901		T2	1		T3	104307
all_pins[5]	values[0x1]	2503	1			T3	2		T58	2		T33	1
all_pins[5]	transitions[0x0=>0x1]	1551	1			T3	2		T58	2		T33	1
all_pins[5]	transitions[0x1=>0x0]	225108	1			T3	63851		T58	2		T33	1
all_pins[6]	values[0x0]	14729362	1			T1	3901		T2	1		T3	40458
all_pins[6]	values[0x1]	226060	1			T3	63851		T58	2		T33	1
all_pins[6]	transitions[0x0=>0x1]	225969	1			T3	63849		T58	2		T33	1
all_pins[6]	transitions[0x1=>0x0]	272	1			T3	1		T58	3		T33	1
all_pins[7]	values[0x0]	14955059	1			T1	3901		T2	1		T3	104306
all_pins[7]	values[0x1]	363	1			T3	3		T58	3		T33	1
all_pins[7]	transitions[0x0=>0x1]	268	1			T3	3		T58	1		T33	1
all_pins[7]	transitions[0x1=>0x0]	2641	1			T58	1		T33	2		T46	2