Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	8619	1			T3	101		T14	44		T27	27
values[1]	8105	1			T3	40		T14	66		T37	6
values[2]	9140	1			T3	41		T14	40		T197	12
values[3]	9554	1			T2	12		T3	48		T210	12
values[4]	9853	1			T3	96		T8	20		T14	60
values[5]	8746	1			T3	48		T14	43		T36	4
values[6]	8616	1			T6	16		T10	2		T11	14
values[7]	8232	1			T3	25		T12	4		T27	96

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	7658	1			T3	46		T6	16		T11	14
values[1]	9729	1			T13	20		T14	60		T27	76
values[2]	8750	1			T3	20		T34	2		T26	20
values[3]	9419	1			T3	21		T14	63		T27	60
values[4]	8921	1			T2	12		T3	96		T27	20
values[5]	8859	1			T3	97		T14	26		T27	149
values[6]	8793	1			T3	25		T14	40		T37	6
values[7]	8736	1			T3	94		T8	20		T10	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

69706

1

T2

12

T3

389

T6

16

auto[1]

1159

1

T3

10

T14

6

T26

4

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	986	1			T27	27		T226	4		T166	187
auto[0]	values[0]	values[1]	1078	1			T205	30		T166	184		T135	20
auto[0]	values[0]	values[2]	1125	1			T132	19		T28	82		T30	20
auto[0]	values[0]	values[3]	1335	1			T28	20		T32	45		T33	20
auto[0]	values[0]	values[4]	1022	1			T166	120		T169	51		T185	8
auto[0]	values[0]	values[5]	1183	1			T3	77		T42	20		T21	29
auto[0]	values[0]	values[6]	737	1			T21	21		T31	32		T182	32
auto[0]	values[0]	values[7]	1002	1			T3	24		T14	43		T85	45
auto[0]	values[1]	values[0]	944	1			T3	20		T169	20		T76	23
auto[0]	values[1]	values[1]	1230	1			T14	20		T33	19		T85	21
auto[0]	values[1]	values[2]	1008	1			T28	20		T168	30		T166	20
auto[0]	values[1]	values[3]	937	1			T14	20		T21	23		T191	20
auto[0]	values[1]	values[4]	875	1			T27	20		T42	18		T30	21
auto[0]	values[1]	values[5]	1326	1			T3	20		T14	23		T27	69
auto[0]	values[1]	values[6]	871	1			T37	6		T160	98		T182	20
auto[0]	values[1]	values[7]	762	1			T160	20		T166	20		T182	20
auto[0]	values[2]	values[0]	1021	1			T14	20		T101	6		T42	79
auto[0]	values[2]	values[1]	940	1			T28	24		T243	32		T169	24
auto[0]	values[2]	values[2]	1371	1			T3	20		T27	30		T223	6
auto[0]	values[2]	values[3]	978	1			T3	21		T28	20		T30	71
auto[0]	values[2]	values[4]	1531	1			T28	20		T166	49		T74	16
auto[0]	values[2]	values[5]	849	1			T30	20		T32	20		T166	51
auto[0]	values[2]	values[6]	1276	1			T14	20		T197	12		T32	20
auto[0]	values[2]	values[7]	1031	1			T200	14		T46	30		T136	91
auto[0]	values[3]	values[0]	889	1			T27	20		T21	21		T28	46
auto[0]	values[3]	values[1]	1343	1			T27	20		T30	93		T31	20
auto[0]	values[3]	values[2]	1020	1			T206	24		T51	50		T203	22
auto[0]	values[3]	values[3]	1260	1			T31	37		T76	20		T230	6
auto[0]	values[3]	values[4]	1299	1			T2	12		T31	20		T32	24
auto[0]	values[3]	values[5]	1104	1			T30	20		T33	24		T85	41
auto[0]	values[3]	values[6]	1417	1			T210	12		T201	24		T133	10
auto[0]	values[3]	values[7]	1061	1			T3	45		T21	20		T170	30
auto[0]	values[4]	values[0]	1074	1			T21	20		T28	20		T244	29
auto[0]	values[4]	values[1]	1485	1			T14	20		T33	20		T166	78
auto[0]	values[4]	values[2]	924	1			T27	40		T224	2		T220	8
auto[0]	values[4]	values[3]	1414	1			T14	20		T27	20		T30	20
auto[0]	values[4]	values[4]	1135	1			T3	70		T32	19		T245	26
auto[0]	values[4]	values[5]	974	1			T31	44		T182	23		T136	20
auto[0]	values[4]	values[6]	1089	1			T14	20		T21	28		T28	62
auto[0]	values[4]	values[7]	1615	1			T3	22		T8	20		T27	60
auto[0]	values[5]	values[0]	833	1			T3	24		T27	20		T33	25
auto[0]	values[5]	values[1]	836	1			T14	20		T225	4		T127	26
auto[0]	values[5]	values[2]	1368	1			T26	16		T27	20		T21	38
auto[0]	values[5]	values[3]	1158	1			T14	21		T42	40		T31	20
auto[0]	values[5]	values[4]	1203	1			T3	22		T237	16		T219	54
auto[0]	values[5]	values[5]	893	1			T235	4		T161	64		T166	18
auto[0]	values[5]	values[6]	1302	1			T30	108		T32	20		T46	45
auto[0]	values[5]	values[7]	1018	1			T36	4		T21	20		T28	62
auto[0]	values[6]	values[0]	795	1			T6	16		T11	14		T168	20
auto[0]	values[6]	values[1]	1361	1			T13	20		T31	67		T160	72
auto[0]	values[6]	values[2]	887	1			T34	2		T27	44		T218	14
auto[0]	values[6]	values[3]	1222	1			T27	20		T21	43		T30	18
auto[0]	values[6]	values[4]	933	1			T28	20		T31	45		T199	30
auto[0]	values[6]	values[5]	1194	1			T27	59		T21	40		T29	24
auto[0]	values[6]	values[6]	995	1			T27	109		T21	24		T232	4
auto[0]	values[6]	values[7]	1104	1			T10	2		T30	20		T85	22
auto[0]	values[7]	values[0]	1002	1			T12	4		T42	20		T190	18
auto[0]	values[7]	values[1]	1314	1			T27	55		T42	29		T31	18
auto[0]	values[7]	values[2]	880	1			T32	20		T33	20		T160	25
auto[0]	values[7]	values[3]	953	1			T27	20		T21	20		T227	2
auto[0]	values[7]	values[4]	768	1			T166	103		T246	2		T189	20
auto[0]	values[7]	values[5]	1197	1			T27	20		T28	20		T30	20
auto[0]	values[7]	values[6]	956	1			T3	24		T21	20		T30	20
auto[0]	values[7]	values[7]	1013	1			T164	20		T247	2		T51	20
auto[1]	values[0]	values[0]	10	1			T166	3		T51	1		T203	2
auto[1]	values[0]	values[1]	23	1			T76	4		T213	1		T248	3
auto[1]	values[0]	values[2]	22	1			T132	1		T28	1		T169	2
auto[1]	values[0]	values[3]	28	1			T249	3		T250	2		T217	4
auto[1]	values[0]	values[4]	26	1			T166	2		T169	3		T199	1
auto[1]	values[0]	values[5]	13	1			T166	2		T182	1		T76	1
auto[1]	values[0]	values[6]	15	1			T21	2		T31	1		T240	3
auto[1]	values[0]	values[7]	14	1			T14	1		T76	1		T47	2
auto[1]	values[1]	values[0]	21	1			T47	2		T183	4		T217	1
auto[1]	values[1]	values[1]	22	1			T33	1		T85	1		T250	1
auto[1]	values[1]	values[2]	22	1			T49	1		T251	1		T252	1
auto[1]	values[1]	values[3]	12	1			T215	2		T253	1		T254	1
auto[1]	values[1]	values[4]	18	1			T42	2		T30	3		T46	2
auto[1]	values[1]	values[5]	27	1			T14	3		T27	1		T30	1
auto[1]	values[1]	values[6]	18	1			T160	1		T217	2		T255	1
auto[1]	values[1]	values[7]	12	1			T189	1		T52	2		T256	6
auto[1]	values[2]	values[0]	13	1			T73	2		T217	1		T195	1
auto[1]	values[2]	values[1]	16	1			T28	2		T240	2		T196	1
auto[1]	values[2]	values[2]	19	1			T244	1		T191	2		T257	1
auto[1]	values[2]	values[3]	19	1			T30	2		T51	1		T258	1
auto[1]	values[2]	values[4]	22	1			T259	2		T250	1		T192	2
auto[1]	values[2]	values[5]	19	1			T166	2		T260	2		T261	2
auto[1]	values[2]	values[6]	20	1			T160	3		T76	1		T189	2
auto[1]	values[2]	values[7]	15	1			T46	3		T136	2		T258	1
auto[1]	values[3]	values[0]	21	1			T203	1		T262	1		T263	1
auto[1]	values[3]	values[1]	12	1			T164	2		T264	3		T265	1
auto[1]	values[3]	values[2]	25	1			T206	2		T51	1		T203	1
auto[1]	values[3]	values[3]	26	1			T199	1		T240	5		T215	1
auto[1]	values[3]	values[4]	24	1			T32	1		T73	1		T258	1
auto[1]	values[3]	values[5]	20	1			T33	4		T49	1		T165	1
auto[1]	values[3]	values[6]	24	1			T189	1		T250	1		T266	1
auto[1]	values[3]	values[7]	9	1			T3	3		T184	1		T258	1
auto[1]	values[4]	values[0]	19	1			T258	2		T248	1		T253	1
auto[1]	values[4]	values[1]	22	1			T166	1		T165	1		T203	1
auto[1]	values[4]	values[2]	7	1			T135	1		T136	1		T231	3
auto[1]	values[4]	values[3]	20	1			T76	2		T136	1		T189	2
auto[1]	values[4]	values[4]	27	1			T3	4		T32	1		T192	1
auto[1]	values[4]	values[5]	11	1			T31	1		T184	1		T261	1
auto[1]	values[4]	values[6]	13	1			T21	1		T28	1		T46	1
auto[1]	values[4]	values[7]	24	1			T31	2		T33	1		T217	1
auto[1]	values[5]	values[0]	13	1			T3	2		T160	2		T76	3
auto[1]	values[5]	values[1]	12	1			T136	1		T249	1		T251	1
auto[1]	values[5]	values[2]	28	1			T26	4		T21	2		T49	5
auto[1]	values[5]	values[3]	27	1			T14	2		T136	1		T240	3
auto[1]	values[5]	values[4]	9	1			T191	1		T267	1		T268	1
auto[1]	values[5]	values[5]	13	1			T166	2		T76	1		T260	3
auto[1]	values[5]	values[6]	17	1			T46	1		T261	2		T52	1
auto[1]	values[5]	values[7]	16	1			T28	1		T168	4		T199	2
auto[1]	values[6]	values[0]	5	1			T253	2		T269	1		T270	1
auto[1]	values[6]	values[1]	15	1			T160	1		T76	1		T165	3
auto[1]	values[6]	values[2]	21	1			T27	2		T135	1		T199	1
auto[1]	values[6]	values[3]	19	1			T30	2		T150	5		T189	1
auto[1]	values[6]	values[4]	11	1			T31	1		T261	2		T270	1
auto[1]	values[6]	values[5]	23	1			T29	4		T51	2		T203	1
auto[1]	values[6]	values[6]	15	1			T27	1		T169	1		T204	1
auto[1]	values[6]	values[7]	16	1			T169	2		T150	1		T189	2
auto[1]	values[7]	values[0]	12	1			T169	3		T267	3		T270	1
auto[1]	values[7]	values[1]	20	1			T27	1		T31	2		T32	1
auto[1]	values[7]	values[2]	23	1			T160	1		T47	2		T51	4
auto[1]	values[7]	values[3]	11	1			T33	1		T160	1		T182	1
auto[1]	values[7]	values[4]	18	1			T166	2		T271	4		T248	1
auto[1]	values[7]	values[5]	13	1			T169	1		T52	2		T272	1
auto[1]	values[7]	values[6]	28	1			T3	1		T31	1		T150	2
auto[1]	values[7]	values[7]	24	1			T215	2		T204	3		T273	1