Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5201

1

T1

19

T3

5

T7

1

auto[1]

5172

1

T1

17

T3

7

T7

2

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5451

1

T1

25

T3

9

T14

14

auto[1]

4922

1

T1

11

T3

3

T7

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8235

1

T1

25

T3

9

T7

3

auto[1]

2138

1

T1

11

T3

3

T14

5

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	2115	1			T1	7		T3	6		T14	3
valid[1]	2023	1			T1	6		T7	1		T14	4
valid[2]	2098	1			T1	7		T3	2		T7	1
valid[3]	2134	1			T1	8		T3	2		T7	1
valid[4]	2003	1			T1	8		T3	2		T14	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	327	1			T14	1		T18	1		T19	1
auto[0]	auto[0]	valid[0]	auto[1]	525	1			T1	1		T18	1		T19	1
auto[0]	auto[0]	valid[1]	auto[0]	337	1			T18	3		T19	1		T20	2
auto[0]	auto[0]	valid[1]	auto[1]	454	1			T1	1		T88	1		T89	1
auto[0]	auto[0]	valid[2]	auto[0]	330	1			T1	4		T14	1		T17	1
auto[0]	auto[0]	valid[2]	auto[1]	517	1			T1	1		T7	1		T25	1
auto[0]	auto[0]	valid[3]	auto[0]	354	1			T1	2		T18	3		T19	1
auto[0]	auto[0]	valid[3]	auto[1]	467	1			T1	4		T3	1		T19	2
auto[0]	auto[0]	valid[4]	auto[0]	315	1			T1	2		T3	1		T14	1
auto[0]	auto[0]	valid[4]	auto[1]	483	1			T1	1		T3	1		T19	1
auto[0]	auto[1]	valid[0]	auto[0]	372	1			T1	3		T3	4		T18	6
auto[0]	auto[1]	valid[0]	auto[1]	467	1			T3	1		T25	1		T88	1
auto[0]	auto[1]	valid[1]	auto[0]	306	1			T1	1		T14	3		T18	4
auto[0]	auto[1]	valid[1]	auto[1]	484	1			T1	1		T7	1		T25	1
auto[0]	auto[1]	valid[2]	auto[0]	325	1			T14	2		T18	2		T20	1
auto[0]	auto[1]	valid[2]	auto[1]	524	1			T1	1		T89	1		T282	3
auto[0]	auto[1]	valid[3]	auto[0]	324	1			T1	1		T3	1		T14	1
auto[0]	auto[1]	valid[3]	auto[1]	538	1			T7	1		T25	2		T282	5
auto[0]	auto[1]	valid[4]	auto[0]	323	1			T1	1		T18	1		T19	1
auto[0]	auto[1]	valid[4]	auto[1]	463	1			T1	1		T88	1		T89	1
auto[1]	auto[0]	valid[0]	auto[0]	205	1			T1	2		T18	1		T277	2
auto[1]	auto[0]	valid[1]	auto[0]	224	1			T19	1		T25	1		T44	2
auto[1]	auto[0]	valid[2]	auto[0]	196	1			T3	2		T17	1		T18	1
auto[1]	auto[0]	valid[3]	auto[0]	238	1			T1	1		T19	2		T44	1
auto[1]	auto[0]	valid[4]	auto[0]	229	1			T18	1		T19	2		T44	1
auto[1]	auto[1]	valid[0]	auto[0]	219	1			T1	1		T3	1		T14	2
auto[1]	auto[1]	valid[1]	auto[0]	218	1			T1	3		T14	1		T18	2
auto[1]	auto[1]	valid[2]	auto[0]	206	1			T1	1		T18	1		T19	1
auto[1]	auto[1]	valid[3]	auto[0]	213	1			T14	1		T18	1		T19	2
auto[1]	auto[1]	valid[4]	auto[0]	190	1			T1	3		T14	1		T18	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal