Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

140967

1

T1

569

T3

366

T4

16

auto[1]

52576

1

T1

126

T3

39

T7

39

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

141319

1

T1

438

T3

266

T4

10

auto[1]

52224

1

T1

257

T3

139

T4

6

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	99336	1			T1	336		T3	210		T4	6
others[1]	16229	1			T1	69		T3	40		T4	5
others[2]	16340	1			T1	62		T3	37		T4	1
others[3]	18616	1			T1	57		T3	37		T4	2
interest[1]	10711	1			T1	46		T3	16		T4	1
interest[4]	64807	1			T1	210		T3	140		T4	4
interest[64]	32311	1			T1	125		T3	65		T4	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	45393	1			T1	153		T3	117		T4	3
auto[0]	auto[0]	others[1]	7494	1			T1	30		T3	18		T4	3
auto[0]	auto[0]	others[2]	7459	1			T1	33		T3	26		T4	1
auto[0]	auto[0]	others[3]	8618	1			T1	24		T3	27		T4	2
auto[0]	auto[0]	interest[1]	4934	1			T1	25		T3	9		T4	1
auto[0]	auto[0]	interest[4]	29486	1			T1	97		T3	77		T4	2
auto[0]	auto[0]	interest[64]	14845	1			T1	47		T3	30		T14	39
auto[0]	auto[1]	others[0]	27357	1			T1	58		T3	18		T7	20
auto[0]	auto[1]	others[1]	4304	1			T1	14		T3	5		T7	3
auto[0]	auto[1]	others[2]	4388	1			T1	5		T3	2		T7	3
auto[0]	auto[1]	others[3]	4952	1			T1	6		T3	4		T7	2
auto[0]	auto[1]	interest[1]	2899	1			T1	13		T3	3		T7	6
auto[0]	auto[1]	interest[4]	18080	1			T1	35		T3	10		T7	13
auto[0]	auto[1]	interest[64]	8676	1			T1	30		T3	7		T7	5
auto[1]	auto[0]	others[0]	26586	1			T1	125		T3	75		T4	3
auto[1]	auto[0]	others[1]	4431	1			T1	25		T3	17		T4	2
auto[1]	auto[0]	others[2]	4493	1			T1	24		T3	9		T14	9
auto[1]	auto[0]	others[3]	5046	1			T1	27		T3	6		T14	17
auto[1]	auto[0]	interest[1]	2878	1			T1	8		T3	4		T14	10
auto[1]	auto[0]	interest[4]	17241	1			T1	78		T3	53		T4	2
auto[1]	auto[0]	interest[64]	8790	1			T1	48		T3	28		T4	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal