Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1494	1			T3	8		T58	8		T33	7
all_values[1]	1494	1			T3	8		T58	8		T33	7
all_values[2]	1494	1			T3	8		T58	8		T33	7
all_values[3]	1494	1			T3	8		T58	8		T33	7
all_values[4]	1494	1			T3	8		T58	8		T33	7
all_values[5]	1494	1			T3	8		T58	8		T33	7
all_values[6]	1494	1			T3	8		T58	8		T33	7
all_values[7]	1494	1			T3	8		T58	8		T33	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6440

1

T3

36

T58

32

T33

28

auto[1]

5512

1

T3

28

T58

32

T33

28

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4658

1

T3

23

T58

26

T33

31

auto[1]

7294

1

T3

41

T58

38

T33

25

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6764

1

T3

34

T58

37

T33

38

auto[1]

5188

1

T3

30

T58

27

T33

18

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	292	1			T3	1		T58	2		T33	2
all_values[0]	auto[0]	auto[0]	auto[1]	156	1			T3	2		T33	1		T59	3
all_values[0]	auto[0]	auto[1]	auto[0]	283	1			T58	2		T33	1		T136	4
all_values[0]	auto[0]	auto[1]	auto[1]	162	1			T58	2		T33	1		T59	1
all_values[0]	auto[1]	auto[0]	auto[1]	320	1			T3	5		T33	1		T59	1
all_values[0]	auto[1]	auto[1]	auto[1]	281	1			T58	2		T33	1		T59	1
all_values[1]	auto[0]	auto[0]	auto[0]	331	1			T3	2		T58	3		T33	3
all_values[1]	auto[0]	auto[0]	auto[1]	138	1			T59	1		T150	1		T164	1
all_values[1]	auto[0]	auto[1]	auto[0]	236	1			T3	2		T58	3		T33	3
all_values[1]	auto[0]	auto[1]	auto[1]	134	1			T136	1		T150	1		T165	1
all_values[1]	auto[1]	auto[0]	auto[1]	344	1			T3	3		T59	4		T136	2
all_values[1]	auto[1]	auto[1]	auto[1]	311	1			T3	1		T58	2		T33	1
all_values[2]	auto[0]	auto[0]	auto[0]	292	1			T3	2		T58	1		T33	3
all_values[2]	auto[0]	auto[0]	auto[1]	147	1			T58	1		T59	3		T46	1
all_values[2]	auto[0]	auto[1]	auto[0]	237	1			T3	1		T58	1		T59	1
all_values[2]	auto[0]	auto[1]	auto[1]	136	1			T3	1		T59	1		T46	1
all_values[2]	auto[1]	auto[0]	auto[1]	367	1			T3	1		T58	4		T59	1
all_values[2]	auto[1]	auto[1]	auto[1]	315	1			T3	3		T58	1		T33	4
all_values[3]	auto[0]	auto[0]	auto[0]	268	1			T3	4		T58	1		T33	3
all_values[3]	auto[0]	auto[0]	auto[1]	141	1			T58	1		T33	1		T59	1
all_values[3]	auto[0]	auto[1]	auto[0]	260	1			T3	1		T58	3		T33	1
all_values[3]	auto[0]	auto[1]	auto[1]	153	1			T3	1		T58	1		T46	1
all_values[3]	auto[1]	auto[0]	auto[1]	362	1			T58	1		T59	3		T46	4
all_values[3]	auto[1]	auto[1]	auto[1]	310	1			T3	2		T58	1		T33	2
all_values[4]	auto[0]	auto[0]	auto[0]	302	1			T3	1		T33	1		T59	1
all_values[4]	auto[0]	auto[0]	auto[1]	157	1			T58	2		T33	1		T59	3
all_values[4]	auto[0]	auto[1]	auto[0]	242	1			T3	1		T33	3		T136	3
all_values[4]	auto[0]	auto[1]	auto[1]	150	1			T3	3		T58	1		T33	1
all_values[4]	auto[1]	auto[0]	auto[1]	324	1			T3	2		T58	2		T59	2
all_values[4]	auto[1]	auto[1]	auto[1]	319	1			T3	1		T58	3		T33	1
all_values[5]	auto[0]	auto[0]	auto[0]	466	1			T3	4		T58	4		T33	2
all_values[5]	auto[0]	auto[1]	auto[0]	361	1			T33	1		T59	2		T136	1
all_values[5]	auto[1]	auto[0]	auto[1]	390	1			T3	4		T58	2		T33	3
all_values[5]	auto[1]	auto[1]	auto[1]	277	1			T58	2		T33	1		T59	3
all_values[6]	auto[0]	auto[0]	auto[0]	313	1			T58	1		T59	2		T46	4
all_values[6]	auto[0]	auto[0]	auto[1]	144	1			T58	1		T33	1		T46	1
all_values[6]	auto[0]	auto[1]	auto[0]	267	1			T3	2		T58	3		T33	3
all_values[6]	auto[0]	auto[1]	auto[1]	147	1			T3	3		T58	1		T59	2
all_values[6]	auto[1]	auto[0]	auto[1]	362	1			T3	1		T58	1		T33	2
all_values[6]	auto[1]	auto[1]	auto[1]	261	1			T3	2		T58	1		T33	1
all_values[7]	auto[0]	auto[0]	auto[0]	292	1			T3	2		T58	2		T33	3
all_values[7]	auto[0]	auto[0]	auto[1]	183	1			T59	1		T46	1		T136	1
all_values[7]	auto[0]	auto[1]	auto[0]	216	1			T33	2		T136	1		T165	2
all_values[7]	auto[0]	auto[1]	auto[1]	158	1			T3	1		T58	1		T33	1
all_values[7]	auto[1]	auto[0]	auto[1]	349	1			T3	2		T58	3		T33	1
all_values[7]	auto[1]	auto[1]	auto[1]	296	1			T3	3		T58	2		T59	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal