Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	11799265	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

12730341

1

T1

2429

T2

1

T3

906

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	15746337	1			T1	1048		T2	1		T3	12
values[0x0]	4390217	1			T1	976		T3	450		T4	428
values[0x1]	4393052	1			T1	938		T3	453		T4	461

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8558271	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

15971335

1

T1

2534

T2

1

T3

909

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	104106	1			T1	3		T3	1		T4	44
valid_sources[0x01]	92224	1			T1	15		T3	12		T4	4
valid_sources[0x02]	89272	1			T1	13		T4	44		T5	425
valid_sources[0x03]	89098	1			T1	14		T4	66		T5	517
valid_sources[0x04]	95510	1			T1	3		T3	8		T4	26
valid_sources[0x05]	97581	1			T1	12		T4	2		T5	462
valid_sources[0x06]	95607	1			T1	17		T3	1		T4	12
valid_sources[0x07]	97088	1			T1	5		T4	20		T5	404
valid_sources[0x08]	95523	1			T1	9		T3	2		T4	14
valid_sources[0x09]	93988	1			T1	8		T3	4		T4	30
valid_sources[0x0a]	94875	1			T1	8		T3	2		T4	13
valid_sources[0x0b]	95679	1			T1	17		T3	3		T4	38
valid_sources[0x0c]	90923	1			T1	11		T3	2		T4	16
valid_sources[0x0d]	90900	1			T1	8		T3	14		T4	37
valid_sources[0x0e]	95502	1			T1	16		T3	2		T4	17
valid_sources[0x0f]	95546	1			T1	11		T3	2		T4	14
valid_sources[0x10]	96038	1			T1	12		T4	1		T5	418
valid_sources[0x11]	89574	1			T1	9		T3	2		T4	30
valid_sources[0x12]	95595	1			T1	13		T3	11		T4	11
valid_sources[0x13]	94568	1			T1	10		T3	3		T4	10
valid_sources[0x14]	90666	1			T1	8		T3	1		T4	15
valid_sources[0x15]	93162	1			T1	14		T3	5		T4	36
valid_sources[0x16]	99674	1			T1	9		T3	14		T4	6
valid_sources[0x17]	89780	1			T1	4		T3	5		T5	443
valid_sources[0x18]	91399	1			T1	6		T3	8		T4	26
valid_sources[0x19]	91873	1			T1	14		T3	2		T4	24
valid_sources[0x1a]	100290	1			T1	6		T3	1		T4	4
valid_sources[0x1b]	99102	1			T1	9		T4	3		T5	482
valid_sources[0x1c]	95223	1			T1	11		T3	1		T4	11
valid_sources[0x1d]	101874	1			T1	11		T4	7		T5	453
valid_sources[0x1e]	94559	1			T1	5		T4	47		T5	396
valid_sources[0x1f]	92773	1			T1	9		T4	13		T5	442
valid_sources[0x20]	93695	1			T1	6		T3	12		T4	32
valid_sources[0x21]	97632	1			T1	18		T3	10		T4	7
valid_sources[0x22]	97775	1			T1	21		T3	1		T4	5
valid_sources[0x23]	91703	1			T1	12		T3	5		T4	13
valid_sources[0x24]	93566	1			T1	11		T4	35		T5	438
valid_sources[0x25]	91248	1			T1	6		T3	3		T4	43
valid_sources[0x26]	94861	1			T1	6		T3	1		T4	2
valid_sources[0x27]	96573	1			T1	11		T4	20		T5	489
valid_sources[0x28]	94399	1			T1	13		T3	1		T4	11
valid_sources[0x29]	92653	1			T1	20		T3	2		T4	13
valid_sources[0x2a]	98940	1			T1	16		T3	1		T4	38
valid_sources[0x2b]	89654	1			T1	6		T3	2		T4	28
valid_sources[0x2c]	95021	1			T1	23		T4	5		T5	442
valid_sources[0x2d]	92445	1			T1	5		T3	10		T4	63
valid_sources[0x2e]	96654	1			T1	12		T3	6		T5	440
valid_sources[0x2f]	91837	1			T1	22		T3	10		T4	4
valid_sources[0x30]	91105	1			T1	13		T3	7		T4	46
valid_sources[0x31]	96621	1			T1	9		T3	3		T4	74
valid_sources[0x32]	90948	1			T1	18		T3	2		T4	48
valid_sources[0x33]	90873	1			T1	9		T3	8		T4	13
valid_sources[0x34]	96140	1			T1	4		T5	424		T7	145
valid_sources[0x35]	105487	1			T1	8		T3	6		T4	17
valid_sources[0x36]	102963	1			T1	13		T3	1		T4	15
valid_sources[0x37]	97531	1			T1	7		T3	3		T4	27
valid_sources[0x38]	98947	1			T1	10		T3	1		T4	16
valid_sources[0x39]	100936	1			T1	6		T3	1		T4	33
valid_sources[0x3a]	95428	1			T1	13		T3	1		T4	77
valid_sources[0x3b]	93500	1			T1	9		T3	3		T4	35
valid_sources[0x3c]	96234	1			T1	12		T3	5		T4	32
valid_sources[0x3d]	95160	1			T1	31		T4	23		T5	460
valid_sources[0x3e]	91155	1			T1	13		T3	7		T4	16
valid_sources[0x3f]	97797	1			T1	17		T3	3		T4	17
valid_sources[0x40]	102119	1			T1	9		T3	1		T4	38
valid_sources[0x41]	102745	1			T1	11		T3	3		T4	31
valid_sources[0x42]	93456	1			T1	8		T3	4		T4	28
valid_sources[0x43]	104683	1			T1	22		T4	26		T5	462
valid_sources[0x44]	100812	1			T1	25		T3	11		T4	12
valid_sources[0x45]	100016	1			T1	13		T4	52		T5	471
valid_sources[0x46]	102566	1			T1	30		T5	476		T7	44
valid_sources[0x47]	96574	1			T1	4		T4	1		T5	473
valid_sources[0x48]	94283	1			T1	7		T3	3		T4	53
valid_sources[0x49]	99521	1			T1	18		T4	18		T5	435
valid_sources[0x4a]	94993	1			T1	5		T3	3		T5	436
valid_sources[0x4b]	90283	1			T1	11		T4	58		T5	422
valid_sources[0x4c]	98340	1			T1	6		T3	5		T4	4
valid_sources[0x4d]	88352	1			T1	14		T4	24		T5	510
valid_sources[0x4e]	98018	1			T1	19		T4	10		T5	403
valid_sources[0x4f]	96440	1			T1	15		T4	16		T5	478
valid_sources[0x50]	97436	1			T4	22		T5	436		T7	81
valid_sources[0x51]	90159	1			T1	21		T4	29		T5	408
valid_sources[0x52]	96901	1			T1	11		T3	4		T4	11
valid_sources[0x53]	95890	1			T1	7		T3	2		T4	58
valid_sources[0x54]	93843	1			T1	10		T3	9		T4	22
valid_sources[0x55]	104425	1			T1	9		T3	2		T4	1
valid_sources[0x56]	101284	1			T1	12		T4	7		T5	467
valid_sources[0x57]	91570	1			T1	9		T3	3		T4	16
valid_sources[0x58]	94881	1			T1	20		T3	3		T4	42
valid_sources[0x59]	93627	1			T1	9		T3	4		T4	21
valid_sources[0x5a]	98521	1			T1	18		T3	7		T4	20
valid_sources[0x5b]	98977	1			T1	14		T3	4		T4	9
valid_sources[0x5c]	95437	1			T1	22		T3	2		T4	28
valid_sources[0x5d]	98409	1			T1	7		T3	9		T4	31
valid_sources[0x5e]	89167	1			T1	9		T3	3		T4	5
valid_sources[0x5f]	92152	1			T1	8		T4	16		T5	456
valid_sources[0x60]	98918	1			T1	12		T4	16		T5	472
valid_sources[0x61]	99456	1			T1	12		T3	2		T4	5
valid_sources[0x62]	93298	1			T1	4		T3	6		T4	29
valid_sources[0x63]	101971	1			T1	15		T4	58		T5	461
valid_sources[0x64]	93903	1			T1	6		T3	8		T5	404
valid_sources[0x65]	95538	1			T1	5		T3	6		T4	52
valid_sources[0x66]	89401	1			T1	13		T4	16		T5	418
valid_sources[0x67]	97499	1			T1	4		T3	2		T4	22
valid_sources[0x68]	101601	1			T1	13		T4	12		T5	485
valid_sources[0x69]	89035	1			T1	6		T3	5		T4	2
valid_sources[0x6a]	102766	1			T1	15		T3	2		T4	1
valid_sources[0x6b]	96158	1			T1	14		T3	1		T4	22
valid_sources[0x6c]	97832	1			T1	15		T3	7		T4	87
valid_sources[0x6d]	92159	1			T1	5		T3	15		T4	37
valid_sources[0x6e]	94484	1			T1	9		T3	1		T4	33
valid_sources[0x6f]	97188	1			T1	9		T3	1		T4	9
valid_sources[0x70]	96073	1			T1	8		T3	2		T4	19
valid_sources[0x71]	92897	1			T1	16		T3	4		T5	482
valid_sources[0x72]	92482	1			T1	14		T3	21		T4	34
valid_sources[0x73]	95358	1			T1	5		T4	60		T5	444
valid_sources[0x74]	98492	1			T1	4		T3	6		T5	439
valid_sources[0x75]	96827	1			T1	10		T4	57		T5	492
valid_sources[0x76]	92664	1			T1	14		T3	7		T4	19
valid_sources[0x77]	97531	1			T1	12		T4	3		T5	439
valid_sources[0x78]	94396	1			T1	21		T4	90		T5	425
valid_sources[0x79]	94523	1			T1	16		T3	9		T4	34
valid_sources[0x7a]	94335	1			T1	12		T3	3		T4	23
valid_sources[0x7b]	94850	1			T1	10		T3	14		T4	11
valid_sources[0x7c]	99298	1			T1	12		T3	3		T4	51
valid_sources[0x7d]	100843	1			T1	24		T3	7		T4	30
valid_sources[0x7e]	95692	1			T1	5		T3	8		T4	4
valid_sources[0x7f]	93601	1			T1	11		T3	11		T5	379
valid_sources[0x80]	93050	1			T1	8		T4	25		T5	474

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4854938

1

T1

525

T2

1

T3

5

values[0x0]

all_enables

biggest_size

3969213

1

T1

971

T3

450

T4

427

values[0x1]

all_enables

biggest_size

3906190

1

T1

933

T3

451

T4

457