Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

11834516

1

T1

533

T3

9

T4

2490

full_word

12728252

1

T1

2429

T2

1

T3

906

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	24561978	1			T1	2962		T2	1		T3	915
auto[TlIntgErrCmd]	276	1			T94	2		T97	4		T100	4
auto[TlIntgErrData]	240	1			T94	4		T97	3		T100	8
auto[TlIntgErrBoth]	274	1			T94	4		T97	3		T100	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15749054

1

T1

1048

T2

1

T3

12

auto[1]

8813714

1

T1

1914

T3

903

T4

889

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	10893655	1			T1	523		T3	7		T4	2485
auto[TlIntgErrNone]	partial	auto[1]	940138	1			T1	10		T3	2		T4	5
auto[TlIntgErrNone]	full_word	auto[0]	4855070	1			T1	525		T2	1		T3	5
auto[TlIntgErrNone]	full_word	auto[1]	7873115	1			T1	1904		T3	901		T4	884
auto[TlIntgErrCmd]	partial	auto[0]	101	1			T94	1		T97	2		T100	2
auto[TlIntgErrCmd]	partial	auto[1]	151	1			T94	1		T97	2		T100	2
auto[TlIntgErrCmd]	full_word	auto[0]	9	1			T113	1		T176	1		T180	1
auto[TlIntgErrCmd]	full_word	auto[1]	15	1			T116	1		T181	2		T176	1
auto[TlIntgErrData]	partial	auto[0]	99	1			T94	2		T97	2		T100	4
auto[TlIntgErrData]	partial	auto[1]	120	1			T94	2		T97	1		T100	4
auto[TlIntgErrData]	full_word	auto[0]	10	1			T113	1		T180	1		T182	1
auto[TlIntgErrData]	full_word	auto[1]	11	1			T177	3		T183	2		T180	2
auto[TlIntgErrBoth]	partial	auto[0]	105	1			T94	1		T100	4		T117	1
auto[TlIntgErrBoth]	partial	auto[1]	147	1			T94	3		T97	2		T100	4
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T181	1		T177	1		T184	1
auto[TlIntgErrBoth]	full_word	auto[1]	17	1			T97	1		T113	1		T181	1