Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.fifo_h.reqfifo

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1101050734	28823131	0	0
DepthKnown_A	1101050734	1100794303	0	0
RvalidKnown_A	1101050734	1100794303	0	0
WreadyKnown_A	1101050734	1100794303	0	0
gen_passthru_fifo.paramCheckPass	2225	2225	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101050734	28823131	0	0
T1	117206	4815	0	0
T2	994	1	0	0
T3	134846	1753	0	0
T4	484321	6605	0	0
T5	362163	118846	0	0
T6	71138	917	0	0
T7	938511	17148	0	0
T8	25744	1792	0	0
T9	28820	925	0	0
T10	30614	914	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101050734	1100794303	0	0
T1	117206	117110	0	0
T2	994	939	0	0
T3	134846	134837	0	0
T4	484321	484228	0	0
T5	362163	362154	0	0
T6	71138	71076	0	0
T7	938511	938422	0	0
T8	25744	25645	0	0
T9	28820	28739	0	0
T10	30614	30520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101050734	1100794303	0	0
T1	117206	117110	0	0
T2	994	939	0	0
T3	134846	134837	0	0
T4	484321	484228	0	0
T5	362163	362154	0	0
T6	71138	71076	0	0
T7	938511	938422	0	0
T8	25744	25645	0	0
T9	28820	28739	0	0
T10	30614	30520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101050734	1100794303	0	0
T1	117206	117110	0	0
T2	994	939	0	0
T3	134846	134837	0	0
T4	484321	484228	0	0
T5	362163	362154	0	0
T6	71138	71076	0	0
T7	938511	938422	0	0
T8	25744	25645	0	0
T9	28820	28739	0	0
T10	30614	30520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2225	2225	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1101050734	56162531	0	0
DepthKnown_A	1101050734	1100794303	0	0
RvalidKnown_A	1101050734	1100794303	0	0
WreadyKnown_A	1101050734	1100794303	0	0
gen_passthru_fifo.paramCheckPass	2225	2225	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101050734	56162531	0	0
T1	117206	2962	0	0
T2	994	2	0	0
T3	134846	1158	0	0
T4	484321	22043	0	0
T5	362163	115137	0	0
T6	71138	917	0	0
T7	938511	17126	0	0
T8	25744	1382	0	0
T9	28820	925	0	0
T10	30614	914	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101050734	1100794303	0	0
T1	117206	117110	0	0
T2	994	939	0	0
T3	134846	134837	0	0
T4	484321	484228	0	0
T5	362163	362154	0	0
T6	71138	71076	0	0
T7	938511	938422	0	0
T8	25744	25645	0	0
T9	28820	28739	0	0
T10	30614	30520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101050734	1100794303	0	0
T1	117206	117110	0	0
T2	994	939	0	0
T3	134846	134837	0	0
T4	484321	484228	0	0
T5	362163	362154	0	0
T6	71138	71076	0	0
T7	938511	938422	0	0
T8	25744	25645	0	0
T9	28820	28739	0	0
T10	30614	30520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101050734	1100794303	0	0
T1	117206	117110	0	0
T2	994	939	0	0
T3	134846	134837	0	0
T4	484321	484228	0	0
T5	362163	362154	0	0
T6	71138	71076	0	0
T7	938511	938422	0	0
T8	25744	25645	0	0
T9	28820	28739	0	0
T10	30614	30520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2225	2225	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1101050734	6687442	0	0
DepthKnown_A	1101050734	1100794303	0	0
RvalidKnown_A	1101050734	1100794303	0	0
WreadyKnown_A	1101050734	1100794303	0	0
gen_passthru_fifo.paramCheckPass	2225	2225	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101050734	6687442	0	0
T1	117206	3707	0	0
T2	994	0	0	0
T3	134846	1670	0	0
T4	484321	1663	0	0
T5	362163	16637	0	0
T6	71138	832	0	0
T7	938511	0	0	0
T8	25744	1667	0	0
T9	28820	832	0	0
T10	30614	832	0	0
T11	0	21622	0	0
T12	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101050734	1100794303	0	0
T1	117206	117110	0	0
T2	994	939	0	0
T3	134846	134837	0	0
T4	484321	484228	0	0
T5	362163	362154	0	0
T6	71138	71076	0	0
T7	938511	938422	0	0
T8	25744	25645	0	0
T9	28820	28739	0	0
T10	30614	30520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101050734	1100794303	0	0
T1	117206	117110	0	0
T2	994	939	0	0
T3	134846	134837	0	0
T4	484321	484228	0	0
T5	362163	362154	0	0
T6	71138	71076	0	0
T7	938511	938422	0	0
T8	25744	25645	0	0
T9	28820	28739	0	0
T10	30614	30520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101050734	1100794303	0	0
T1	117206	117110	0	0
T2	994	939	0	0
T3	134846	134837	0	0
T4	484321	484228	0	0
T5	362163	362154	0	0
T6	71138	71076	0	0
T7	938511	938422	0	0
T8	25744	25645	0	0
T9	28820	28739	0	0
T10	30614	30520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2225	2225	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1101050734	7321172	0	0
DepthKnown_A	1101050734	1100794303	0	0
RvalidKnown_A	1101050734	1100794303	0	0
WreadyKnown_A	1101050734	1100794303	0	0
gen_passthru_fifo.paramCheckPass	2225	2225	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101050734	7321172	0	0
T1	117206	1856	0	0
T2	994	0	0	0
T3	134846	840	0	0
T4	484321	832	0	0
T5	362163	14144	0	0
T6	71138	832	0	0
T7	938511	0	0	0
T8	25744	837	0	0
T9	28820	832	0	0
T10	30614	832	0	0
T11	0	13312	0	0
T12	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101050734	1100794303	0	0
T1	117206	117110	0	0
T2	994	939	0	0
T3	134846	134837	0	0
T4	484321	484228	0	0
T5	362163	362154	0	0
T6	71138	71076	0	0
T7	938511	938422	0	0
T8	25744	25645	0	0
T9	28820	28739	0	0
T10	30614	30520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101050734	1100794303	0	0
T1	117206	117110	0	0
T2	994	939	0	0
T3	134846	134837	0	0
T4	484321	484228	0	0
T5	362163	362154	0	0
T6	71138	71076	0	0
T7	938511	938422	0	0
T8	25744	25645	0	0
T9	28820	28739	0	0
T10	30614	30520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101050734	1100794303	0	0
T1	117206	117110	0	0
T2	994	939	0	0
T3	134846	134837	0	0
T4	484321	484228	0	0
T5	362163	362154	0	0
T6	71138	71076	0	0
T7	938511	938422	0	0
T8	25744	25645	0	0
T9	28820	28739	0	0
T10	30614	30520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2225	2225	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1101050734	430758	0	0
DepthKnown_A	1101050734	1100794303	0	0
RvalidKnown_A	1101050734	1100794303	0	0
WreadyKnown_A	1101050734	1100794303	0	0
gen_passthru_fifo.paramCheckPass	2225	2225	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101050734	430758	0	0
T4	484321	1	0	0
T5	362163	2120	0	0
T6	71138	0	0	0
T7	938511	979	0	0
T8	25744	0	0	0
T9	28820	0	0	0
T10	30614	0	0	0
T11	106782	192	0	0
T12	40309	0	0	0
T13	1297	0	0	0
T14	0	1021	0	0
T15	0	1693	0	0
T17	0	519	0	0
T18	0	1302	0	0
T21	0	506	0	0
T22	0	64	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101050734	1100794303	0	0
T1	117206	117110	0	0
T2	994	939	0	0
T3	134846	134837	0	0
T4	484321	484228	0	0
T5	362163	362154	0	0
T6	71138	71076	0	0
T7	938511	938422	0	0
T8	25744	25645	0	0
T9	28820	28739	0	0
T10	30614	30520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101050734	1100794303	0	0
T1	117206	117110	0	0
T2	994	939	0	0
T3	134846	134837	0	0
T4	484321	484228	0	0
T5	362163	362154	0	0
T6	71138	71076	0	0
T7	938511	938422	0	0
T8	25744	25645	0	0
T9	28820	28739	0	0
T10	30614	30520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101050734	1100794303	0	0
T1	117206	117110	0	0
T2	994	939	0	0
T3	134846	134837	0	0
T4	484321	484228	0	0
T5	362163	362154	0	0
T6	71138	71076	0	0
T7	938511	938422	0	0
T8	25744	25645	0	0
T9	28820	28739	0	0
T10	30614	30520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2225	2225	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1101050734	1005752	0	0
DepthKnown_A	1101050734	1100794303	0	0
RvalidKnown_A	1101050734	1100794303	0	0
WreadyKnown_A	1101050734	1100794303	0	0
gen_passthru_fifo.paramCheckPass	2225	2225	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101050734	1005752	0	0
T4	484321	2	0	0
T5	362163	2118	0	0
T6	71138	0	0	0
T7	938511	979	0	0
T8	25744	0	0	0
T9	28820	0	0	0
T10	30614	0	0	0
T11	106782	192	0	0
T12	40309	0	0	0
T13	1297	0	0	0
T14	0	3067	0	0
T15	0	1693	0	0
T17	0	1907	0	0
T18	0	6072	0	0
T21	0	506	0	0
T22	0	348	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101050734	1100794303	0	0
T1	117206	117110	0	0
T2	994	939	0	0
T3	134846	134837	0	0
T4	484321	484228	0	0
T5	362163	362154	0	0
T6	71138	71076	0	0
T7	938511	938422	0	0
T8	25744	25645	0	0
T9	28820	28739	0	0
T10	30614	30520	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101050734	1100794303	0	0
T1	117206	117110	0	0
T2	994	939	0	0
T3	134846	134837	0	0
T4	484321	484228	0	0
T5	362163	362154	0	0
T6	71138	71076	0	0
T7	938511	938422	0	0
T8	25744	25645	0	0
T9	28820	28739	0	0
T10	30614	30520	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101050734	1100794303	0	0
T1	117206	117110	0	0
T2	994	939	0	0
T3	134846	134837	0	0
T4	484321	484228	0	0
T5	362163	362154	0	0
T6	71138	71076	0	0
T7	938511	938422	0	0
T8	25744	25645	0	0
T9	28820	28739	0	0
T10	30614	30520	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2225	2225	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0