Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T14
1	0	Covered	T5,T7,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T14
1	0	Unreachable
1	1	Covered	T5,T7,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T11
1	0	Covered	T4,T5,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T4,T5,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T7
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1837768193	1463323603	0	0
CheckNGreaterZero_A	5625	5625	0	0
GntImpliesReady_A	1837768193	8537952	0	0
GntImpliesValid_A	1837768193	8537952	0	0
GrantKnown_A	1837768193	1463323603	0	0
IdxKnown_A	1837768193	1463323603	0	0
IndexIsCorrect_A	1837768193	8537952	0	0
LockArbDecision_A	1837768193	0	0	0
NoReadyValidNoGrant_A	1837768193	0	0	0
ReadyAndValidImplyGrant_A	1837768193	8537952	0	0
ReqAndReadyImplyGrant_A	1837768193	8537952	0	0
ReqImpliesValid_A	1837768193	8537952	0	0
ReqStaysHighUntilGranted0_M	1837768193	0	0	0
RoundRobin_A	1837768193	9	0	1875
ValidKnown_A	1837768193	1463323603	0	0
gen_data_port_assertion.DataFlow_A	1837768193	8537952	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1837768193	1463323603	0	0
T1	229848	229018	0	0
T2	994	939	0	0
T3	303149	302851	0	0
T4	564191	563635	0	0
T5	2182879	1260620	0	0
T6	105202	88108	0	0
T7	1256363	1090374	0	0
T8	121478	72585	0	0
T9	77330	52617	0	0
T10	86422	58424	0	0
T11	954574	471722	0	0
T12	36864	36864	0	0
T14	0	148432	0	0
T15	0	225632	0	0
T16	0	144888	0	0
T17	0	55928	0	0
T18	0	79592	0	0
T19	0	67900	0	0
T20	0	12600	0	0
T22	81123	0	0	0
T42	0	792	0	0
T49	99994	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5625	5625	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1837768193	8537952	0	0
T1	117206	1856	0	0
T2	994	0	0	0
T3	134846	832	0	0
T4	564191	848	0	0
T5	2182879	36816	0	0
T6	105202	832	0	0
T7	1256363	9701	0	0
T8	121478	832	0	0
T9	77330	832	0	0
T10	86422	832	0	0
T11	954574	16490	0	0
T12	73728	0	0	0
T14	0	5310	0	0
T15	0	9641	0	0
T17	0	4988	0	0
T18	0	9742	0	0
T19	0	3981	0	0
T20	0	353	0	0
T21	0	4940	0	0
T22	162246	260	0	0
T45	0	117	0	0
T46	0	3600	0	0
T49	99994	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1837768193	8537952	0	0
T1	117206	1856	0	0
T2	994	0	0	0
T3	134846	832	0	0
T4	564191	848	0	0
T5	2182879	36816	0	0
T6	105202	832	0	0
T7	1256363	9701	0	0
T8	121478	832	0	0
T9	77330	832	0	0
T10	86422	832	0	0
T11	954574	16490	0	0
T12	73728	0	0	0
T14	0	5310	0	0
T15	0	9641	0	0
T17	0	4988	0	0
T18	0	9742	0	0
T19	0	3981	0	0
T20	0	353	0	0
T21	0	4940	0	0
T22	162246	260	0	0
T45	0	117	0	0
T46	0	3600	0	0
T49	99994	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1837768193	1463323603	0	0
T1	229848	229018	0	0
T2	994	939	0	0
T3	303149	302851	0	0
T4	564191	563635	0	0
T5	2182879	1260620	0	0
T6	105202	88108	0	0
T7	1256363	1090374	0	0
T8	121478	72585	0	0
T9	77330	52617	0	0
T10	86422	58424	0	0
T11	954574	471722	0	0
T12	36864	36864	0	0
T14	0	148432	0	0
T15	0	225632	0	0
T16	0	144888	0	0
T17	0	55928	0	0
T18	0	79592	0	0
T19	0	67900	0	0
T20	0	12600	0	0
T22	81123	0	0	0
T42	0	792	0	0
T49	99994	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1837768193	1463323603	0	0
T1	229848	229018	0	0
T2	994	939	0	0
T3	303149	302851	0	0
T4	564191	563635	0	0
T5	2182879	1260620	0	0
T6	105202	88108	0	0
T7	1256363	1090374	0	0
T8	121478	72585	0	0
T9	77330	52617	0	0
T10	86422	58424	0	0
T11	954574	471722	0	0
T12	36864	36864	0	0
T14	0	148432	0	0
T15	0	225632	0	0
T16	0	144888	0	0
T17	0	55928	0	0
T18	0	79592	0	0
T19	0	67900	0	0
T20	0	12600	0	0
T22	81123	0	0	0
T42	0	792	0	0
T49	99994	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1837768193	8537952	0	0
T1	117206	1856	0	0
T2	994	0	0	0
T3	134846	832	0	0
T4	564191	848	0	0
T5	2182879	36816	0	0
T6	105202	832	0	0
T7	1256363	9701	0	0
T8	121478	832	0	0
T9	77330	832	0	0
T10	86422	832	0	0
T11	954574	16490	0	0
T12	73728	0	0	0
T14	0	5310	0	0
T15	0	9641	0	0
T17	0	4988	0	0
T18	0	9742	0	0
T19	0	3981	0	0
T20	0	353	0	0
T21	0	4940	0	0
T22	162246	260	0	0
T45	0	117	0	0
T46	0	3600	0	0
T49	99994	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1837768193	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1837768193	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1837768193	8537952	0	0
T1	117206	1856	0	0
T2	994	0	0	0
T3	134846	832	0	0
T4	564191	848	0	0
T5	2182879	36816	0	0
T6	105202	832	0	0
T7	1256363	9701	0	0
T8	121478	832	0	0
T9	77330	832	0	0
T10	86422	832	0	0
T11	954574	16490	0	0
T12	73728	0	0	0
T14	0	5310	0	0
T15	0	9641	0	0
T17	0	4988	0	0
T18	0	9742	0	0
T19	0	3981	0	0
T20	0	353	0	0
T21	0	4940	0	0
T22	162246	260	0	0
T45	0	117	0	0
T46	0	3600	0	0
T49	99994	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1837768193	8537952	0	0
T1	117206	1856	0	0
T2	994	0	0	0
T3	134846	832	0	0
T4	564191	848	0	0
T5	2182879	36816	0	0
T6	105202	832	0	0
T7	1256363	9701	0	0
T8	121478	832	0	0
T9	77330	832	0	0
T10	86422	832	0	0
T11	954574	16490	0	0
T12	73728	0	0	0
T14	0	5310	0	0
T15	0	9641	0	0
T17	0	4988	0	0
T18	0	9742	0	0
T19	0	3981	0	0
T20	0	353	0	0
T21	0	4940	0	0
T22	162246	260	0	0
T45	0	117	0	0
T46	0	3600	0	0
T49	99994	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1837768193	8537952	0	0
T1	117206	1856	0	0
T2	994	0	0	0
T3	134846	832	0	0
T4	564191	848	0	0
T5	2182879	36816	0	0
T6	105202	832	0	0
T7	1256363	9701	0	0
T8	121478	832	0	0
T9	77330	832	0	0
T10	86422	832	0	0
T11	954574	16490	0	0
T12	73728	0	0	0
T14	0	5310	0	0
T15	0	9641	0	0
T17	0	4988	0	0
T18	0	9742	0	0
T19	0	3981	0	0
T20	0	353	0	0
T21	0	4940	0	0
T22	162246	260	0	0
T45	0	117	0	0
T46	0	3600	0	0
T49	99994	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1837768193	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1837768193	9	0	1875
T17	611807	1	0	1
T18	162614	2	0	1
T19	552841	0	0	1
T20	429898	0	0	1
T32	634782	0	0	1
T33	131741	0	0	1
T42	2516	0	0	1
T43	261956	0	0	1
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	1109	0	0	1
T57	1106	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1837768193	1463323603	0	0
T1	229848	229018	0	0
T2	994	939	0	0
T3	303149	302851	0	0
T4	564191	563635	0	0
T5	2182879	1260620	0	0
T6	105202	88108	0	0
T7	1256363	1090374	0	0
T8	121478	72585	0	0
T9	77330	52617	0	0
T10	86422	58424	0	0
T11	954574	471722	0	0
T12	36864	36864	0	0
T14	0	148432	0	0
T15	0	225632	0	0
T16	0	144888	0	0
T17	0	55928	0	0
T18	0	79592	0	0
T19	0	67900	0	0
T20	0	12600	0	0
T22	81123	0	0	0
T42	0	792	0	0
T49	99994	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1837768193	8537952	0	0
T1	117206	1856	0	0
T2	994	0	0	0
T3	134846	832	0	0
T4	564191	848	0	0
T5	2182879	36816	0	0
T6	105202	832	0	0
T7	1256363	9701	0	0
T8	121478	832	0	0
T9	77330	832	0	0
T10	86422	832	0	0
T11	954574	16490	0	0
T12	73728	0	0	0
T14	0	5310	0	0
T15	0	9641	0	0
T17	0	4988	0	0
T18	0	9742	0	0
T19	0	3981	0	0
T20	0	353	0	0
T21	0	4940	0	0
T22	162246	260	0	0
T45	0	117	0	0
T46	0	3600	0	0
T49	99994	0	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T14
1	0	Covered	T5,T7,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T14
1	0	Unreachable
1	1	Covered	T5,T7,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T7,T14
0	0	1	Unreachable
0	0	0	Covered	T5,T7,T14

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	370707041	82421757	0	0
CheckNGreaterZero_A	1875	1875	0	0
GntImpliesReady_A	370707041	1791752	0	0
GntImpliesValid_A	370707041	1791752	0	0
GrantKnown_A	370707041	82421757	0	0
IdxKnown_A	370707041	82421757	0	0
IndexIsCorrect_A	370707041	1791752	0	0
LockArbDecision_A	370707041	0	0	0
NoReadyValidNoGrant_A	370707041	0	0	0
ReadyAndValidImplyGrant_A	370707041	1791752	0	0
ReqAndReadyImplyGrant_A	370707041	1791752	0	0
ReqImpliesValid_A	370707041	1791752	0	0
ReqStaysHighUntilGranted0_M	370707041	0	0	0
RoundRobin_A	370707041	0	0	0
ValidKnown_A	370707041	82421757	0	0
gen_data_port_assertion.DataFlow_A	370707041	1791752	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370707041	82421757	0	0
T5	910358	204736	0	0
T6	17032	0	0	0
T7	158926	151952	0	0
T8	47867	0	0	0
T9	24255	0	0	0
T10	27904	0	0	0
T11	477287	0	0	0
T12	36864	0	0	0
T14	0	148432	0	0
T15	0	225632	0	0
T16	0	144888	0	0
T17	0	55928	0	0
T18	0	79592	0	0
T19	0	67900	0	0
T20	0	12600	0	0
T22	81123	0	0	0
T42	0	792	0	0
T49	99994	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1875	1875	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370707041	1791752	0	0
T5	910358	8283	0	0
T6	17032	0	0	0
T7	158926	6347	0	0
T8	47867	0	0	0
T9	24255	0	0	0
T10	27904	0	0	0
T11	477287	0	0	0
T12	36864	0	0	0
T14	0	5310	0	0
T15	0	9380	0	0
T17	0	2682	0	0
T18	0	2853	0	0
T19	0	2966	0	0
T20	0	345	0	0
T22	81123	0	0	0
T45	0	117	0	0
T46	0	3600	0	0
T49	99994	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370707041	1791752	0	0
T5	910358	8283	0	0
T6	17032	0	0	0
T7	158926	6347	0	0
T8	47867	0	0	0
T9	24255	0	0	0
T10	27904	0	0	0
T11	477287	0	0	0
T12	36864	0	0	0
T14	0	5310	0	0
T15	0	9380	0	0
T17	0	2682	0	0
T18	0	2853	0	0
T19	0	2966	0	0
T20	0	345	0	0
T22	81123	0	0	0
T45	0	117	0	0
T46	0	3600	0	0
T49	99994	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370707041	82421757	0	0
T5	910358	204736	0	0
T6	17032	0	0	0
T7	158926	151952	0	0
T8	47867	0	0	0
T9	24255	0	0	0
T10	27904	0	0	0
T11	477287	0	0	0
T12	36864	0	0	0
T14	0	148432	0	0
T15	0	225632	0	0
T16	0	144888	0	0
T17	0	55928	0	0
T18	0	79592	0	0
T19	0	67900	0	0
T20	0	12600	0	0
T22	81123	0	0	0
T42	0	792	0	0
T49	99994	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370707041	82421757	0	0
T5	910358	204736	0	0
T6	17032	0	0	0
T7	158926	151952	0	0
T8	47867	0	0	0
T9	24255	0	0	0
T10	27904	0	0	0
T11	477287	0	0	0
T12	36864	0	0	0
T14	0	148432	0	0
T15	0	225632	0	0
T16	0	144888	0	0
T17	0	55928	0	0
T18	0	79592	0	0
T19	0	67900	0	0
T20	0	12600	0	0
T22	81123	0	0	0
T42	0	792	0	0
T49	99994	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370707041	1791752	0	0
T5	910358	8283	0	0
T6	17032	0	0	0
T7	158926	6347	0	0
T8	47867	0	0	0
T9	24255	0	0	0
T10	27904	0	0	0
T11	477287	0	0	0
T12	36864	0	0	0
T14	0	5310	0	0
T15	0	9380	0	0
T17	0	2682	0	0
T18	0	2853	0	0
T19	0	2966	0	0
T20	0	345	0	0
T22	81123	0	0	0
T45	0	117	0	0
T46	0	3600	0	0
T49	99994	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370707041	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370707041	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370707041	1791752	0	0
T5	910358	8283	0	0
T6	17032	0	0	0
T7	158926	6347	0	0
T8	47867	0	0	0
T9	24255	0	0	0
T10	27904	0	0	0
T11	477287	0	0	0
T12	36864	0	0	0
T14	0	5310	0	0
T15	0	9380	0	0
T17	0	2682	0	0
T18	0	2853	0	0
T19	0	2966	0	0
T20	0	345	0	0
T22	81123	0	0	0
T45	0	117	0	0
T46	0	3600	0	0
T49	99994	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370707041	1791752	0	0
T5	910358	8283	0	0
T6	17032	0	0	0
T7	158926	6347	0	0
T8	47867	0	0	0
T9	24255	0	0	0
T10	27904	0	0	0
T11	477287	0	0	0
T12	36864	0	0	0
T14	0	5310	0	0
T15	0	9380	0	0
T17	0	2682	0	0
T18	0	2853	0	0
T19	0	2966	0	0
T20	0	345	0	0
T22	81123	0	0	0
T45	0	117	0	0
T46	0	3600	0	0
T49	99994	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370707041	1791752	0	0
T5	910358	8283	0	0
T6	17032	0	0	0
T7	158926	6347	0	0
T8	47867	0	0	0
T9	24255	0	0	0
T10	27904	0	0	0
T11	477287	0	0	0
T12	36864	0	0	0
T14	0	5310	0	0
T15	0	9380	0	0
T17	0	2682	0	0
T18	0	2853	0	0
T19	0	2966	0	0
T20	0	345	0	0
T22	81123	0	0	0
T45	0	117	0	0
T46	0	3600	0	0
T49	99994	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	370707041	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370707041	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370707041	82421757	0	0
T5	910358	204736	0	0
T6	17032	0	0	0
T7	158926	151952	0	0
T8	47867	0	0	0
T9	24255	0	0	0
T10	27904	0	0	0
T11	477287	0	0	0
T12	36864	0	0	0
T14	0	148432	0	0
T15	0	225632	0	0
T16	0	144888	0	0
T17	0	55928	0	0
T18	0	79592	0	0
T19	0	67900	0	0
T20	0	12600	0	0
T22	81123	0	0	0
T42	0	792	0	0
T49	99994	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370707041	1791752	0	0
T5	910358	8283	0	0
T6	17032	0	0	0
T7	158926	6347	0	0
T8	47867	0	0	0
T9	24255	0	0	0
T10	27904	0	0	0
T11	477287	0	0	0
T12	36864	0	0	0
T14	0	5310	0	0
T15	0	9380	0	0
T17	0	2682	0	0
T18	0	2853	0	0
T19	0	2966	0	0
T20	0	345	0	0
T22	81123	0	0	0
T45	0	117	0	0
T46	0	3600	0	0
T49	99994	0	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T11
1	0	Covered	T4,T5,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T4,T5,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T11
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	370707041	284716357	0	0
CheckNGreaterZero_A	1875	1875	0	0
GntImpliesReady_A	370707041	1404634	0	0
GntImpliesValid_A	370707041	1404634	0	0
GrantKnown_A	370707041	284716357	0	0
IdxKnown_A	370707041	284716357	0	0
IndexIsCorrect_A	370707041	1404634	0	0
LockArbDecision_A	370707041	0	0	0
NoReadyValidNoGrant_A	370707041	0	0	0
ReadyAndValidImplyGrant_A	370707041	1404634	0	0
ReqAndReadyImplyGrant_A	370707041	1404634	0	0
ReqImpliesValid_A	370707041	1404634	0	0
ReqStaysHighUntilGranted0_M	370707041	0	0	0
RoundRobin_A	370707041	0	0	0
ValidKnown_A	370707041	284716357	0	0
gen_data_port_assertion.DataFlow_A	370707041	1404634	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370707041	284716357	0	0
T1	112642	111908	0	0
T3	168303	168014	0	0
T4	79870	79407	0	0
T5	910358	693730	0	0
T6	17032	17032	0	0
T7	158926	0	0	0
T8	47867	46940	0	0
T9	24255	23878	0	0
T10	27904	27904	0	0
T11	477287	471722	0	0
T12	0	36864	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1875	1875	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370707041	1404634	0	0
T4	79870	11	0	0
T5	910358	9389	0	0
T6	17032	0	0	0
T7	158926	0	0	0
T8	47867	0	0	0
T9	24255	0	0	0
T10	27904	0	0	0
T11	477287	2946	0	0
T12	36864	0	0	0
T15	0	261	0	0
T17	0	2306	0	0
T18	0	6889	0	0
T19	0	1015	0	0
T20	0	8	0	0
T21	0	4940	0	0
T22	81123	260	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370707041	1404634	0	0
T4	79870	11	0	0
T5	910358	9389	0	0
T6	17032	0	0	0
T7	158926	0	0	0
T8	47867	0	0	0
T9	24255	0	0	0
T10	27904	0	0	0
T11	477287	2946	0	0
T12	36864	0	0	0
T15	0	261	0	0
T17	0	2306	0	0
T18	0	6889	0	0
T19	0	1015	0	0
T20	0	8	0	0
T21	0	4940	0	0
T22	81123	260	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370707041	284716357	0	0
T1	112642	111908	0	0
T3	168303	168014	0	0
T4	79870	79407	0	0
T5	910358	693730	0	0
T6	17032	17032	0	0
T7	158926	0	0	0
T8	47867	46940	0	0
T9	24255	23878	0	0
T10	27904	27904	0	0
T11	477287	471722	0	0
T12	0	36864	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370707041	284716357	0	0
T1	112642	111908	0	0
T3	168303	168014	0	0
T4	79870	79407	0	0
T5	910358	693730	0	0
T6	17032	17032	0	0
T7	158926	0	0	0
T8	47867	46940	0	0
T9	24255	23878	0	0
T10	27904	27904	0	0
T11	477287	471722	0	0
T12	0	36864	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370707041	1404634	0	0
T4	79870	11	0	0
T5	910358	9389	0	0
T6	17032	0	0	0
T7	158926	0	0	0
T8	47867	0	0	0
T9	24255	0	0	0
T10	27904	0	0	0
T11	477287	2946	0	0
T12	36864	0	0	0
T15	0	261	0	0
T17	0	2306	0	0
T18	0	6889	0	0
T19	0	1015	0	0
T20	0	8	0	0
T21	0	4940	0	0
T22	81123	260	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370707041	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370707041	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370707041	1404634	0	0
T4	79870	11	0	0
T5	910358	9389	0	0
T6	17032	0	0	0
T7	158926	0	0	0
T8	47867	0	0	0
T9	24255	0	0	0
T10	27904	0	0	0
T11	477287	2946	0	0
T12	36864	0	0	0
T15	0	261	0	0
T17	0	2306	0	0
T18	0	6889	0	0
T19	0	1015	0	0
T20	0	8	0	0
T21	0	4940	0	0
T22	81123	260	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370707041	1404634	0	0
T4	79870	11	0	0
T5	910358	9389	0	0
T6	17032	0	0	0
T7	158926	0	0	0
T8	47867	0	0	0
T9	24255	0	0	0
T10	27904	0	0	0
T11	477287	2946	0	0
T12	36864	0	0	0
T15	0	261	0	0
T17	0	2306	0	0
T18	0	6889	0	0
T19	0	1015	0	0
T20	0	8	0	0
T21	0	4940	0	0
T22	81123	260	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370707041	1404634	0	0
T4	79870	11	0	0
T5	910358	9389	0	0
T6	17032	0	0	0
T7	158926	0	0	0
T8	47867	0	0	0
T9	24255	0	0	0
T10	27904	0	0	0
T11	477287	2946	0	0
T12	36864	0	0	0
T15	0	261	0	0
T17	0	2306	0	0
T18	0	6889	0	0
T19	0	1015	0	0
T20	0	8	0	0
T21	0	4940	0	0
T22	81123	260	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	370707041	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370707041	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370707041	284716357	0	0
T1	112642	111908	0	0
T3	168303	168014	0	0
T4	79870	79407	0	0
T5	910358	693730	0	0
T6	17032	17032	0	0
T7	158926	0	0	0
T8	47867	46940	0	0
T9	24255	23878	0	0
T10	27904	27904	0	0
T11	477287	471722	0	0
T12	0	36864	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370707041	1404634	0	0
T4	79870	11	0	0
T5	910358	9389	0	0
T6	17032	0	0	0
T7	158926	0	0	0
T8	47867	0	0	0
T9	24255	0	0	0
T10	27904	0	0	0
T11	477287	2946	0	0
T12	36864	0	0	0
T15	0	261	0	0
T17	0	2306	0	0
T18	0	6889	0	0
T19	0	1015	0	0
T20	0	8	0	0
T21	0	4940	0	0
T22	81123	260	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T7
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1096354111	1096185489	0	0
CheckNGreaterZero_A	1875	1875	0	0
GntImpliesReady_A	1096354111	5341566	0	0
GntImpliesValid_A	1096354111	5341566	0	0
GrantKnown_A	1096354111	1096185489	0	0
IdxKnown_A	1096354111	1096185489	0	0
IndexIsCorrect_A	1096354111	5341566	0	0
LockArbDecision_A	1096354111	0	0	0
NoReadyValidNoGrant_A	1096354111	0	0	0
ReadyAndValidImplyGrant_A	1096354111	5341566	0	0
ReqAndReadyImplyGrant_A	1096354111	5341566	0	0
ReqImpliesValid_A	1096354111	5341566	0	0
ReqStaysHighUntilGranted0_M	1096354111	0	0	0
RoundRobin_A	1096354111	9	0	1875
ValidKnown_A	1096354111	1096185489	0	0
gen_data_port_assertion.DataFlow_A	1096354111	5341566	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096354111	1096185489	0	0
T1	117206	117110	0	0
T2	994	939	0	0
T3	134846	134837	0	0
T4	484321	484228	0	0
T5	362163	362154	0	0
T6	71138	71076	0	0
T7	938511	938422	0	0
T8	25744	25645	0	0
T9	28820	28739	0	0
T10	30614	30520	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1875	1875	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096354111	5341566	0	0
T1	117206	1856	0	0
T2	994	0	0	0
T3	134846	832	0	0
T4	484321	837	0	0
T5	362163	19144	0	0
T6	71138	832	0	0
T7	938511	3354	0	0
T8	25744	832	0	0
T9	28820	832	0	0
T10	30614	832	0	0
T11	0	13544	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096354111	5341566	0	0
T1	117206	1856	0	0
T2	994	0	0	0
T3	134846	832	0	0
T4	484321	837	0	0
T5	362163	19144	0	0
T6	71138	832	0	0
T7	938511	3354	0	0
T8	25744	832	0	0
T9	28820	832	0	0
T10	30614	832	0	0
T11	0	13544	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096354111	1096185489	0	0
T1	117206	117110	0	0
T2	994	939	0	0
T3	134846	134837	0	0
T4	484321	484228	0	0
T5	362163	362154	0	0
T6	71138	71076	0	0
T7	938511	938422	0	0
T8	25744	25645	0	0
T9	28820	28739	0	0
T10	30614	30520	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096354111	1096185489	0	0
T1	117206	117110	0	0
T2	994	939	0	0
T3	134846	134837	0	0
T4	484321	484228	0	0
T5	362163	362154	0	0
T6	71138	71076	0	0
T7	938511	938422	0	0
T8	25744	25645	0	0
T9	28820	28739	0	0
T10	30614	30520	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096354111	5341566	0	0
T1	117206	1856	0	0
T2	994	0	0	0
T3	134846	832	0	0
T4	484321	837	0	0
T5	362163	19144	0	0
T6	71138	832	0	0
T7	938511	3354	0	0
T8	25744	832	0	0
T9	28820	832	0	0
T10	30614	832	0	0
T11	0	13544	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096354111	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096354111	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096354111	5341566	0	0
T1	117206	1856	0	0
T2	994	0	0	0
T3	134846	832	0	0
T4	484321	837	0	0
T5	362163	19144	0	0
T6	71138	832	0	0
T7	938511	3354	0	0
T8	25744	832	0	0
T9	28820	832	0	0
T10	30614	832	0	0
T11	0	13544	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096354111	5341566	0	0
T1	117206	1856	0	0
T2	994	0	0	0
T3	134846	832	0	0
T4	484321	837	0	0
T5	362163	19144	0	0
T6	71138	832	0	0
T7	938511	3354	0	0
T8	25744	832	0	0
T9	28820	832	0	0
T10	30614	832	0	0
T11	0	13544	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096354111	5341566	0	0
T1	117206	1856	0	0
T2	994	0	0	0
T3	134846	832	0	0
T4	484321	837	0	0
T5	362163	19144	0	0
T6	71138	832	0	0
T7	938511	3354	0	0
T8	25744	832	0	0
T9	28820	832	0	0
T10	30614	832	0	0
T11	0	13544	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096354111	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096354111	9	0	1875
T17	611807	1	0	1
T18	162614	2	0	1
T19	552841	0	0	1
T20	429898	0	0	1
T32	634782	0	0	1
T33	131741	0	0	1
T42	2516	0	0	1
T43	261956	0	0	1
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	1109	0	0	1
T57	1106	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096354111	1096185489	0	0
T1	117206	117110	0	0
T2	994	939	0	0
T3	134846	134837	0	0
T4	484321	484228	0	0
T5	362163	362154	0	0
T6	71138	71076	0	0
T7	938511	938422	0	0
T8	25744	25645	0	0
T9	28820	28739	0	0
T10	30614	30520	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096354111	5341566	0	0
T1	117206	1856	0	0
T2	994	0	0	0
T3	134846	832	0	0
T4	484321	837	0	0
T5	362163	19144	0	0
T6	71138	832	0	0
T7	938511	3354	0	0
T8	25744	832	0	0
T9	28820	832	0	0
T10	30614	832	0	0
T11	0	13544	0	0