Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
6803 |
0 |
0 |
T93 |
15318 |
3 |
0 |
0 |
T94 |
38112 |
1 |
0 |
0 |
T95 |
12423 |
5 |
0 |
0 |
T96 |
11422 |
3 |
0 |
0 |
T97 |
25939 |
1 |
0 |
0 |
T98 |
4422 |
146 |
0 |
0 |
T99 |
9092 |
150 |
0 |
0 |
T100 |
67738 |
2 |
0 |
0 |
T101 |
5725 |
9 |
0 |
0 |
T115 |
9888 |
3 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
3377 |
0 |
0 |
T76 |
2287 |
2 |
0 |
0 |
T93 |
15318 |
20 |
0 |
0 |
T94 |
38112 |
34 |
0 |
0 |
T96 |
11422 |
15 |
0 |
0 |
T121 |
180389 |
410 |
0 |
0 |
T149 |
14479 |
17 |
0 |
0 |
T150 |
13525 |
66 |
0 |
0 |
T151 |
7141 |
3 |
0 |
0 |
T152 |
20642 |
45 |
0 |
0 |
T153 |
13402 |
60 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
3452 |
0 |
0 |
T93 |
15318 |
20 |
0 |
0 |
T94 |
38112 |
45 |
0 |
0 |
T96 |
11422 |
15 |
0 |
0 |
T115 |
9888 |
13 |
0 |
0 |
T121 |
180389 |
444 |
0 |
0 |
T149 |
14479 |
47 |
0 |
0 |
T150 |
13525 |
54 |
0 |
0 |
T151 |
7141 |
1 |
0 |
0 |
T152 |
20642 |
71 |
0 |
0 |
T153 |
13402 |
12 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
4204 |
0 |
0 |
T93 |
15318 |
24 |
0 |
0 |
T94 |
38112 |
63 |
0 |
0 |
T96 |
11422 |
28 |
0 |
0 |
T115 |
9888 |
25 |
0 |
0 |
T121 |
180389 |
428 |
0 |
0 |
T149 |
14479 |
42 |
0 |
0 |
T150 |
13525 |
26 |
0 |
0 |
T151 |
7141 |
7 |
0 |
0 |
T152 |
20642 |
64 |
0 |
0 |
T153 |
13402 |
57 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
16672 |
0 |
0 |
T93 |
15318 |
132 |
0 |
0 |
T94 |
38112 |
420 |
0 |
0 |
T96 |
11422 |
146 |
0 |
0 |
T115 |
9888 |
66 |
0 |
0 |
T121 |
180389 |
412 |
0 |
0 |
T149 |
14479 |
56 |
0 |
0 |
T150 |
13525 |
40 |
0 |
0 |
T151 |
7141 |
3 |
0 |
0 |
T152 |
20642 |
86 |
0 |
0 |
T153 |
13402 |
39 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
18543 |
0 |
0 |
T93 |
15318 |
138 |
0 |
0 |
T94 |
38112 |
815 |
0 |
0 |
T96 |
11422 |
114 |
0 |
0 |
T115 |
9888 |
11 |
0 |
0 |
T121 |
180389 |
478 |
0 |
0 |
T149 |
14479 |
30 |
0 |
0 |
T150 |
13525 |
65 |
0 |
0 |
T151 |
7141 |
15 |
0 |
0 |
T152 |
20642 |
71 |
0 |
0 |
T153 |
13402 |
51 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
16281 |
0 |
0 |
T93 |
15318 |
225 |
0 |
0 |
T94 |
38112 |
909 |
0 |
0 |
T96 |
11422 |
292 |
0 |
0 |
T115 |
9888 |
89 |
0 |
0 |
T121 |
180389 |
475 |
0 |
0 |
T149 |
14479 |
62 |
0 |
0 |
T150 |
13525 |
46 |
0 |
0 |
T151 |
7141 |
17 |
0 |
0 |
T152 |
20642 |
50 |
0 |
0 |
T153 |
13402 |
38 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
17642 |
0 |
0 |
T93 |
15318 |
143 |
0 |
0 |
T94 |
38112 |
601 |
0 |
0 |
T96 |
11422 |
14 |
0 |
0 |
T115 |
9888 |
111 |
0 |
0 |
T121 |
180389 |
465 |
0 |
0 |
T149 |
14479 |
40 |
0 |
0 |
T150 |
13525 |
61 |
0 |
0 |
T151 |
7141 |
23 |
0 |
0 |
T152 |
20642 |
79 |
0 |
0 |
T153 |
13402 |
24 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
16583 |
0 |
0 |
T93 |
15318 |
259 |
0 |
0 |
T94 |
38112 |
678 |
0 |
0 |
T96 |
11422 |
253 |
0 |
0 |
T115 |
9888 |
79 |
0 |
0 |
T121 |
180389 |
444 |
0 |
0 |
T149 |
14479 |
43 |
0 |
0 |
T150 |
13525 |
8 |
0 |
0 |
T151 |
7141 |
1 |
0 |
0 |
T152 |
20642 |
21 |
0 |
0 |
T153 |
13402 |
49 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
15791 |
0 |
0 |
T93 |
15318 |
135 |
0 |
0 |
T94 |
38112 |
749 |
0 |
0 |
T96 |
11422 |
136 |
0 |
0 |
T115 |
9888 |
8 |
0 |
0 |
T121 |
180389 |
450 |
0 |
0 |
T149 |
14479 |
66 |
0 |
0 |
T150 |
13525 |
21 |
0 |
0 |
T151 |
7141 |
6 |
0 |
0 |
T152 |
20642 |
94 |
0 |
0 |
T153 |
13402 |
52 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
17406 |
0 |
0 |
T93 |
15318 |
128 |
0 |
0 |
T94 |
38112 |
627 |
0 |
0 |
T96 |
11422 |
214 |
0 |
0 |
T115 |
9888 |
77 |
0 |
0 |
T121 |
180389 |
472 |
0 |
0 |
T149 |
14479 |
21 |
0 |
0 |
T150 |
13525 |
84 |
0 |
0 |
T151 |
7141 |
11 |
0 |
0 |
T152 |
20642 |
103 |
0 |
0 |
T153 |
13402 |
25 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
16757 |
0 |
0 |
T93 |
15318 |
418 |
0 |
0 |
T94 |
38112 |
714 |
0 |
0 |
T96 |
11422 |
139 |
0 |
0 |
T115 |
9888 |
92 |
0 |
0 |
T121 |
180389 |
455 |
0 |
0 |
T149 |
14479 |
58 |
0 |
0 |
T150 |
13525 |
65 |
0 |
0 |
T151 |
7141 |
4 |
0 |
0 |
T152 |
20642 |
72 |
0 |
0 |
T153 |
13402 |
76 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
8871 |
0 |
0 |
T93 |
15318 |
149 |
0 |
0 |
T94 |
38112 |
322 |
0 |
0 |
T96 |
11422 |
14 |
0 |
0 |
T115 |
9888 |
7 |
0 |
0 |
T121 |
180389 |
461 |
0 |
0 |
T149 |
14479 |
63 |
0 |
0 |
T150 |
13525 |
49 |
0 |
0 |
T151 |
7141 |
8 |
0 |
0 |
T152 |
20642 |
102 |
0 |
0 |
T153 |
13402 |
30 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
7762 |
0 |
0 |
T93 |
15318 |
66 |
0 |
0 |
T94 |
38112 |
123 |
0 |
0 |
T96 |
11422 |
86 |
0 |
0 |
T115 |
9888 |
30 |
0 |
0 |
T121 |
180389 |
436 |
0 |
0 |
T149 |
14479 |
40 |
0 |
0 |
T150 |
13525 |
37 |
0 |
0 |
T151 |
7141 |
8 |
0 |
0 |
T152 |
20642 |
47 |
0 |
0 |
T153 |
13402 |
43 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
8717 |
0 |
0 |
T93 |
15318 |
129 |
0 |
0 |
T94 |
38112 |
308 |
0 |
0 |
T96 |
11422 |
42 |
0 |
0 |
T115 |
9888 |
19 |
0 |
0 |
T121 |
180389 |
465 |
0 |
0 |
T149 |
14479 |
28 |
0 |
0 |
T150 |
13525 |
40 |
0 |
0 |
T151 |
7141 |
10 |
0 |
0 |
T152 |
20642 |
81 |
0 |
0 |
T153 |
13402 |
78 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
8782 |
0 |
0 |
T93 |
15318 |
21 |
0 |
0 |
T94 |
38112 |
327 |
0 |
0 |
T96 |
11422 |
14 |
0 |
0 |
T100 |
67738 |
666 |
0 |
0 |
T115 |
9888 |
39 |
0 |
0 |
T121 |
180389 |
452 |
0 |
0 |
T149 |
14479 |
21 |
0 |
0 |
T150 |
13525 |
71 |
0 |
0 |
T152 |
20642 |
22 |
0 |
0 |
T153 |
13402 |
22 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
9115 |
0 |
0 |
T93 |
15318 |
97 |
0 |
0 |
T94 |
38112 |
301 |
0 |
0 |
T96 |
11422 |
73 |
0 |
0 |
T115 |
9888 |
34 |
0 |
0 |
T121 |
180389 |
396 |
0 |
0 |
T149 |
14479 |
46 |
0 |
0 |
T150 |
13525 |
39 |
0 |
0 |
T151 |
7141 |
18 |
0 |
0 |
T152 |
20642 |
72 |
0 |
0 |
T153 |
13402 |
30 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
8269 |
0 |
0 |
T76 |
2287 |
1 |
0 |
0 |
T93 |
15318 |
65 |
0 |
0 |
T94 |
38112 |
177 |
0 |
0 |
T96 |
11422 |
43 |
0 |
0 |
T115 |
9888 |
53 |
0 |
0 |
T121 |
180389 |
423 |
0 |
0 |
T149 |
14479 |
42 |
0 |
0 |
T150 |
13525 |
26 |
0 |
0 |
T152 |
20642 |
61 |
0 |
0 |
T153 |
13402 |
41 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
8699 |
0 |
0 |
T93 |
15318 |
128 |
0 |
0 |
T94 |
38112 |
353 |
0 |
0 |
T96 |
11422 |
10 |
0 |
0 |
T115 |
9888 |
60 |
0 |
0 |
T121 |
180389 |
474 |
0 |
0 |
T149 |
14479 |
62 |
0 |
0 |
T150 |
13525 |
77 |
0 |
0 |
T151 |
7141 |
4 |
0 |
0 |
T152 |
20642 |
64 |
0 |
0 |
T153 |
13402 |
30 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
9227 |
0 |
0 |
T93 |
15318 |
17 |
0 |
0 |
T94 |
38112 |
417 |
0 |
0 |
T96 |
11422 |
63 |
0 |
0 |
T115 |
9888 |
53 |
0 |
0 |
T121 |
180389 |
413 |
0 |
0 |
T149 |
14479 |
38 |
0 |
0 |
T150 |
13525 |
47 |
0 |
0 |
T151 |
7141 |
5 |
0 |
0 |
T152 |
20642 |
98 |
0 |
0 |
T153 |
13402 |
22 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
8415 |
0 |
0 |
T93 |
15318 |
116 |
0 |
0 |
T94 |
38112 |
257 |
0 |
0 |
T96 |
11422 |
7 |
0 |
0 |
T115 |
9888 |
44 |
0 |
0 |
T121 |
180389 |
445 |
0 |
0 |
T149 |
14479 |
48 |
0 |
0 |
T150 |
13525 |
36 |
0 |
0 |
T151 |
7141 |
7 |
0 |
0 |
T152 |
20642 |
70 |
0 |
0 |
T153 |
13402 |
76 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
8356 |
0 |
0 |
T93 |
15318 |
132 |
0 |
0 |
T94 |
38112 |
324 |
0 |
0 |
T96 |
11422 |
21 |
0 |
0 |
T115 |
9888 |
52 |
0 |
0 |
T121 |
180389 |
461 |
0 |
0 |
T149 |
14479 |
27 |
0 |
0 |
T150 |
13525 |
34 |
0 |
0 |
T151 |
7141 |
24 |
0 |
0 |
T152 |
20642 |
39 |
0 |
0 |
T153 |
13402 |
38 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
8628 |
0 |
0 |
T93 |
15318 |
57 |
0 |
0 |
T94 |
38112 |
345 |
0 |
0 |
T96 |
11422 |
103 |
0 |
0 |
T115 |
9888 |
25 |
0 |
0 |
T121 |
180389 |
501 |
0 |
0 |
T149 |
14479 |
33 |
0 |
0 |
T150 |
13525 |
36 |
0 |
0 |
T151 |
7141 |
17 |
0 |
0 |
T152 |
20642 |
35 |
0 |
0 |
T153 |
13402 |
55 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
8478 |
0 |
0 |
T93 |
15318 |
72 |
0 |
0 |
T94 |
38112 |
268 |
0 |
0 |
T96 |
11422 |
21 |
0 |
0 |
T115 |
9888 |
32 |
0 |
0 |
T121 |
180389 |
453 |
0 |
0 |
T149 |
14479 |
55 |
0 |
0 |
T150 |
13525 |
49 |
0 |
0 |
T151 |
7141 |
17 |
0 |
0 |
T152 |
20642 |
98 |
0 |
0 |
T153 |
13402 |
93 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
8650 |
0 |
0 |
T93 |
15318 |
63 |
0 |
0 |
T94 |
38112 |
192 |
0 |
0 |
T96 |
11422 |
42 |
0 |
0 |
T115 |
9888 |
40 |
0 |
0 |
T121 |
180389 |
436 |
0 |
0 |
T149 |
14479 |
38 |
0 |
0 |
T150 |
13525 |
17 |
0 |
0 |
T151 |
7141 |
11 |
0 |
0 |
T152 |
20642 |
60 |
0 |
0 |
T153 |
13402 |
60 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
8655 |
0 |
0 |
T93 |
15318 |
141 |
0 |
0 |
T94 |
38112 |
313 |
0 |
0 |
T96 |
11422 |
46 |
0 |
0 |
T115 |
9888 |
40 |
0 |
0 |
T121 |
180389 |
491 |
0 |
0 |
T149 |
14479 |
33 |
0 |
0 |
T150 |
13525 |
36 |
0 |
0 |
T151 |
7141 |
20 |
0 |
0 |
T152 |
20642 |
57 |
0 |
0 |
T153 |
13402 |
88 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
8547 |
0 |
0 |
T93 |
15318 |
18 |
0 |
0 |
T94 |
38112 |
336 |
0 |
0 |
T96 |
11422 |
55 |
0 |
0 |
T115 |
9888 |
3 |
0 |
0 |
T121 |
180389 |
405 |
0 |
0 |
T149 |
14479 |
49 |
0 |
0 |
T150 |
13525 |
41 |
0 |
0 |
T151 |
7141 |
3 |
0 |
0 |
T152 |
20642 |
57 |
0 |
0 |
T153 |
13402 |
9 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
8560 |
0 |
0 |
T76 |
2287 |
5 |
0 |
0 |
T93 |
15318 |
171 |
0 |
0 |
T94 |
38112 |
262 |
0 |
0 |
T96 |
11422 |
126 |
0 |
0 |
T121 |
180389 |
467 |
0 |
0 |
T149 |
14479 |
21 |
0 |
0 |
T150 |
13525 |
7 |
0 |
0 |
T151 |
7141 |
14 |
0 |
0 |
T152 |
20642 |
45 |
0 |
0 |
T153 |
13402 |
71 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
9030 |
0 |
0 |
T93 |
15318 |
167 |
0 |
0 |
T94 |
38112 |
235 |
0 |
0 |
T96 |
11422 |
66 |
0 |
0 |
T115 |
9888 |
51 |
0 |
0 |
T121 |
180389 |
465 |
0 |
0 |
T149 |
14479 |
45 |
0 |
0 |
T150 |
13525 |
11 |
0 |
0 |
T151 |
7141 |
38 |
0 |
0 |
T152 |
20642 |
52 |
0 |
0 |
T153 |
13402 |
65 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
8867 |
0 |
0 |
T93 |
15318 |
103 |
0 |
0 |
T94 |
38112 |
340 |
0 |
0 |
T96 |
11422 |
69 |
0 |
0 |
T115 |
9888 |
10 |
0 |
0 |
T121 |
180389 |
476 |
0 |
0 |
T149 |
14479 |
37 |
0 |
0 |
T150 |
13525 |
67 |
0 |
0 |
T151 |
7141 |
12 |
0 |
0 |
T152 |
20642 |
39 |
0 |
0 |
T153 |
13402 |
44 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
8281 |
0 |
0 |
T93 |
15318 |
23 |
0 |
0 |
T94 |
38112 |
188 |
0 |
0 |
T96 |
11422 |
104 |
0 |
0 |
T115 |
9888 |
29 |
0 |
0 |
T121 |
180389 |
390 |
0 |
0 |
T149 |
14479 |
18 |
0 |
0 |
T150 |
13525 |
50 |
0 |
0 |
T151 |
7141 |
5 |
0 |
0 |
T152 |
20642 |
22 |
0 |
0 |
T153 |
13402 |
41 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
8379 |
0 |
0 |
T93 |
15318 |
58 |
0 |
0 |
T94 |
38112 |
318 |
0 |
0 |
T96 |
11422 |
100 |
0 |
0 |
T115 |
9888 |
7 |
0 |
0 |
T121 |
180389 |
459 |
0 |
0 |
T149 |
14479 |
19 |
0 |
0 |
T150 |
13525 |
54 |
0 |
0 |
T151 |
7141 |
29 |
0 |
0 |
T152 |
20642 |
29 |
0 |
0 |
T153 |
13402 |
66 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
8056 |
0 |
0 |
T93 |
15318 |
28 |
0 |
0 |
T94 |
38112 |
395 |
0 |
0 |
T96 |
11422 |
70 |
0 |
0 |
T115 |
9888 |
76 |
0 |
0 |
T121 |
180389 |
385 |
0 |
0 |
T149 |
14479 |
35 |
0 |
0 |
T150 |
13525 |
15 |
0 |
0 |
T151 |
7141 |
12 |
0 |
0 |
T152 |
20642 |
60 |
0 |
0 |
T153 |
13402 |
12 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
8157 |
0 |
0 |
T93 |
15318 |
117 |
0 |
0 |
T94 |
38112 |
239 |
0 |
0 |
T96 |
11422 |
36 |
0 |
0 |
T115 |
9888 |
48 |
0 |
0 |
T121 |
180389 |
458 |
0 |
0 |
T149 |
14479 |
88 |
0 |
0 |
T150 |
13525 |
52 |
0 |
0 |
T151 |
7141 |
7 |
0 |
0 |
T152 |
20642 |
25 |
0 |
0 |
T153 |
13402 |
43 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
8694 |
0 |
0 |
T93 |
15318 |
62 |
0 |
0 |
T94 |
38112 |
215 |
0 |
0 |
T96 |
11422 |
77 |
0 |
0 |
T115 |
9888 |
24 |
0 |
0 |
T121 |
180389 |
478 |
0 |
0 |
T149 |
14479 |
48 |
0 |
0 |
T150 |
13525 |
7 |
0 |
0 |
T151 |
7141 |
9 |
0 |
0 |
T152 |
20642 |
50 |
0 |
0 |
T153 |
13402 |
42 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
8274 |
0 |
0 |
T93 |
15318 |
16 |
0 |
0 |
T94 |
38112 |
174 |
0 |
0 |
T96 |
11422 |
78 |
0 |
0 |
T115 |
9888 |
6 |
0 |
0 |
T121 |
180389 |
377 |
0 |
0 |
T149 |
14479 |
57 |
0 |
0 |
T150 |
13525 |
64 |
0 |
0 |
T151 |
7141 |
7 |
0 |
0 |
T152 |
20642 |
45 |
0 |
0 |
T153 |
13402 |
26 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
3779 |
0 |
0 |
T93 |
15318 |
20 |
0 |
0 |
T94 |
38112 |
61 |
0 |
0 |
T96 |
11422 |
23 |
0 |
0 |
T115 |
9888 |
3 |
0 |
0 |
T121 |
180389 |
412 |
0 |
0 |
T149 |
14479 |
34 |
0 |
0 |
T150 |
13525 |
78 |
0 |
0 |
T151 |
7141 |
16 |
0 |
0 |
T152 |
20642 |
50 |
0 |
0 |
T153 |
13402 |
48 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
3903 |
0 |
0 |
T93 |
15318 |
21 |
0 |
0 |
T94 |
38112 |
62 |
0 |
0 |
T96 |
11422 |
15 |
0 |
0 |
T115 |
9888 |
14 |
0 |
0 |
T121 |
180389 |
443 |
0 |
0 |
T149 |
14479 |
32 |
0 |
0 |
T150 |
13525 |
9 |
0 |
0 |
T151 |
7141 |
2 |
0 |
0 |
T152 |
20642 |
80 |
0 |
0 |
T153 |
13402 |
77 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
3801 |
0 |
0 |
T93 |
15318 |
30 |
0 |
0 |
T94 |
38112 |
81 |
0 |
0 |
T96 |
11422 |
37 |
0 |
0 |
T115 |
9888 |
15 |
0 |
0 |
T121 |
180389 |
369 |
0 |
0 |
T149 |
14479 |
13 |
0 |
0 |
T150 |
13525 |
44 |
0 |
0 |
T151 |
7141 |
5 |
0 |
0 |
T152 |
20642 |
69 |
0 |
0 |
T153 |
13402 |
41 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
4070 |
0 |
0 |
T76 |
2287 |
8 |
0 |
0 |
T93 |
15318 |
40 |
0 |
0 |
T94 |
38112 |
42 |
0 |
0 |
T96 |
11422 |
22 |
0 |
0 |
T115 |
9888 |
11 |
0 |
0 |
T121 |
180389 |
482 |
0 |
0 |
T149 |
14479 |
47 |
0 |
0 |
T150 |
13525 |
32 |
0 |
0 |
T152 |
20642 |
60 |
0 |
0 |
T153 |
13402 |
35 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
4658 |
0 |
0 |
T93 |
15318 |
33 |
0 |
0 |
T94 |
38112 |
96 |
0 |
0 |
T96 |
11422 |
23 |
0 |
0 |
T115 |
9888 |
19 |
0 |
0 |
T121 |
180389 |
414 |
0 |
0 |
T149 |
14479 |
43 |
0 |
0 |
T150 |
13525 |
37 |
0 |
0 |
T151 |
7141 |
34 |
0 |
0 |
T152 |
20642 |
82 |
0 |
0 |
T153 |
13402 |
23 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
8056 |
0 |
0 |
T23 |
0 |
37 |
0 |
0 |
T36 |
346807 |
0 |
0 |
0 |
T62 |
284714 |
28 |
0 |
0 |
T63 |
3501 |
0 |
0 |
0 |
T145 |
344642 |
0 |
0 |
0 |
T154 |
0 |
12 |
0 |
0 |
T155 |
0 |
52 |
0 |
0 |
T156 |
0 |
43 |
0 |
0 |
T157 |
0 |
78 |
0 |
0 |
T158 |
0 |
45 |
0 |
0 |
T159 |
0 |
24 |
0 |
0 |
T160 |
0 |
46 |
0 |
0 |
T161 |
0 |
54 |
0 |
0 |
T162 |
929 |
0 |
0 |
0 |
T163 |
8873 |
0 |
0 |
0 |
T164 |
1083 |
0 |
0 |
0 |
T165 |
984185 |
0 |
0 |
0 |
T166 |
1294 |
0 |
0 |
0 |
T167 |
129903 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
4022 |
0 |
0 |
T93 |
15318 |
19 |
0 |
0 |
T94 |
38112 |
58 |
0 |
0 |
T96 |
11422 |
13 |
0 |
0 |
T115 |
9888 |
3 |
0 |
0 |
T121 |
180389 |
459 |
0 |
0 |
T149 |
14479 |
37 |
0 |
0 |
T150 |
13525 |
54 |
0 |
0 |
T151 |
7141 |
18 |
0 |
0 |
T152 |
20642 |
119 |
0 |
0 |
T153 |
13402 |
34 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
3954 |
0 |
0 |
T93 |
15318 |
16 |
0 |
0 |
T94 |
38112 |
53 |
0 |
0 |
T96 |
11422 |
15 |
0 |
0 |
T115 |
9888 |
4 |
0 |
0 |
T121 |
180389 |
461 |
0 |
0 |
T149 |
14479 |
83 |
0 |
0 |
T150 |
13525 |
83 |
0 |
0 |
T151 |
7141 |
11 |
0 |
0 |
T152 |
20642 |
67 |
0 |
0 |
T153 |
13402 |
102 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
3447 |
0 |
0 |
T93 |
15318 |
31 |
0 |
0 |
T94 |
38112 |
25 |
0 |
0 |
T96 |
11422 |
6 |
0 |
0 |
T115 |
9888 |
9 |
0 |
0 |
T121 |
180389 |
442 |
0 |
0 |
T149 |
14479 |
30 |
0 |
0 |
T150 |
13525 |
90 |
0 |
0 |
T151 |
7141 |
6 |
0 |
0 |
T152 |
20642 |
91 |
0 |
0 |
T153 |
13402 |
40 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
3588 |
0 |
0 |
T93 |
15318 |
17 |
0 |
0 |
T94 |
38112 |
33 |
0 |
0 |
T96 |
11422 |
24 |
0 |
0 |
T115 |
9888 |
9 |
0 |
0 |
T121 |
180389 |
463 |
0 |
0 |
T149 |
14479 |
55 |
0 |
0 |
T150 |
13525 |
55 |
0 |
0 |
T151 |
7141 |
19 |
0 |
0 |
T152 |
20642 |
119 |
0 |
0 |
T153 |
13402 |
34 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
3450 |
0 |
0 |
T93 |
15318 |
23 |
0 |
0 |
T94 |
38112 |
38 |
0 |
0 |
T96 |
11422 |
2 |
0 |
0 |
T115 |
9888 |
16 |
0 |
0 |
T121 |
180389 |
481 |
0 |
0 |
T149 |
14479 |
63 |
0 |
0 |
T150 |
13525 |
55 |
0 |
0 |
T151 |
7141 |
16 |
0 |
0 |
T152 |
20642 |
30 |
0 |
0 |
T153 |
13402 |
12 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
3588 |
0 |
0 |
T76 |
2287 |
9 |
0 |
0 |
T93 |
15318 |
29 |
0 |
0 |
T94 |
38112 |
19 |
0 |
0 |
T96 |
11422 |
18 |
0 |
0 |
T115 |
9888 |
8 |
0 |
0 |
T121 |
180389 |
475 |
0 |
0 |
T149 |
14479 |
75 |
0 |
0 |
T150 |
13525 |
26 |
0 |
0 |
T152 |
20642 |
59 |
0 |
0 |
T153 |
13402 |
40 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
4729 |
0 |
0 |
T93 |
15318 |
24 |
0 |
0 |
T94 |
38112 |
65 |
0 |
0 |
T96 |
11422 |
22 |
0 |
0 |
T115 |
9888 |
10 |
0 |
0 |
T121 |
180389 |
523 |
0 |
0 |
T149 |
14479 |
28 |
0 |
0 |
T150 |
13525 |
26 |
0 |
0 |
T151 |
7141 |
14 |
0 |
0 |
T152 |
20642 |
58 |
0 |
0 |
T153 |
13402 |
32 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
3358 |
0 |
0 |
T76 |
2287 |
2 |
0 |
0 |
T93 |
15318 |
17 |
0 |
0 |
T94 |
38112 |
47 |
0 |
0 |
T96 |
11422 |
16 |
0 |
0 |
T121 |
180389 |
444 |
0 |
0 |
T149 |
14479 |
51 |
0 |
0 |
T150 |
13525 |
4 |
0 |
0 |
T151 |
7141 |
33 |
0 |
0 |
T152 |
20642 |
87 |
0 |
0 |
T153 |
13402 |
46 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
5276 |
0 |
0 |
T93 |
15318 |
44 |
0 |
0 |
T94 |
38112 |
107 |
0 |
0 |
T96 |
11422 |
36 |
0 |
0 |
T115 |
9888 |
12 |
0 |
0 |
T121 |
180389 |
445 |
0 |
0 |
T149 |
14479 |
61 |
0 |
0 |
T150 |
13525 |
24 |
0 |
0 |
T151 |
7141 |
9 |
0 |
0 |
T152 |
20642 |
107 |
0 |
0 |
T153 |
13402 |
103 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
3862 |
0 |
0 |
T93 |
15318 |
20 |
0 |
0 |
T94 |
38112 |
59 |
0 |
0 |
T96 |
11422 |
19 |
0 |
0 |
T115 |
9888 |
22 |
0 |
0 |
T121 |
180389 |
451 |
0 |
0 |
T149 |
14479 |
43 |
0 |
0 |
T150 |
13525 |
44 |
0 |
0 |
T151 |
7141 |
6 |
0 |
0 |
T152 |
20642 |
45 |
0 |
0 |
T153 |
13402 |
27 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
3351 |
0 |
0 |
T76 |
2287 |
3 |
0 |
0 |
T93 |
15318 |
14 |
0 |
0 |
T94 |
38112 |
41 |
0 |
0 |
T96 |
11422 |
28 |
0 |
0 |
T121 |
180389 |
455 |
0 |
0 |
T149 |
14479 |
29 |
0 |
0 |
T150 |
13525 |
31 |
0 |
0 |
T151 |
7141 |
12 |
0 |
0 |
T152 |
20642 |
29 |
0 |
0 |
T153 |
13402 |
41 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
3342 |
0 |
0 |
T93 |
15318 |
32 |
0 |
0 |
T94 |
38112 |
34 |
0 |
0 |
T96 |
11422 |
21 |
0 |
0 |
T115 |
9888 |
3 |
0 |
0 |
T121 |
180389 |
398 |
0 |
0 |
T149 |
14479 |
53 |
0 |
0 |
T150 |
13525 |
40 |
0 |
0 |
T151 |
7141 |
6 |
0 |
0 |
T152 |
20642 |
58 |
0 |
0 |
T153 |
13402 |
54 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
3468 |
0 |
0 |
T93 |
15318 |
23 |
0 |
0 |
T94 |
38112 |
26 |
0 |
0 |
T96 |
11422 |
31 |
0 |
0 |
T115 |
9888 |
8 |
0 |
0 |
T121 |
180389 |
442 |
0 |
0 |
T149 |
14479 |
61 |
0 |
0 |
T150 |
13525 |
19 |
0 |
0 |
T151 |
7141 |
33 |
0 |
0 |
T152 |
20642 |
52 |
0 |
0 |
T153 |
13402 |
24 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
3521 |
0 |
0 |
T93 |
15318 |
17 |
0 |
0 |
T94 |
38112 |
16 |
0 |
0 |
T96 |
11422 |
13 |
0 |
0 |
T115 |
9888 |
9 |
0 |
0 |
T121 |
180389 |
429 |
0 |
0 |
T149 |
14479 |
74 |
0 |
0 |
T150 |
13525 |
87 |
0 |
0 |
T151 |
7141 |
14 |
0 |
0 |
T152 |
20642 |
32 |
0 |
0 |
T153 |
13402 |
40 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
3431 |
0 |
0 |
T93 |
15318 |
21 |
0 |
0 |
T94 |
38112 |
40 |
0 |
0 |
T96 |
11422 |
16 |
0 |
0 |
T115 |
9888 |
13 |
0 |
0 |
T121 |
180389 |
460 |
0 |
0 |
T149 |
14479 |
87 |
0 |
0 |
T150 |
13525 |
48 |
0 |
0 |
T151 |
7141 |
25 |
0 |
0 |
T152 |
20642 |
119 |
0 |
0 |
T153 |
13402 |
17 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1101050734 |
3426 |
0 |
0 |
T93 |
15318 |
21 |
0 |
0 |
T94 |
38112 |
34 |
0 |
0 |
T96 |
11422 |
17 |
0 |
0 |
T115 |
9888 |
4 |
0 |
0 |
T121 |
180389 |
487 |
0 |
0 |
T149 |
14479 |
26 |
0 |
0 |
T150 |
13525 |
46 |
0 |
0 |
T151 |
7141 |
2 |
0 |
0 |
T152 |
20642 |
85 |
0 |
0 |
T153 |
13402 |
35 |
0 |
0 |