| T1816 |
/workspace/coverage/default/48.spi_device_tpm_rw.1038707018 |
|
|
Mar 12 01:13:18 PM PDT 24 |
Mar 12 01:13:21 PM PDT 24 |
41665090 ps |
| T1817 |
/workspace/coverage/default/37.spi_device_cfg_cmd.37219703 |
|
|
Mar 12 03:09:57 PM PDT 24 |
Mar 12 03:10:05 PM PDT 24 |
9295730676 ps |
| T1818 |
/workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1612619826 |
|
|
Mar 12 03:05:01 PM PDT 24 |
Mar 12 03:05:11 PM PDT 24 |
23367826650 ps |
| T1819 |
/workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3004381272 |
|
|
Mar 12 01:12:09 PM PDT 24 |
Mar 12 01:12:22 PM PDT 24 |
4497826079 ps |
| T1820 |
/workspace/coverage/default/24.spi_device_flash_all.1514659325 |
|
|
Mar 12 03:08:27 PM PDT 24 |
Mar 12 03:11:41 PM PDT 24 |
153544405120 ps |
| T1821 |
/workspace/coverage/default/26.spi_device_flash_and_tpm.2252994338 |
|
|
Mar 12 03:08:37 PM PDT 24 |
Mar 12 03:10:32 PM PDT 24 |
7024778782 ps |
| T1822 |
/workspace/coverage/default/41.spi_device_cfg_cmd.3848306605 |
|
|
Mar 12 03:10:10 PM PDT 24 |
Mar 12 03:10:19 PM PDT 24 |
1406175227 ps |
| T1823 |
/workspace/coverage/default/14.spi_device_csb_read.3714456513 |
|
|
Mar 12 01:11:19 PM PDT 24 |
Mar 12 01:11:20 PM PDT 24 |
104303094 ps |
| T1824 |
/workspace/coverage/default/0.spi_device_tpm_sts_read.1140717129 |
|
|
Mar 12 03:04:51 PM PDT 24 |
Mar 12 03:04:52 PM PDT 24 |
111162606 ps |
| T1825 |
/workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.520974079 |
|
|
Mar 12 03:05:50 PM PDT 24 |
Mar 12 03:07:32 PM PDT 24 |
6979979782 ps |
| T1826 |
/workspace/coverage/default/35.spi_device_tpm_all.1596766947 |
|
|
Mar 12 03:09:44 PM PDT 24 |
Mar 12 03:10:18 PM PDT 24 |
6772597559 ps |
| T1827 |
/workspace/coverage/default/30.spi_device_pass_cmd_filtering.3916992849 |
|
|
Mar 12 03:09:10 PM PDT 24 |
Mar 12 03:09:12 PM PDT 24 |
99545360 ps |
| T1828 |
/workspace/coverage/default/37.spi_device_alert_test.337268133 |
|
|
Mar 12 03:09:59 PM PDT 24 |
Mar 12 03:09:59 PM PDT 24 |
16047856 ps |
| T1829 |
/workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2202118154 |
|
|
Mar 12 03:08:17 PM PDT 24 |
Mar 12 03:14:02 PM PDT 24 |
50057454021 ps |
| T1830 |
/workspace/coverage/default/12.spi_device_tpm_read_hw_reg.661247500 |
|
|
Mar 12 01:11:19 PM PDT 24 |
Mar 12 01:11:26 PM PDT 24 |
2707940626 ps |
| T1831 |
/workspace/coverage/default/19.spi_device_tpm_all.2894181922 |
|
|
Mar 12 01:11:32 PM PDT 24 |
Mar 12 01:11:58 PM PDT 24 |
4564558016 ps |
| T1832 |
/workspace/coverage/default/14.spi_device_upload.2575718414 |
|
|
Mar 12 01:11:16 PM PDT 24 |
Mar 12 01:11:19 PM PDT 24 |
607290159 ps |
| T1833 |
/workspace/coverage/default/27.spi_device_intercept.1179939121 |
|
|
Mar 12 01:11:51 PM PDT 24 |
Mar 12 01:11:56 PM PDT 24 |
5759201521 ps |
| T1834 |
/workspace/coverage/default/10.spi_device_cfg_cmd.2574329740 |
|
|
Mar 12 01:11:05 PM PDT 24 |
Mar 12 01:11:10 PM PDT 24 |
279746316 ps |
| T1835 |
/workspace/coverage/default/44.spi_device_read_buffer_direct.671506525 |
|
|
Mar 12 01:12:47 PM PDT 24 |
Mar 12 01:12:54 PM PDT 24 |
4398048320 ps |
| T1836 |
/workspace/coverage/default/36.spi_device_upload.948712345 |
|
|
Mar 12 03:09:55 PM PDT 24 |
Mar 12 03:10:04 PM PDT 24 |
1789965600 ps |
| T1837 |
/workspace/coverage/default/13.spi_device_tpm_all.1446135223 |
|
|
Mar 12 01:11:07 PM PDT 24 |
Mar 12 01:11:25 PM PDT 24 |
4844132644 ps |
| T1838 |
/workspace/coverage/default/42.spi_device_mailbox.3995489699 |
|
|
Mar 12 03:10:14 PM PDT 24 |
Mar 12 03:10:34 PM PDT 24 |
13429883048 ps |
| T1839 |
/workspace/coverage/default/2.spi_device_intercept.3461636873 |
|
|
Mar 12 03:05:30 PM PDT 24 |
Mar 12 03:05:38 PM PDT 24 |
2536194057 ps |
| T1840 |
/workspace/coverage/default/4.spi_device_flash_all.83204140 |
|
|
Mar 12 03:05:38 PM PDT 24 |
Mar 12 03:06:01 PM PDT 24 |
3627973875 ps |
| T1841 |
/workspace/coverage/default/19.spi_device_upload.352650745 |
|
|
Mar 12 03:07:48 PM PDT 24 |
Mar 12 03:07:54 PM PDT 24 |
463546039 ps |
| T1842 |
/workspace/coverage/default/27.spi_device_read_buffer_direct.1119014830 |
|
|
Mar 12 01:12:01 PM PDT 24 |
Mar 12 01:12:06 PM PDT 24 |
349773840 ps |
| T1843 |
/workspace/coverage/default/42.spi_device_tpm_rw.1764178770 |
|
|
Mar 12 03:10:12 PM PDT 24 |
Mar 12 03:10:22 PM PDT 24 |
691067593 ps |
| T1844 |
/workspace/coverage/default/23.spi_device_flash_all.2588770382 |
|
|
Mar 12 01:11:47 PM PDT 24 |
Mar 12 01:14:44 PM PDT 24 |
27935688728 ps |
| T1845 |
/workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.560089018 |
|
|
Mar 12 03:06:18 PM PDT 24 |
Mar 12 03:11:57 PM PDT 24 |
267245588045 ps |
| T1846 |
/workspace/coverage/default/29.spi_device_flash_mode.248571201 |
|
|
Mar 12 03:08:53 PM PDT 24 |
Mar 12 03:09:19 PM PDT 24 |
4141423772 ps |
| T1847 |
/workspace/coverage/default/36.spi_device_tpm_rw.3945131829 |
|
|
Mar 12 01:12:27 PM PDT 24 |
Mar 12 01:12:28 PM PDT 24 |
46557235 ps |
| T1848 |
/workspace/coverage/default/12.spi_device_ram_cfg.2722016046 |
|
|
Mar 12 01:11:08 PM PDT 24 |
Mar 12 01:11:09 PM PDT 24 |
29820951 ps |
| T1849 |
/workspace/coverage/default/49.spi_device_tpm_sts_read.627747606 |
|
|
Mar 12 03:11:02 PM PDT 24 |
Mar 12 03:11:03 PM PDT 24 |
95358345 ps |
| T1850 |
/workspace/coverage/default/33.spi_device_stress_all.4084420627 |
|
|
Mar 12 03:09:19 PM PDT 24 |
Mar 12 03:15:19 PM PDT 24 |
187680679696 ps |
| T1851 |
/workspace/coverage/default/4.spi_device_mailbox.2166233637 |
|
|
Mar 12 03:05:37 PM PDT 24 |
Mar 12 03:06:12 PM PDT 24 |
12659027507 ps |
| T1852 |
/workspace/coverage/default/2.spi_device_csb_read.2439765020 |
|
|
Mar 12 03:05:18 PM PDT 24 |
Mar 12 03:05:21 PM PDT 24 |
24168027 ps |
| T1853 |
/workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2356091775 |
|
|
Mar 12 01:13:20 PM PDT 24 |
Mar 12 01:13:27 PM PDT 24 |
10935637536 ps |
| T1854 |
/workspace/coverage/default/42.spi_device_read_buffer_direct.1650253895 |
|
|
Mar 12 01:12:43 PM PDT 24 |
Mar 12 01:12:48 PM PDT 24 |
1948610835 ps |
| T1855 |
/workspace/coverage/default/0.spi_device_stress_all.3404721283 |
|
|
Mar 12 01:10:22 PM PDT 24 |
Mar 12 01:19:32 PM PDT 24 |
61247367744 ps |
| T1856 |
/workspace/coverage/default/8.spi_device_alert_test.1162581996 |
|
|
Mar 12 03:06:18 PM PDT 24 |
Mar 12 03:06:19 PM PDT 24 |
142698799 ps |
| T1857 |
/workspace/coverage/default/45.spi_device_tpm_all.1567733780 |
|
|
Mar 12 01:12:48 PM PDT 24 |
Mar 12 01:13:02 PM PDT 24 |
2329827997 ps |
| T1858 |
/workspace/coverage/default/3.spi_device_read_buffer_direct.1698762281 |
|
|
Mar 12 01:10:30 PM PDT 24 |
Mar 12 01:10:36 PM PDT 24 |
2094390668 ps |
| T1859 |
/workspace/coverage/default/24.spi_device_intercept.4188277525 |
|
|
Mar 12 01:11:44 PM PDT 24 |
Mar 12 01:11:47 PM PDT 24 |
166304811 ps |
| T1860 |
/workspace/coverage/default/11.spi_device_mailbox.3197198527 |
|
|
Mar 12 03:06:51 PM PDT 24 |
Mar 12 03:06:54 PM PDT 24 |
172298454 ps |
| T1861 |
/workspace/coverage/default/20.spi_device_alert_test.2348352400 |
|
|
Mar 12 03:08:04 PM PDT 24 |
Mar 12 03:08:05 PM PDT 24 |
21733929 ps |
| T1862 |
/workspace/coverage/default/33.spi_device_csb_read.2015203631 |
|
|
Mar 12 01:12:14 PM PDT 24 |
Mar 12 01:12:14 PM PDT 24 |
38880493 ps |
| T1863 |
/workspace/coverage/default/11.spi_device_flash_mode.885955283 |
|
|
Mar 12 03:06:49 PM PDT 24 |
Mar 12 03:07:01 PM PDT 24 |
3307553212 ps |
| T1864 |
/workspace/coverage/default/41.spi_device_tpm_rw.1367850444 |
|
|
Mar 12 01:12:47 PM PDT 24 |
Mar 12 01:12:49 PM PDT 24 |
88155682 ps |
| T1865 |
/workspace/coverage/default/33.spi_device_pass_cmd_filtering.3785459427 |
|
|
Mar 12 01:12:14 PM PDT 24 |
Mar 12 01:12:29 PM PDT 24 |
7757475185 ps |
| T1866 |
/workspace/coverage/default/1.spi_device_csb_read.836987594 |
|
|
Mar 12 03:05:05 PM PDT 24 |
Mar 12 03:05:07 PM PDT 24 |
55729543 ps |
| T1867 |
/workspace/coverage/default/6.spi_device_mem_parity.2978305767 |
|
|
Mar 12 01:10:38 PM PDT 24 |
Mar 12 01:10:39 PM PDT 24 |
25473293 ps |
| T1868 |
/workspace/coverage/default/35.spi_device_tpm_sts_read.525359683 |
|
|
Mar 12 01:12:24 PM PDT 24 |
Mar 12 01:12:25 PM PDT 24 |
155066367 ps |
| T1869 |
/workspace/coverage/default/44.spi_device_cfg_cmd.1772417903 |
|
|
Mar 12 03:10:34 PM PDT 24 |
Mar 12 03:10:40 PM PDT 24 |
1312837345 ps |
| T1870 |
/workspace/coverage/default/42.spi_device_alert_test.841290111 |
|
|
Mar 12 03:10:25 PM PDT 24 |
Mar 12 03:10:26 PM PDT 24 |
77023011 ps |
| T1871 |
/workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.4030308525 |
|
|
Mar 12 01:10:46 PM PDT 24 |
Mar 12 01:18:58 PM PDT 24 |
61263800833 ps |
| T1872 |
/workspace/coverage/default/47.spi_device_flash_all.3164171298 |
|
|
Mar 12 01:13:03 PM PDT 24 |
Mar 12 01:14:26 PM PDT 24 |
8293421121 ps |
| T1873 |
/workspace/coverage/default/3.spi_device_stress_all.164829958 |
|
|
Mar 12 01:10:28 PM PDT 24 |
Mar 12 01:11:48 PM PDT 24 |
25409406606 ps |
| T1874 |
/workspace/coverage/default/14.spi_device_flash_all.1746120100 |
|
|
Mar 12 01:11:16 PM PDT 24 |
Mar 12 01:13:32 PM PDT 24 |
68814182299 ps |
| T1875 |
/workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1478660540 |
|
|
Mar 12 01:12:36 PM PDT 24 |
Mar 12 01:12:38 PM PDT 24 |
586969857 ps |
| T1876 |
/workspace/coverage/default/2.spi_device_mem_parity.32312035 |
|
|
Mar 12 01:10:16 PM PDT 24 |
Mar 12 01:10:17 PM PDT 24 |
91522117 ps |
| T1877 |
/workspace/coverage/default/21.spi_device_cfg_cmd.3552375353 |
|
|
Mar 12 03:08:01 PM PDT 24 |
Mar 12 03:08:05 PM PDT 24 |
150188271 ps |
| T1878 |
/workspace/coverage/default/28.spi_device_upload.3164320834 |
|
|
Mar 12 01:12:07 PM PDT 24 |
Mar 12 01:12:13 PM PDT 24 |
545463856 ps |
| T1879 |
/workspace/coverage/default/21.spi_device_pass_addr_payload_swap.375115496 |
|
|
Mar 12 01:11:45 PM PDT 24 |
Mar 12 01:11:52 PM PDT 24 |
1932485012 ps |
| T1880 |
/workspace/coverage/default/7.spi_device_tpm_rw.924360716 |
|
|
Mar 12 03:06:08 PM PDT 24 |
Mar 12 03:06:15 PM PDT 24 |
228803951 ps |
| T1881 |
/workspace/coverage/default/28.spi_device_alert_test.1289252394 |
|
|
Mar 12 03:08:55 PM PDT 24 |
Mar 12 03:08:58 PM PDT 24 |
16380358 ps |
| T1882 |
/workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3606900704 |
|
|
Mar 12 03:08:52 PM PDT 24 |
Mar 12 03:08:58 PM PDT 24 |
294397704 ps |
| T1883 |
/workspace/coverage/default/19.spi_device_read_buffer_direct.2352203259 |
|
|
Mar 12 03:07:49 PM PDT 24 |
Mar 12 03:07:54 PM PDT 24 |
904008677 ps |
| T1884 |
/workspace/coverage/default/41.spi_device_flash_mode.746098084 |
|
|
Mar 12 03:10:13 PM PDT 24 |
Mar 12 03:10:29 PM PDT 24 |
1051764710 ps |
| T1885 |
/workspace/coverage/default/46.spi_device_intercept.1402086158 |
|
|
Mar 12 01:13:06 PM PDT 24 |
Mar 12 01:13:08 PM PDT 24 |
37452755 ps |
| T1886 |
/workspace/coverage/default/40.spi_device_tpm_sts_read.555599828 |
|
|
Mar 12 03:10:07 PM PDT 24 |
Mar 12 03:10:09 PM PDT 24 |
275916864 ps |
| T1887 |
/workspace/coverage/default/15.spi_device_upload.1854125665 |
|
|
Mar 12 03:07:14 PM PDT 24 |
Mar 12 03:07:20 PM PDT 24 |
6188235972 ps |
| T1888 |
/workspace/coverage/default/6.spi_device_flash_and_tpm.4239652965 |
|
|
Mar 12 03:06:09 PM PDT 24 |
Mar 12 03:06:56 PM PDT 24 |
3708260111 ps |
| T1889 |
/workspace/coverage/default/42.spi_device_tpm_all.1285868643 |
|
|
Mar 12 03:10:12 PM PDT 24 |
Mar 12 03:10:33 PM PDT 24 |
3872891451 ps |
| T1890 |
/workspace/coverage/default/22.spi_device_pass_cmd_filtering.2392434868 |
|
|
Mar 12 01:11:41 PM PDT 24 |
Mar 12 01:11:51 PM PDT 24 |
30307360916 ps |
| T1891 |
/workspace/coverage/default/12.spi_device_mailbox.3782591850 |
|
|
Mar 12 03:06:55 PM PDT 24 |
Mar 12 03:07:01 PM PDT 24 |
340324603 ps |
| T1892 |
/workspace/coverage/default/41.spi_device_read_buffer_direct.3330689572 |
|
|
Mar 12 03:10:14 PM PDT 24 |
Mar 12 03:10:18 PM PDT 24 |
1282926328 ps |
| T1893 |
/workspace/coverage/default/13.spi_device_tpm_sts_read.3468959639 |
|
|
Mar 12 01:11:12 PM PDT 24 |
Mar 12 01:11:13 PM PDT 24 |
425205006 ps |
| T1894 |
/workspace/coverage/default/0.spi_device_ram_cfg.139760073 |
|
|
Mar 12 01:10:04 PM PDT 24 |
Mar 12 01:10:05 PM PDT 24 |
17313289 ps |
| T1895 |
/workspace/coverage/default/25.spi_device_alert_test.3670218254 |
|
|
Mar 12 01:12:04 PM PDT 24 |
Mar 12 01:12:05 PM PDT 24 |
29656141 ps |
| T1896 |
/workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2852563149 |
|
|
Mar 12 03:07:37 PM PDT 24 |
Mar 12 03:08:15 PM PDT 24 |
3636642889 ps |
| T1897 |
/workspace/coverage/default/43.spi_device_csb_read.1120555497 |
|
|
Mar 12 03:10:22 PM PDT 24 |
Mar 12 03:10:24 PM PDT 24 |
14889177 ps |
| T1898 |
/workspace/coverage/default/18.spi_device_pass_addr_payload_swap.903077493 |
|
|
Mar 12 01:11:33 PM PDT 24 |
Mar 12 01:11:43 PM PDT 24 |
2999655578 ps |
| T1899 |
/workspace/coverage/default/41.spi_device_cfg_cmd.594579020 |
|
|
Mar 12 01:12:34 PM PDT 24 |
Mar 12 01:12:37 PM PDT 24 |
966333587 ps |
| T1900 |
/workspace/coverage/default/36.spi_device_flash_all.2369973876 |
|
|
Mar 12 01:12:30 PM PDT 24 |
Mar 12 01:13:27 PM PDT 24 |
3556130895 ps |
| T1901 |
/workspace/coverage/default/12.spi_device_flash_all.3916207341 |
|
|
Mar 12 03:06:56 PM PDT 24 |
Mar 12 03:07:34 PM PDT 24 |
4227560955 ps |
| T1902 |
/workspace/coverage/default/13.spi_device_csb_read.3534962913 |
|
|
Mar 12 03:06:55 PM PDT 24 |
Mar 12 03:06:56 PM PDT 24 |
26441017 ps |
| T1903 |
/workspace/coverage/default/43.spi_device_tpm_sts_read.424670700 |
|
|
Mar 12 03:10:21 PM PDT 24 |
Mar 12 03:10:23 PM PDT 24 |
51465352 ps |
| T1904 |
/workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3163878392 |
|
|
Mar 12 01:10:54 PM PDT 24 |
Mar 12 01:10:57 PM PDT 24 |
298995466 ps |
| T1905 |
/workspace/coverage/default/31.spi_device_pass_cmd_filtering.3265831352 |
|
|
Mar 12 01:12:16 PM PDT 24 |
Mar 12 01:12:23 PM PDT 24 |
1798844417 ps |
| T1906 |
/workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2411430142 |
|
|
Mar 12 03:06:46 PM PDT 24 |
Mar 12 03:08:51 PM PDT 24 |
49920612890 ps |
| T1907 |
/workspace/coverage/default/22.spi_device_tpm_sts_read.1008487880 |
|
|
Mar 12 01:11:44 PM PDT 24 |
Mar 12 01:11:45 PM PDT 24 |
82070496 ps |
| T1908 |
/workspace/coverage/default/39.spi_device_upload.2566303526 |
|
|
Mar 12 01:12:36 PM PDT 24 |
Mar 12 01:12:41 PM PDT 24 |
3685311108 ps |
| T1909 |
/workspace/coverage/default/7.spi_device_flash_mode.1531946510 |
|
|
Mar 12 03:06:20 PM PDT 24 |
Mar 12 03:06:34 PM PDT 24 |
970718000 ps |
| T1910 |
/workspace/coverage/default/10.spi_device_intercept.2879373974 |
|
|
Mar 12 01:11:07 PM PDT 24 |
Mar 12 01:11:18 PM PDT 24 |
2550009332 ps |
| T1911 |
/workspace/coverage/default/45.spi_device_stress_all.44401271 |
|
|
Mar 12 03:10:47 PM PDT 24 |
Mar 12 03:10:48 PM PDT 24 |
31473092 ps |
| T1912 |
/workspace/coverage/default/39.spi_device_flash_mode.2974960812 |
|
|
Mar 12 03:10:01 PM PDT 24 |
Mar 12 03:10:18 PM PDT 24 |
797659650 ps |
| T1913 |
/workspace/coverage/default/2.spi_device_ram_cfg.4155954735 |
|
|
Mar 12 03:05:17 PM PDT 24 |
Mar 12 03:05:18 PM PDT 24 |
19525653 ps |
| T1914 |
/workspace/coverage/default/45.spi_device_tpm_read_hw_reg.275704569 |
|
|
Mar 12 03:10:41 PM PDT 24 |
Mar 12 03:10:43 PM PDT 24 |
128162233 ps |
| T1915 |
/workspace/coverage/default/49.spi_device_tpm_rw.3257015650 |
|
|
Mar 12 03:11:00 PM PDT 24 |
Mar 12 03:11:03 PM PDT 24 |
980969968 ps |
| T1916 |
/workspace/coverage/default/28.spi_device_intercept.3573577786 |
|
|
Mar 12 01:12:00 PM PDT 24 |
Mar 12 01:12:14 PM PDT 24 |
15893823894 ps |
| T1917 |
/workspace/coverage/default/23.spi_device_pass_cmd_filtering.3244076185 |
|
|
Mar 12 03:08:14 PM PDT 24 |
Mar 12 03:08:20 PM PDT 24 |
994412610 ps |
| T1918 |
/workspace/coverage/default/29.spi_device_pass_cmd_filtering.504095408 |
|
|
Mar 12 03:08:53 PM PDT 24 |
Mar 12 03:09:05 PM PDT 24 |
11195318746 ps |
| T1919 |
/workspace/coverage/default/28.spi_device_tpm_rw.3913768519 |
|
|
Mar 12 03:08:54 PM PDT 24 |
Mar 12 03:08:59 PM PDT 24 |
297144541 ps |
| T1920 |
/workspace/coverage/default/8.spi_device_stress_all.2026839039 |
|
|
Mar 12 03:06:19 PM PDT 24 |
Mar 12 03:13:17 PM PDT 24 |
72428407033 ps |
| T1921 |
/workspace/coverage/default/49.spi_device_flash_all.3297678893 |
|
|
Mar 12 01:13:20 PM PDT 24 |
Mar 12 01:15:20 PM PDT 24 |
19550618418 ps |
| T1922 |
/workspace/coverage/default/36.spi_device_mailbox.695191305 |
|
|
Mar 12 03:09:59 PM PDT 24 |
Mar 12 03:10:22 PM PDT 24 |
19677640654 ps |
| T1923 |
/workspace/coverage/default/21.spi_device_tpm_all.2916856364 |
|
|
Mar 12 01:11:43 PM PDT 24 |
Mar 12 01:12:10 PM PDT 24 |
9905659410 ps |
| T1924 |
/workspace/coverage/default/17.spi_device_upload.2800011416 |
|
|
Mar 12 03:07:37 PM PDT 24 |
Mar 12 03:07:43 PM PDT 24 |
616786159 ps |
| T1925 |
/workspace/coverage/default/14.spi_device_intercept.3369334000 |
|
|
Mar 12 01:11:14 PM PDT 24 |
Mar 12 01:11:23 PM PDT 24 |
2314330235 ps |
| T1926 |
/workspace/coverage/default/47.spi_device_intercept.1391516644 |
|
|
Mar 12 01:13:04 PM PDT 24 |
Mar 12 01:13:09 PM PDT 24 |
1131658077 ps |
| T1927 |
/workspace/coverage/default/8.spi_device_flash_mode.1405431137 |
|
|
Mar 12 03:06:17 PM PDT 24 |
Mar 12 03:06:24 PM PDT 24 |
1839403924 ps |
| T1928 |
/workspace/coverage/default/17.spi_device_pass_cmd_filtering.191404701 |
|
|
Mar 12 01:11:32 PM PDT 24 |
Mar 12 01:11:47 PM PDT 24 |
41514657983 ps |
| T1929 |
/workspace/coverage/default/6.spi_device_stress_all.3916210167 |
|
|
Mar 12 01:10:59 PM PDT 24 |
Mar 12 01:15:56 PM PDT 24 |
49758273439 ps |
| T1930 |
/workspace/coverage/default/14.spi_device_flash_and_tpm.2068130802 |
|
|
Mar 12 01:11:14 PM PDT 24 |
Mar 12 01:22:58 PM PDT 24 |
91117852074 ps |
| T1931 |
/workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.268181712 |
|
|
Mar 12 01:11:06 PM PDT 24 |
Mar 12 01:13:19 PM PDT 24 |
22068906458 ps |
| T1932 |
/workspace/coverage/default/8.spi_device_mem_parity.655528864 |
|
|
Mar 12 01:10:58 PM PDT 24 |
Mar 12 01:10:59 PM PDT 24 |
27880099 ps |
| T1933 |
/workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1629672736 |
|
|
Mar 12 03:09:38 PM PDT 24 |
Mar 12 03:10:19 PM PDT 24 |
2108577280 ps |
| T1934 |
/workspace/coverage/default/8.spi_device_tpm_all.1601274804 |
|
|
Mar 12 01:10:54 PM PDT 24 |
Mar 12 01:11:00 PM PDT 24 |
879932854 ps |
| T1935 |
/workspace/coverage/default/7.spi_device_mem_parity.585066845 |
|
|
Mar 12 01:10:58 PM PDT 24 |
Mar 12 01:10:59 PM PDT 24 |
33766083 ps |
| T1936 |
/workspace/coverage/default/15.spi_device_tpm_rw.3922386613 |
|
|
Mar 12 01:11:17 PM PDT 24 |
Mar 12 01:11:20 PM PDT 24 |
123907918 ps |
| T1937 |
/workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3025634564 |
|
|
Mar 12 01:10:52 PM PDT 24 |
Mar 12 01:11:01 PM PDT 24 |
8186756218 ps |
| T1938 |
/workspace/coverage/default/15.spi_device_stress_all.4064025824 |
|
|
Mar 12 01:11:19 PM PDT 24 |
Mar 12 01:15:51 PM PDT 24 |
278321587418 ps |
| T1939 |
/workspace/coverage/default/20.spi_device_tpm_sts_read.2500404041 |
|
|
Mar 12 03:07:48 PM PDT 24 |
Mar 12 03:07:49 PM PDT 24 |
60796132 ps |
| T1940 |
/workspace/coverage/default/22.spi_device_upload.2961599186 |
|
|
Mar 12 03:08:12 PM PDT 24 |
Mar 12 03:08:18 PM PDT 24 |
1091654013 ps |
| T149 |
/workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.529103744 |
|
|
Mar 12 12:45:56 PM PDT 24 |
Mar 12 12:45:59 PM PDT 24 |
150857729 ps |
| T150 |
/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1428144605 |
|
|
Mar 12 12:59:17 PM PDT 24 |
Mar 12 12:59:20 PM PDT 24 |
541091275 ps |
| T93 |
/workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1676868505 |
|
|
Mar 12 12:46:24 PM PDT 24 |
Mar 12 12:46:29 PM PDT 24 |
510644495 ps |
| T1941 |
/workspace/coverage/cover_reg_top/12.spi_device_intr_test.2655267033 |
|
|
Mar 12 12:59:26 PM PDT 24 |
Mar 12 12:59:27 PM PDT 24 |
15276854 ps |
| T1942 |
/workspace/coverage/cover_reg_top/42.spi_device_intr_test.2032155287 |
|
|
Mar 12 12:46:25 PM PDT 24 |
Mar 12 12:46:27 PM PDT 24 |
15992046 ps |
| T94 |
/workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.861613183 |
|
|
Mar 12 12:45:57 PM PDT 24 |
Mar 12 12:46:07 PM PDT 24 |
1270401043 ps |
| T151 |
/workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.460145768 |
|
|
Mar 12 12:59:24 PM PDT 24 |
Mar 12 12:59:26 PM PDT 24 |
73634816 ps |
| T1943 |
/workspace/coverage/cover_reg_top/16.spi_device_intr_test.3481614274 |
|
|
Mar 12 12:59:46 PM PDT 24 |
Mar 12 12:59:47 PM PDT 24 |
59612524 ps |
| T1944 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.85637548 |
|
|
Mar 12 12:46:00 PM PDT 24 |
Mar 12 12:46:16 PM PDT 24 |
332809181 ps |
| T1945 |
/workspace/coverage/cover_reg_top/35.spi_device_intr_test.1969561499 |
|
|
Mar 12 12:59:52 PM PDT 24 |
Mar 12 12:59:53 PM PDT 24 |
16961343 ps |
| T152 |
/workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2293955004 |
|
|
Mar 12 12:59:48 PM PDT 24 |
Mar 12 12:59:53 PM PDT 24 |
210653842 ps |
| T1946 |
/workspace/coverage/cover_reg_top/19.spi_device_intr_test.3417960211 |
|
|
Mar 12 12:46:20 PM PDT 24 |
Mar 12 12:46:21 PM PDT 24 |
40528981 ps |
| T95 |
/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2225819154 |
|
|
Mar 12 12:46:08 PM PDT 24 |
Mar 12 12:46:15 PM PDT 24 |
258834455 ps |
| T96 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.438888291 |
|
|
Mar 12 12:59:14 PM PDT 24 |
Mar 12 12:59:17 PM PDT 24 |
116566764 ps |
| T97 |
/workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.731785002 |
|
|
Mar 12 12:59:23 PM PDT 24 |
Mar 12 12:59:30 PM PDT 24 |
324265361 ps |
| T1947 |
/workspace/coverage/cover_reg_top/43.spi_device_intr_test.2393790112 |
|
|
Mar 12 12:59:36 PM PDT 24 |
Mar 12 12:59:37 PM PDT 24 |
17254053 ps |
| T119 |
/workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1397467794 |
|
|
Mar 12 12:46:04 PM PDT 24 |
Mar 12 12:46:05 PM PDT 24 |
105106017 ps |
| T1948 |
/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.374061144 |
|
|
Mar 12 12:59:31 PM PDT 24 |
Mar 12 12:59:35 PM PDT 24 |
2145488721 ps |
| T153 |
/workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.787346863 |
|
|
Mar 12 12:59:12 PM PDT 24 |
Mar 12 12:59:15 PM PDT 24 |
134045591 ps |
| T120 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3135433177 |
|
|
Mar 12 01:01:23 PM PDT 24 |
Mar 12 01:01:27 PM PDT 24 |
119227797 ps |
| T1949 |
/workspace/coverage/cover_reg_top/31.spi_device_intr_test.3746275500 |
|
|
Mar 12 12:59:53 PM PDT 24 |
Mar 12 12:59:54 PM PDT 24 |
23914894 ps |
| T101 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4173510221 |
|
|
Mar 12 12:45:57 PM PDT 24 |
Mar 12 12:46:01 PM PDT 24 |
58440186 ps |
| T121 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3145514311 |
|
|
Mar 12 12:59:29 PM PDT 24 |
Mar 12 12:59:56 PM PDT 24 |
16399073117 ps |
| T115 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3431047388 |
|
|
Mar 12 12:45:57 PM PDT 24 |
Mar 12 12:46:00 PM PDT 24 |
103028647 ps |
| T1950 |
/workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2564396080 |
|
|
Mar 12 12:59:20 PM PDT 24 |
Mar 12 12:59:20 PM PDT 24 |
68320314 ps |
| T1951 |
/workspace/coverage/cover_reg_top/6.spi_device_intr_test.354631636 |
|
|
Mar 12 12:46:00 PM PDT 24 |
Mar 12 12:46:01 PM PDT 24 |
45847721 ps |
| T1952 |
/workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3305789124 |
|
|
Mar 12 12:46:07 PM PDT 24 |
Mar 12 12:46:12 PM PDT 24 |
60433609 ps |
| T1953 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1055471759 |
|
|
Mar 12 12:46:03 PM PDT 24 |
Mar 12 12:46:15 PM PDT 24 |
1479452570 ps |
| T1954 |
/workspace/coverage/cover_reg_top/28.spi_device_intr_test.1946412459 |
|
|
Mar 12 12:59:55 PM PDT 24 |
Mar 12 12:59:56 PM PDT 24 |
13769293 ps |
| T1955 |
/workspace/coverage/cover_reg_top/41.spi_device_intr_test.2130658491 |
|
|
Mar 12 12:46:28 PM PDT 24 |
Mar 12 12:46:30 PM PDT 24 |
24646832 ps |
| T76 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2023363875 |
|
|
Mar 12 12:59:09 PM PDT 24 |
Mar 12 12:59:10 PM PDT 24 |
114469471 ps |
| T98 |
/workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2606973116 |
|
|
Mar 12 12:59:17 PM PDT 24 |
Mar 12 12:59:21 PM PDT 24 |
163788608 ps |
| T99 |
/workspace/coverage/cover_reg_top/3.spi_device_tl_errors.526614086 |
|
|
Mar 12 01:01:30 PM PDT 24 |
Mar 12 01:01:33 PM PDT 24 |
90954147 ps |
| T122 |
/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1513173484 |
|
|
Mar 12 12:46:10 PM PDT 24 |
Mar 12 12:46:15 PM PDT 24 |
73610935 ps |
| T1956 |
/workspace/coverage/cover_reg_top/21.spi_device_intr_test.4219689753 |
|
|
Mar 12 12:59:47 PM PDT 24 |
Mar 12 12:59:48 PM PDT 24 |
43068082 ps |
| T123 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2090210197 |
|
|
Mar 12 12:45:57 PM PDT 24 |
Mar 12 12:45:59 PM PDT 24 |
32828444 ps |
| T100 |
/workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2001070117 |
|
|
Mar 12 12:45:54 PM PDT 24 |
Mar 12 12:46:09 PM PDT 24 |
713033116 ps |
| T124 |
/workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1800233770 |
|
|
Mar 12 12:59:38 PM PDT 24 |
Mar 12 12:59:41 PM PDT 24 |
185508856 ps |
| T117 |
/workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.266641857 |
|
|
Mar 12 12:59:33 PM PDT 24 |
Mar 12 12:59:47 PM PDT 24 |
3006281152 ps |
| T1957 |
/workspace/coverage/cover_reg_top/39.spi_device_intr_test.1777538055 |
|
|
Mar 12 12:59:50 PM PDT 24 |
Mar 12 12:59:51 PM PDT 24 |
13925645 ps |
| T125 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2354345748 |
|
|
Mar 12 12:59:22 PM PDT 24 |
Mar 12 12:59:30 PM PDT 24 |
410127976 ps |
| T1958 |
/workspace/coverage/cover_reg_top/17.spi_device_intr_test.146639400 |
|
|
Mar 12 12:46:24 PM PDT 24 |
Mar 12 12:46:25 PM PDT 24 |
46408858 ps |
| T1959 |
/workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3681455884 |
|
|
Mar 12 12:46:07 PM PDT 24 |
Mar 12 12:46:09 PM PDT 24 |
53272480 ps |
| T116 |
/workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1368307796 |
|
|
Mar 12 12:46:11 PM PDT 24 |
Mar 12 12:46:27 PM PDT 24 |
213225297 ps |
| T113 |
/workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2772087164 |
|
|
Mar 12 01:00:54 PM PDT 24 |
Mar 12 01:01:14 PM PDT 24 |
3307060454 ps |
| T1960 |
/workspace/coverage/cover_reg_top/44.spi_device_intr_test.2636341917 |
|
|
Mar 12 12:59:54 PM PDT 24 |
Mar 12 12:59:55 PM PDT 24 |
12733697 ps |
| T1961 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2927793090 |
|
|
Mar 12 12:59:13 PM PDT 24 |
Mar 12 12:59:14 PM PDT 24 |
19607899 ps |
| T107 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4064891542 |
|
|
Mar 12 12:59:14 PM PDT 24 |
Mar 12 12:59:17 PM PDT 24 |
81625108 ps |
| T1962 |
/workspace/coverage/cover_reg_top/46.spi_device_intr_test.1176355723 |
|
|
Mar 12 12:46:24 PM PDT 24 |
Mar 12 12:46:26 PM PDT 24 |
27061212 ps |
| T1963 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3197784746 |
|
|
Mar 12 12:59:40 PM PDT 24 |
Mar 12 12:59:41 PM PDT 24 |
63318565 ps |
| T112 |
/workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2236349046 |
|
|
Mar 12 12:46:03 PM PDT 24 |
Mar 12 12:46:06 PM PDT 24 |
70588722 ps |
| T1964 |
/workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3383350160 |
|
|
Mar 12 12:59:13 PM PDT 24 |
Mar 12 12:59:14 PM PDT 24 |
11355319 ps |
| T1965 |
/workspace/coverage/cover_reg_top/7.spi_device_csr_rw.611685045 |
|
|
Mar 12 12:59:33 PM PDT 24 |
Mar 12 12:59:34 PM PDT 24 |
20300243 ps |
| T126 |
/workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3941753643 |
|
|
Mar 12 12:59:10 PM PDT 24 |
Mar 12 12:59:12 PM PDT 24 |
49088407 ps |
| T127 |
/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1577682015 |
|
|
Mar 12 12:59:17 PM PDT 24 |
Mar 12 12:59:20 PM PDT 24 |
332473023 ps |
| T1966 |
/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1833193485 |
|
|
Mar 12 12:59:53 PM PDT 24 |
Mar 12 12:59:57 PM PDT 24 |
66068658 ps |
| T1967 |
/workspace/coverage/cover_reg_top/18.spi_device_intr_test.2228669881 |
|
|
Mar 12 12:59:35 PM PDT 24 |
Mar 12 12:59:36 PM PDT 24 |
13774478 ps |
| T104 |
/workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2081172150 |
|
|
Mar 12 12:59:48 PM PDT 24 |
Mar 12 12:59:50 PM PDT 24 |
57589037 ps |
| T102 |
/workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2927201044 |
|
|
Mar 12 12:46:06 PM PDT 24 |
Mar 12 12:46:10 PM PDT 24 |
541666363 ps |
| T1968 |
/workspace/coverage/cover_reg_top/20.spi_device_intr_test.2320459389 |
|
|
Mar 12 12:46:25 PM PDT 24 |
Mar 12 12:46:26 PM PDT 24 |
21215754 ps |
| T1969 |
/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1957172938 |
|
|
Mar 12 12:45:49 PM PDT 24 |
Mar 12 12:45:52 PM PDT 24 |
165961271 ps |
| T1970 |
/workspace/coverage/cover_reg_top/5.spi_device_intr_test.3012364682 |
|
|
Mar 12 12:59:38 PM PDT 24 |
Mar 12 12:59:39 PM PDT 24 |
15609221 ps |
| T1971 |
/workspace/coverage/cover_reg_top/25.spi_device_intr_test.451315914 |
|
|
Mar 12 12:46:20 PM PDT 24 |
Mar 12 12:46:21 PM PDT 24 |
23900865 ps |
| T1972 |
/workspace/coverage/cover_reg_top/4.spi_device_intr_test.3714904230 |
|
|
Mar 12 12:45:55 PM PDT 24 |
Mar 12 12:45:56 PM PDT 24 |
31635881 ps |
| T181 |
/workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1381096078 |
|
|
Mar 12 12:59:44 PM PDT 24 |
Mar 12 01:00:09 PM PDT 24 |
4015592389 ps |
| T128 |
/workspace/coverage/cover_reg_top/19.spi_device_csr_rw.4067636129 |
|
|
Mar 12 12:46:20 PM PDT 24 |
Mar 12 12:46:23 PM PDT 24 |
41289952 ps |
| T1973 |
/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2870972629 |
|
|
Mar 12 12:46:08 PM PDT 24 |
Mar 12 12:46:15 PM PDT 24 |
486526079 ps |
| T1974 |
/workspace/coverage/cover_reg_top/47.spi_device_intr_test.212703808 |
|
|
Mar 12 12:59:56 PM PDT 24 |
Mar 12 12:59:57 PM PDT 24 |
43121509 ps |
| T1975 |
/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2600653247 |
|
|
Mar 12 12:59:49 PM PDT 24 |
Mar 12 12:59:52 PM PDT 24 |
83573133 ps |
| T1976 |
/workspace/coverage/cover_reg_top/0.spi_device_intr_test.539930677 |
|
|
Mar 12 12:45:46 PM PDT 24 |
Mar 12 12:45:47 PM PDT 24 |
32079844 ps |
| T1977 |
/workspace/coverage/cover_reg_top/34.spi_device_intr_test.3947889993 |
|
|
Mar 12 12:59:50 PM PDT 24 |
Mar 12 12:59:51 PM PDT 24 |
23989139 ps |
| T1978 |
/workspace/coverage/cover_reg_top/7.spi_device_intr_test.327909509 |
|
|
Mar 12 12:46:07 PM PDT 24 |
Mar 12 12:46:08 PM PDT 24 |
19587415 ps |
| T1979 |
/workspace/coverage/cover_reg_top/21.spi_device_intr_test.4147822273 |
|
|
Mar 12 12:46:24 PM PDT 24 |
Mar 12 12:46:25 PM PDT 24 |
38479121 ps |
| T129 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.9045855 |
|
|
Mar 12 12:59:15 PM PDT 24 |
Mar 12 12:59:16 PM PDT 24 |
35038650 ps |
| T1980 |
/workspace/coverage/cover_reg_top/41.spi_device_intr_test.2815234669 |
|
|
Mar 12 12:59:52 PM PDT 24 |
Mar 12 12:59:54 PM PDT 24 |
37126968 ps |
| T1981 |
/workspace/coverage/cover_reg_top/1.spi_device_intr_test.1400071159 |
|
|
Mar 12 12:45:51 PM PDT 24 |
Mar 12 12:45:52 PM PDT 24 |
36509723 ps |
| T1982 |
/workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1856521989 |
|
|
Mar 12 12:59:21 PM PDT 24 |
Mar 12 12:59:22 PM PDT 24 |
223047409 ps |
| T1983 |
/workspace/coverage/cover_reg_top/38.spi_device_intr_test.2100369437 |
|
|
Mar 12 12:59:48 PM PDT 24 |
Mar 12 12:59:48 PM PDT 24 |
11893957 ps |
| T1984 |
/workspace/coverage/cover_reg_top/3.spi_device_intr_test.622507151 |
|
|
Mar 12 12:59:13 PM PDT 24 |
Mar 12 12:59:14 PM PDT 24 |
13159934 ps |
| T1985 |
/workspace/coverage/cover_reg_top/31.spi_device_intr_test.2273126805 |
|
|
Mar 12 12:46:27 PM PDT 24 |
Mar 12 12:46:28 PM PDT 24 |
20542442 ps |
| T77 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1378704328 |
|
|
Mar 12 12:45:56 PM PDT 24 |
Mar 12 12:45:57 PM PDT 24 |
77055829 ps |
| T1986 |
/workspace/coverage/cover_reg_top/4.spi_device_intr_test.906633708 |
|
|
Mar 12 01:01:30 PM PDT 24 |
Mar 12 01:01:31 PM PDT 24 |
129418387 ps |
| T106 |
/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.510663335 |
|
|
Mar 12 12:59:48 PM PDT 24 |
Mar 12 12:59:52 PM PDT 24 |
173452524 ps |
| T111 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.835692069 |
|
|
Mar 12 12:45:46 PM PDT 24 |
Mar 12 12:45:49 PM PDT 24 |
199084426 ps |
| T105 |
/workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2855775978 |
|
|
Mar 12 12:59:25 PM PDT 24 |
Mar 12 12:59:28 PM PDT 24 |
148798861 ps |
| T114 |
/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1799439534 |
|
|
Mar 12 12:46:11 PM PDT 24 |
Mar 12 12:46:18 PM PDT 24 |
199832996 ps |
| T1987 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1834189435 |
|
|
Mar 12 12:45:45 PM PDT 24 |
Mar 12 12:46:23 PM PDT 24 |
6719807350 ps |
| T130 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1661643651 |
|
|
Mar 12 12:59:24 PM PDT 24 |
Mar 12 12:59:33 PM PDT 24 |
766384547 ps |
| T1988 |
/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.870602892 |
|
|
Mar 12 12:45:56 PM PDT 24 |
Mar 12 12:45:58 PM PDT 24 |
150275909 ps |
| T176 |
/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.936278944 |
|
|
Mar 12 12:46:07 PM PDT 24 |
Mar 12 12:46:22 PM PDT 24 |
602946322 ps |
| T177 |
/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.896487795 |
|
|
Mar 12 12:59:26 PM PDT 24 |
Mar 12 12:59:38 PM PDT 24 |
786712905 ps |
| T1989 |
/workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.66851662 |
|
|
Mar 12 12:59:22 PM PDT 24 |
Mar 12 12:59:25 PM PDT 24 |
40986438 ps |
| T109 |
/workspace/coverage/cover_reg_top/0.spi_device_tl_errors.435669765 |
|
|
Mar 12 12:59:18 PM PDT 24 |
Mar 12 12:59:20 PM PDT 24 |
915601522 ps |
| T1990 |
/workspace/coverage/cover_reg_top/25.spi_device_intr_test.2634389291 |
|
|
Mar 12 12:59:47 PM PDT 24 |
Mar 12 12:59:48 PM PDT 24 |
15092513 ps |
| T1991 |
/workspace/coverage/cover_reg_top/13.spi_device_intr_test.1040817188 |
|
|
Mar 12 12:46:09 PM PDT 24 |
Mar 12 12:46:13 PM PDT 24 |
11619756 ps |
| T1992 |
/workspace/coverage/cover_reg_top/14.spi_device_intr_test.2024424878 |
|
|
Mar 12 12:46:13 PM PDT 24 |
Mar 12 12:46:15 PM PDT 24 |
20832095 ps |
| T1993 |
/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3062377498 |
|
|
Mar 12 12:46:12 PM PDT 24 |
Mar 12 12:46:22 PM PDT 24 |
343974688 ps |
| T132 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1900862272 |
|
|
Mar 12 12:45:51 PM PDT 24 |
Mar 12 12:46:13 PM PDT 24 |
365870955 ps |
| T1994 |
/workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2854054567 |
|
|
Mar 12 12:59:51 PM PDT 24 |
Mar 12 12:59:55 PM PDT 24 |
179463358 ps |
| T1995 |
/workspace/coverage/cover_reg_top/19.spi_device_tl_errors.51295783 |
|
|
Mar 12 12:46:21 PM PDT 24 |
Mar 12 12:46:23 PM PDT 24 |
157143073 ps |
| T1996 |
/workspace/coverage/cover_reg_top/37.spi_device_intr_test.2257725062 |
|
|
Mar 12 12:46:24 PM PDT 24 |
Mar 12 12:46:31 PM PDT 24 |
11459740 ps |
| T1997 |
/workspace/coverage/cover_reg_top/0.spi_device_intr_test.2191026952 |
|
|
Mar 12 12:59:15 PM PDT 24 |
Mar 12 12:59:16 PM PDT 24 |
35985761 ps |
| T183 |
/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.900804566 |
|
|
Mar 12 12:46:22 PM PDT 24 |
Mar 12 12:46:39 PM PDT 24 |
303290577 ps |
| T1998 |
/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2773168293 |
|
|
Mar 12 12:46:21 PM PDT 24 |
Mar 12 12:46:24 PM PDT 24 |
41812987 ps |
| T1999 |
/workspace/coverage/cover_reg_top/18.spi_device_intr_test.1843481791 |
|
|
Mar 12 12:46:19 PM PDT 24 |
Mar 12 12:46:20 PM PDT 24 |
11269849 ps |
| T103 |
/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3670949461 |
|
|
Mar 12 12:59:38 PM PDT 24 |
Mar 12 12:59:43 PM PDT 24 |
383870454 ps |
| T2000 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3506412490 |
|
|
Mar 12 12:59:22 PM PDT 24 |
Mar 12 12:59:39 PM PDT 24 |
698176477 ps |
| T131 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3058372683 |
|
|
Mar 12 12:59:15 PM PDT 24 |
Mar 12 12:59:17 PM PDT 24 |
76802609 ps |
| T108 |
/workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1407547817 |
|
|
Mar 12 12:59:20 PM PDT 24 |
Mar 12 12:59:22 PM PDT 24 |
93185285 ps |
| T2001 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.238527646 |
|
|
Mar 12 12:59:09 PM PDT 24 |
Mar 12 12:59:11 PM PDT 24 |
27261660 ps |
| T133 |
/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1992113828 |
|
|
Mar 12 12:59:47 PM PDT 24 |
Mar 12 12:59:50 PM PDT 24 |
312573540 ps |
| T2002 |
/workspace/coverage/cover_reg_top/39.spi_device_intr_test.3307399675 |
|
|
Mar 12 12:46:22 PM PDT 24 |
Mar 12 12:46:24 PM PDT 24 |
26858079 ps |
| T2003 |
/workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4016540133 |
|
|
Mar 12 12:59:35 PM PDT 24 |
Mar 12 12:59:38 PM PDT 24 |
82000660 ps |
| T2004 |
/workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.4096022796 |
|
|
Mar 12 12:59:16 PM PDT 24 |
Mar 12 12:59:20 PM PDT 24 |
207697684 ps |
| T2005 |
/workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2177760869 |
|
|
Mar 12 12:59:22 PM PDT 24 |
Mar 12 12:59:24 PM PDT 24 |
71890523 ps |
| T110 |
/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3355186334 |
|
|
Mar 12 12:46:10 PM PDT 24 |
Mar 12 12:46:16 PM PDT 24 |
58229931 ps |
| T2006 |
/workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2218819725 |
|
|
Mar 12 12:59:44 PM PDT 24 |
Mar 12 12:59:46 PM PDT 24 |
59940788 ps |
| T2007 |
/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2243548806 |
|
|
Mar 12 12:46:09 PM PDT 24 |
Mar 12 12:46:14 PM PDT 24 |
96486344 ps |
| T2008 |
/workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2170897024 |
|
|
Mar 12 12:46:18 PM PDT 24 |
Mar 12 12:46:19 PM PDT 24 |
180326842 ps |
| T2009 |
/workspace/coverage/cover_reg_top/40.spi_device_intr_test.3380436914 |
|
|
Mar 12 12:46:23 PM PDT 24 |
Mar 12 12:46:24 PM PDT 24 |
15750822 ps |
| T78 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1140591094 |
|
|
Mar 12 12:46:02 PM PDT 24 |
Mar 12 12:46:04 PM PDT 24 |
21721478 ps |
| T2010 |
/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1287697884 |
|
|
Mar 12 12:59:20 PM PDT 24 |
Mar 12 12:59:22 PM PDT 24 |
39541014 ps |
| T2011 |
/workspace/coverage/cover_reg_top/34.spi_device_intr_test.934051063 |
|
|
Mar 12 12:46:26 PM PDT 24 |
Mar 12 12:46:27 PM PDT 24 |
17883789 ps |
| T134 |
/workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2952078452 |
|
|
Mar 12 12:45:57 PM PDT 24 |
Mar 12 12:45:59 PM PDT 24 |
65051517 ps |
| T2012 |
/workspace/coverage/cover_reg_top/22.spi_device_intr_test.3886160783 |
|
|
Mar 12 12:59:53 PM PDT 24 |
Mar 12 12:59:54 PM PDT 24 |
150618357 ps |