Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.99 98.38 94.43 98.61 89.36 97.10 95.82 98.22


Total test records in report: 2225
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html
T178 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2438580109 Mar 12 01:01:34 PM PDT 24 Mar 12 01:01:49 PM PDT 24 1140719513 ps
T2013 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2053177421 Mar 12 01:01:34 PM PDT 24 Mar 12 01:01:35 PM PDT 24 63586519 ps
T2014 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2035177626 Mar 12 12:59:38 PM PDT 24 Mar 12 12:59:41 PM PDT 24 93869479 ps
T180 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.4093548931 Mar 12 12:59:32 PM PDT 24 Mar 12 12:59:52 PM PDT 24 772620647 ps
T2015 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1667511717 Mar 12 12:59:38 PM PDT 24 Mar 12 12:59:47 PM PDT 24 471986892 ps
T2016 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3209037932 Mar 12 12:59:41 PM PDT 24 Mar 12 12:59:42 PM PDT 24 178786720 ps
T2017 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.4190362712 Mar 12 12:59:22 PM PDT 24 Mar 12 12:59:24 PM PDT 24 138465185 ps
T2018 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2915699161 Mar 12 12:45:56 PM PDT 24 Mar 12 12:45:59 PM PDT 24 205450687 ps
T2019 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2613346340 Mar 12 12:59:29 PM PDT 24 Mar 12 12:59:29 PM PDT 24 48402822 ps
T2020 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.756980234 Mar 12 12:46:08 PM PDT 24 Mar 12 12:46:15 PM PDT 24 283744314 ps
T135 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.359690241 Mar 12 12:59:43 PM PDT 24 Mar 12 12:59:44 PM PDT 24 67830476 ps
T179 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2974105522 Mar 12 01:01:34 PM PDT 24 Mar 12 01:01:47 PM PDT 24 539807148 ps
T2021 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3843231977 Mar 12 12:59:40 PM PDT 24 Mar 12 12:59:45 PM PDT 24 485006759 ps
T2022 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1443477020 Mar 12 12:59:24 PM PDT 24 Mar 12 12:59:39 PM PDT 24 534056981 ps
T2023 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1062197410 Mar 12 12:59:12 PM PDT 24 Mar 12 12:59:14 PM PDT 24 84489168 ps
T2024 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.630268219 Mar 12 01:00:01 PM PDT 24 Mar 12 01:00:04 PM PDT 24 349731364 ps
T182 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.4078619015 Mar 12 12:59:33 PM PDT 24 Mar 12 12:59:41 PM PDT 24 339975015 ps
T2025 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2692508067 Mar 12 12:45:53 PM PDT 24 Mar 12 12:45:54 PM PDT 24 37609218 ps
T2026 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2870209392 Mar 12 12:46:21 PM PDT 24 Mar 12 12:46:22 PM PDT 24 40058295 ps
T2027 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3915894219 Mar 12 12:46:09 PM PDT 24 Mar 12 12:46:14 PM PDT 24 720499040 ps
T2028 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2808825847 Mar 12 12:46:28 PM PDT 24 Mar 12 12:46:29 PM PDT 24 16661895 ps
T2029 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.638232314 Mar 12 12:59:52 PM PDT 24 Mar 12 12:59:54 PM PDT 24 14778736 ps
T79 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.129711945 Mar 12 12:45:53 PM PDT 24 Mar 12 12:45:55 PM PDT 24 125805952 ps
T2030 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3993467185 Mar 12 12:59:10 PM PDT 24 Mar 12 12:59:36 PM PDT 24 1205936626 ps
T2031 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.224983350 Mar 12 12:46:07 PM PDT 24 Mar 12 12:46:10 PM PDT 24 64105710 ps
T2032 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3197466044 Mar 12 12:59:57 PM PDT 24 Mar 12 12:59:58 PM PDT 24 16962870 ps
T2033 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2950233055 Mar 12 12:59:49 PM PDT 24 Mar 12 01:00:11 PM PDT 24 1723527059 ps
T2034 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.636610347 Mar 12 12:46:22 PM PDT 24 Mar 12 12:46:26 PM PDT 24 823257291 ps
T2035 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1355690843 Mar 12 12:45:58 PM PDT 24 Mar 12 12:46:02 PM PDT 24 162506861 ps
T80 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1717100386 Mar 12 12:45:51 PM PDT 24 Mar 12 12:45:52 PM PDT 24 14612180 ps
T2036 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1291880637 Mar 12 12:59:18 PM PDT 24 Mar 12 12:59:41 PM PDT 24 3987376026 ps
T2037 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.973206104 Mar 12 12:46:02 PM PDT 24 Mar 12 12:46:04 PM PDT 24 19585106 ps
T2038 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1456599361 Mar 12 12:46:05 PM PDT 24 Mar 12 12:46:10 PM PDT 24 444826844 ps
T2039 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1278175527 Mar 12 12:59:17 PM PDT 24 Mar 12 12:59:29 PM PDT 24 189992186 ps
T81 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1061590898 Mar 12 12:59:14 PM PDT 24 Mar 12 12:59:15 PM PDT 24 18031503 ps
T2040 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2363388384 Mar 12 12:59:26 PM PDT 24 Mar 12 12:59:29 PM PDT 24 104441406 ps
T2041 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1906524823 Mar 12 12:59:52 PM PDT 24 Mar 12 12:59:54 PM PDT 24 47596100 ps
T2042 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.420166980 Mar 12 12:45:51 PM PDT 24 Mar 12 12:45:51 PM PDT 24 11963290 ps
T2043 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3410368458 Mar 12 12:46:25 PM PDT 24 Mar 12 12:46:27 PM PDT 24 18181567 ps
T2044 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1739068650 Mar 12 12:59:14 PM PDT 24 Mar 12 12:59:15 PM PDT 24 15090749 ps
T2045 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2176995463 Mar 12 12:59:56 PM PDT 24 Mar 12 12:59:57 PM PDT 24 41878440 ps
T2046 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.938184128 Mar 12 12:59:45 PM PDT 24 Mar 12 12:59:51 PM PDT 24 43859355 ps
T2047 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2670360298 Mar 12 12:46:23 PM PDT 24 Mar 12 12:46:25 PM PDT 24 12796391 ps
T2048 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3531912329 Mar 12 12:59:17 PM PDT 24 Mar 12 12:59:18 PM PDT 24 26717861 ps
T2049 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.16457375 Mar 12 12:59:24 PM PDT 24 Mar 12 12:59:25 PM PDT 24 19551506 ps
T2050 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.795254980 Mar 12 12:45:56 PM PDT 24 Mar 12 12:45:57 PM PDT 24 29606058 ps
T2051 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.584550151 Mar 12 12:46:26 PM PDT 24 Mar 12 12:46:27 PM PDT 24 14472801 ps
T2052 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.449160000 Mar 12 12:59:20 PM PDT 24 Mar 12 12:59:24 PM PDT 24 402048866 ps
T2053 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2946819919 Mar 12 12:59:46 PM PDT 24 Mar 12 12:59:49 PM PDT 24 371364584 ps
T2054 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.78793312 Mar 12 12:59:13 PM PDT 24 Mar 12 12:59:27 PM PDT 24 1675131193 ps
T2055 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2487286997 Mar 12 12:59:16 PM PDT 24 Mar 12 12:59:19 PM PDT 24 68713337 ps
T2056 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2782478642 Mar 12 12:46:08 PM PDT 24 Mar 12 12:46:18 PM PDT 24 1739567277 ps
T2057 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.334238016 Mar 12 12:59:46 PM PDT 24 Mar 12 12:59:49 PM PDT 24 112908517 ps
T2058 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.32275171 Mar 12 12:46:20 PM PDT 24 Mar 12 12:46:24 PM PDT 24 175279321 ps
T2059 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3915283036 Mar 12 12:45:48 PM PDT 24 Mar 12 12:45:50 PM PDT 24 133168032 ps
T2060 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.4100383245 Mar 12 12:59:42 PM PDT 24 Mar 12 12:59:43 PM PDT 24 24567419 ps
T2061 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2844273690 Mar 12 12:45:59 PM PDT 24 Mar 12 12:46:01 PM PDT 24 226044485 ps
T2062 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1145374707 Mar 12 12:45:59 PM PDT 24 Mar 12 12:46:03 PM PDT 24 240279494 ps
T2063 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2659526543 Mar 12 12:59:33 PM PDT 24 Mar 12 12:59:35 PM PDT 24 288407864 ps
T2064 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3563004869 Mar 12 12:59:49 PM PDT 24 Mar 12 12:59:52 PM PDT 24 58500474 ps
T173 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2106969100 Mar 12 12:59:49 PM PDT 24 Mar 12 12:59:53 PM PDT 24 629360962 ps
T2065 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2800853734 Mar 12 12:59:24 PM PDT 24 Mar 12 12:59:26 PM PDT 24 28286156 ps
T2066 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3557460229 Mar 12 12:59:17 PM PDT 24 Mar 12 12:59:18 PM PDT 24 15688110 ps
T2067 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.600747750 Mar 12 12:45:56 PM PDT 24 Mar 12 12:45:59 PM PDT 24 100318129 ps
T2068 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3741632414 Mar 12 12:59:17 PM PDT 24 Mar 12 12:59:18 PM PDT 24 10528558 ps
T2069 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3373276816 Mar 12 12:46:01 PM PDT 24 Mar 12 12:46:01 PM PDT 24 32380035 ps
T2070 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1104179319 Mar 12 12:46:09 PM PDT 24 Mar 12 12:46:15 PM PDT 24 88281642 ps
T2071 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.298230905 Mar 12 12:59:34 PM PDT 24 Mar 12 12:59:36 PM PDT 24 54915266 ps
T2072 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3636486582 Mar 12 12:46:25 PM PDT 24 Mar 12 12:46:26 PM PDT 24 12501623 ps
T2073 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2453302173 Mar 12 12:59:33 PM PDT 24 Mar 12 12:59:35 PM PDT 24 109423162 ps
T2074 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2152895593 Mar 12 12:46:30 PM PDT 24 Mar 12 12:46:32 PM PDT 24 111371049 ps
T2075 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.450594790 Mar 12 12:59:12 PM PDT 24 Mar 12 12:59:14 PM PDT 24 122030008 ps
T2076 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1878237553 Mar 12 12:45:57 PM PDT 24 Mar 12 12:45:58 PM PDT 24 64565802 ps
T2077 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2994310003 Mar 12 12:59:38 PM PDT 24 Mar 12 12:59:38 PM PDT 24 37037709 ps
T2078 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3088610586 Mar 12 12:59:34 PM PDT 24 Mar 12 12:59:35 PM PDT 24 87090198 ps
T2079 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.23811103 Mar 12 12:59:13 PM PDT 24 Mar 12 12:59:17 PM PDT 24 65872279 ps
T2080 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1525832210 Mar 12 12:46:27 PM PDT 24 Mar 12 12:46:28 PM PDT 24 44934442 ps
T2081 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.639800421 Mar 12 12:45:57 PM PDT 24 Mar 12 12:46:00 PM PDT 24 155901124 ps
T2082 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.120204964 Mar 12 12:59:36 PM PDT 24 Mar 12 12:59:37 PM PDT 24 48783939 ps
T2083 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2835615096 Mar 12 12:59:33 PM PDT 24 Mar 12 12:59:35 PM PDT 24 69598532 ps
T2084 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.79791781 Mar 12 12:45:46 PM PDT 24 Mar 12 12:46:00 PM PDT 24 559229137 ps
T2085 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1172295788 Mar 12 12:45:57 PM PDT 24 Mar 12 12:46:04 PM PDT 24 730808310 ps
T2086 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1054018322 Mar 12 12:46:24 PM PDT 24 Mar 12 12:46:25 PM PDT 24 27155882 ps
T2087 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.95409596 Mar 12 12:46:09 PM PDT 24 Mar 12 12:46:13 PM PDT 24 15410617 ps
T2088 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2140703022 Mar 12 12:59:33 PM PDT 24 Mar 12 12:59:34 PM PDT 24 73821788 ps
T2089 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.200530613 Mar 12 12:46:08 PM PDT 24 Mar 12 12:46:15 PM PDT 24 164406719 ps
T2090 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2404559864 Mar 12 12:59:43 PM PDT 24 Mar 12 12:59:44 PM PDT 24 18110383 ps
T2091 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2942600433 Mar 12 12:59:35 PM PDT 24 Mar 12 12:59:54 PM PDT 24 724594626 ps
T174 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1055584286 Mar 12 12:45:56 PM PDT 24 Mar 12 12:46:00 PM PDT 24 263561831 ps
T2092 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2173642591 Mar 12 12:46:07 PM PDT 24 Mar 12 12:46:09 PM PDT 24 13434243 ps
T2093 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1338813101 Mar 12 12:46:11 PM PDT 24 Mar 12 12:46:21 PM PDT 24 222150987 ps
T2094 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.474877605 Mar 12 12:46:22 PM PDT 24 Mar 12 12:46:23 PM PDT 24 13249328 ps
T2095 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3488404267 Mar 12 12:46:09 PM PDT 24 Mar 12 12:46:14 PM PDT 24 104407791 ps
T2096 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1251995141 Mar 12 12:45:51 PM PDT 24 Mar 12 12:45:52 PM PDT 24 806114044 ps
T2097 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.153201769 Mar 12 12:59:49 PM PDT 24 Mar 12 12:59:50 PM PDT 24 22003081 ps
T2098 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3495936399 Mar 12 12:59:26 PM PDT 24 Mar 12 12:59:28 PM PDT 24 30679188 ps
T2099 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1186711919 Mar 12 12:59:25 PM PDT 24 Mar 12 12:59:26 PM PDT 24 12022065 ps
T2100 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.355288573 Mar 12 12:46:19 PM PDT 24 Mar 12 12:46:21 PM PDT 24 27237639 ps
T2101 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1271024528 Mar 12 12:45:58 PM PDT 24 Mar 12 12:45:59 PM PDT 24 96130005 ps
T2102 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.756060607 Mar 12 12:59:32 PM PDT 24 Mar 12 12:59:34 PM PDT 24 243717206 ps
T2103 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.997221533 Mar 12 12:46:09 PM PDT 24 Mar 12 12:46:14 PM PDT 24 40385165 ps
T2104 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2295144338 Mar 12 12:59:17 PM PDT 24 Mar 12 12:59:21 PM PDT 24 309340062 ps
T2105 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.617838330 Mar 12 12:46:11 PM PDT 24 Mar 12 12:46:17 PM PDT 24 83098513 ps
T2106 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3822124046 Mar 12 12:46:03 PM PDT 24 Mar 12 12:46:06 PM PDT 24 157102837 ps
T2107 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.976432584 Mar 12 12:59:34 PM PDT 24 Mar 12 12:59:36 PM PDT 24 27377295 ps
T2108 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3972658191 Mar 12 12:46:28 PM PDT 24 Mar 12 12:46:29 PM PDT 24 37826644 ps
T2109 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2152978949 Mar 12 12:59:37 PM PDT 24 Mar 12 12:59:38 PM PDT 24 42049539 ps
T2110 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3767801396 Mar 12 12:59:13 PM PDT 24 Mar 12 12:59:36 PM PDT 24 1396769745 ps
T2111 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2861098365 Mar 12 12:46:08 PM PDT 24 Mar 12 12:46:33 PM PDT 24 1331697644 ps
T2112 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3117419218 Mar 12 12:59:17 PM PDT 24 Mar 12 12:59:51 PM PDT 24 1070153792 ps
T2113 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2031587353 Mar 12 12:45:48 PM PDT 24 Mar 12 12:45:49 PM PDT 24 125329779 ps
T2114 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.556979171 Mar 12 12:59:36 PM PDT 24 Mar 12 12:59:39 PM PDT 24 235988996 ps
T175 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2146255864 Mar 12 12:59:44 PM PDT 24 Mar 12 12:59:50 PM PDT 24 1116929724 ps
T2115 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3149103171 Mar 12 12:45:55 PM PDT 24 Mar 12 12:46:13 PM PDT 24 1564124029 ps
T2116 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.229492463 Mar 12 12:59:33 PM PDT 24 Mar 12 12:59:39 PM PDT 24 228253597 ps
T2117 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2128877754 Mar 12 12:59:20 PM PDT 24 Mar 12 12:59:23 PM PDT 24 534805754 ps
T2118 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3614366317 Mar 12 12:46:08 PM PDT 24 Mar 12 12:46:14 PM PDT 24 380336275 ps
T2119 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2144049240 Mar 12 12:59:20 PM PDT 24 Mar 12 12:59:22 PM PDT 24 275033638 ps
T2120 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2431576346 Mar 12 12:59:45 PM PDT 24 Mar 12 12:59:46 PM PDT 24 19360669 ps
T2121 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3950401205 Mar 12 12:45:58 PM PDT 24 Mar 12 12:46:01 PM PDT 24 668608420 ps
T2122 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.795713212 Mar 12 01:01:24 PM PDT 24 Mar 12 01:01:26 PM PDT 24 75493570 ps
T2123 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2370433512 Mar 12 12:46:14 PM PDT 24 Mar 12 12:46:19 PM PDT 24 226230413 ps
T2124 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.686658945 Mar 12 12:59:26 PM PDT 24 Mar 12 12:59:28 PM PDT 24 51280634 ps
T2125 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3956582527 Mar 12 12:46:07 PM PDT 24 Mar 12 12:46:19 PM PDT 24 413133690 ps
T2126 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1314551457 Mar 12 12:59:46 PM PDT 24 Mar 12 12:59:47 PM PDT 24 17911574 ps
T2127 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1805923111 Mar 12 12:45:51 PM PDT 24 Mar 12 12:46:14 PM PDT 24 10005875405 ps
T2128 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1379795252 Mar 12 12:46:09 PM PDT 24 Mar 12 12:46:14 PM PDT 24 40637356 ps
T2129 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4037241500 Mar 12 12:59:39 PM PDT 24 Mar 12 12:59:41 PM PDT 24 179998644 ps
T2130 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2630899938 Mar 12 12:46:09 PM PDT 24 Mar 12 12:46:14 PM PDT 24 82052746 ps
T2131 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.304738087 Mar 12 12:46:14 PM PDT 24 Mar 12 12:46:15 PM PDT 24 18487101 ps
T2132 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3400049828 Mar 12 12:46:06 PM PDT 24 Mar 12 12:46:08 PM PDT 24 228998842 ps
T2133 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3780033143 Mar 12 12:59:46 PM PDT 24 Mar 12 12:59:47 PM PDT 24 18683646 ps
T2134 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1284937169 Mar 12 12:46:24 PM PDT 24 Mar 12 12:46:26 PM PDT 24 16075246 ps
T2135 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.769982378 Mar 12 12:59:47 PM PDT 24 Mar 12 12:59:55 PM PDT 24 2645679285 ps
T2136 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3910141517 Mar 12 12:59:14 PM PDT 24 Mar 12 12:59:15 PM PDT 24 24751897 ps
T2137 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3416434927 Mar 12 12:46:12 PM PDT 24 Mar 12 12:46:17 PM PDT 24 367745608 ps
T2138 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1378918065 Mar 12 12:46:25 PM PDT 24 Mar 12 12:46:26 PM PDT 24 16098204 ps
T2139 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2220009329 Mar 12 12:45:55 PM PDT 24 Mar 12 12:46:35 PM PDT 24 10821547454 ps
T2140 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.284747499 Mar 12 12:59:45 PM PDT 24 Mar 12 12:59:46 PM PDT 24 45277752 ps
T2141 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1994588886 Mar 12 12:59:55 PM PDT 24 Mar 12 12:59:58 PM PDT 24 353886646 ps
T2142 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2580065419 Mar 12 12:46:12 PM PDT 24 Mar 12 12:46:17 PM PDT 24 137530475 ps
T2143 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2163810257 Mar 12 12:46:08 PM PDT 24 Mar 12 12:46:15 PM PDT 24 435949352 ps
T2144 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3888488408 Mar 12 12:46:20 PM PDT 24 Mar 12 12:46:41 PM PDT 24 983182476 ps
T2145 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1461261511 Mar 12 12:45:48 PM PDT 24 Mar 12 12:45:50 PM PDT 24 214012992 ps
T2146 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2619388461 Mar 12 12:59:51 PM PDT 24 Mar 12 12:59:53 PM PDT 24 12218043 ps
T2147 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2813573065 Mar 12 12:45:50 PM PDT 24 Mar 12 12:45:52 PM PDT 24 122565368 ps
T2148 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3822219194 Mar 12 12:59:46 PM PDT 24 Mar 12 12:59:47 PM PDT 24 17658232 ps
T2149 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3215141631 Mar 12 12:59:37 PM PDT 24 Mar 12 12:59:38 PM PDT 24 67682641 ps
T2150 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.582775718 Mar 12 12:46:25 PM PDT 24 Mar 12 12:46:26 PM PDT 24 19842579 ps
T2151 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1301674823 Mar 12 12:46:07 PM PDT 24 Mar 12 12:46:13 PM PDT 24 62797243 ps
T184 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3936063036 Mar 12 12:46:19 PM PDT 24 Mar 12 12:46:27 PM PDT 24 582901643 ps
T2152 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2316081322 Mar 12 12:46:27 PM PDT 24 Mar 12 12:46:28 PM PDT 24 37855375 ps
T2153 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3019743736 Mar 12 12:59:45 PM PDT 24 Mar 12 01:00:00 PM PDT 24 724298769 ps
T2154 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1921789461 Mar 12 12:59:42 PM PDT 24 Mar 12 12:59:45 PM PDT 24 301913852 ps
T2155 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3929260881 Mar 12 12:59:24 PM PDT 24 Mar 12 12:59:25 PM PDT 24 34168627 ps
T2156 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3327796201 Mar 12 12:46:13 PM PDT 24 Mar 12 12:46:34 PM PDT 24 779374431 ps
T2157 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.562837973 Mar 12 12:59:57 PM PDT 24 Mar 12 12:59:58 PM PDT 24 13838042 ps
T2158 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3105958716 Mar 12 12:46:08 PM PDT 24 Mar 12 12:46:12 PM PDT 24 58487017 ps
T2159 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3419447894 Mar 12 12:59:24 PM PDT 24 Mar 12 12:59:26 PM PDT 24 119693818 ps
T2160 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3437591757 Mar 12 12:46:08 PM PDT 24 Mar 12 12:46:14 PM PDT 24 386555772 ps
T2161 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1614045827 Mar 12 12:59:48 PM PDT 24 Mar 12 12:59:48 PM PDT 24 27926170 ps
T2162 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.46498779 Mar 12 12:45:57 PM PDT 24 Mar 12 12:46:10 PM PDT 24 738884764 ps
T2163 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3703647930 Mar 12 12:46:12 PM PDT 24 Mar 12 12:46:18 PM PDT 24 1050470584 ps
T2164 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2770423454 Mar 12 12:46:01 PM PDT 24 Mar 12 12:46:10 PM PDT 24 810043826 ps
T2165 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1431409627 Mar 12 12:45:55 PM PDT 24 Mar 12 12:45:56 PM PDT 24 173982212 ps
T2166 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.508714266 Mar 12 12:45:49 PM PDT 24 Mar 12 12:45:52 PM PDT 24 47323611 ps
T2167 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1439539554 Mar 12 12:59:14 PM PDT 24 Mar 12 12:59:16 PM PDT 24 24780112 ps
T2168 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.263935152 Mar 12 12:59:11 PM PDT 24 Mar 12 12:59:12 PM PDT 24 12124473 ps
T2169 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3362775269 Mar 12 12:59:46 PM PDT 24 Mar 12 12:59:49 PM PDT 24 485395345 ps
T2170 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1713612492 Mar 12 12:45:47 PM PDT 24 Mar 12 12:46:03 PM PDT 24 817450395 ps
T2171 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2270195698 Mar 12 12:59:47 PM PDT 24 Mar 12 12:59:51 PM PDT 24 41215022 ps
T2172 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3110004081 Mar 12 12:59:13 PM PDT 24 Mar 12 12:59:37 PM PDT 24 1896544679 ps
T2173 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.4165162564 Mar 12 12:46:07 PM PDT 24 Mar 12 12:46:12 PM PDT 24 123809256 ps
T2174 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2733693030 Mar 12 12:45:57 PM PDT 24 Mar 12 12:45:58 PM PDT 24 19995271 ps
T2175 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.290805600 Mar 12 12:45:47 PM PDT 24 Mar 12 12:45:50 PM PDT 24 47792813 ps
T2176 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2949750685 Mar 12 12:45:57 PM PDT 24 Mar 12 12:46:04 PM PDT 24 491878187 ps
T2177 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2443871075 Mar 12 12:45:56 PM PDT 24 Mar 12 12:46:11 PM PDT 24 206602227 ps
T2178 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3576543271 Mar 12 12:45:56 PM PDT 24 Mar 12 12:45:58 PM PDT 24 29457232 ps
T2179 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.15578385 Mar 12 12:46:02 PM PDT 24 Mar 12 12:46:05 PM PDT 24 598787513 ps
T2180 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1023465509 Mar 12 12:45:55 PM PDT 24 Mar 12 12:46:10 PM PDT 24 1780197430 ps
T2181 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3243300794 Mar 12 12:59:36 PM PDT 24 Mar 12 12:59:40 PM PDT 24 2620772040 ps
T2182 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3979115179 Mar 12 12:59:31 PM PDT 24 Mar 12 12:59:34 PM PDT 24 180641667 ps
T2183 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.531862051 Mar 12 12:46:23 PM PDT 24 Mar 12 12:46:24 PM PDT 24 35171920 ps
T2184 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.905175557 Mar 12 12:46:18 PM PDT 24 Mar 12 12:46:22 PM PDT 24 150336412 ps
T2185 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.764111108 Mar 12 12:46:12 PM PDT 24 Mar 12 12:46:15 PM PDT 24 33881047 ps
T2186 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2646792953 Mar 12 12:59:21 PM PDT 24 Mar 12 12:59:22 PM PDT 24 26146336 ps
T2187 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3885904405 Mar 12 12:46:06 PM PDT 24 Mar 12 12:46:09 PM PDT 24 30770540 ps
T2188 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2374642295 Mar 12 12:46:06 PM PDT 24 Mar 12 12:46:11 PM PDT 24 137328285 ps
T2189 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.4080427529 Mar 12 12:59:39 PM PDT 24 Mar 12 12:59:54 PM PDT 24 608728329 ps
T2190 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.636558813 Mar 12 12:45:56 PM PDT 24 Mar 12 12:45:57 PM PDT 24 10678124 ps
T2191 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1691876647 Mar 12 12:46:07 PM PDT 24 Mar 12 12:46:14 PM PDT 24 325100216 ps
T2192 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1764004891 Mar 12 12:46:25 PM PDT 24 Mar 12 12:46:26 PM PDT 24 19663110 ps
T2193 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.4269908826 Mar 12 12:59:15 PM PDT 24 Mar 12 12:59:17 PM PDT 24 46277234 ps
T2194 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1854435754 Mar 12 12:59:26 PM PDT 24 Mar 12 12:59:39 PM PDT 24 224669482 ps
T2195 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4112856623 Mar 12 12:59:42 PM PDT 24 Mar 12 12:59:46 PM PDT 24 144570914 ps
T2196 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.240518321 Mar 12 12:59:16 PM PDT 24 Mar 12 12:59:19 PM PDT 24 84311478 ps
T2197 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1451882194 Mar 12 12:46:07 PM PDT 24 Mar 12 12:46:10 PM PDT 24 49446235 ps
T2198 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1731431087 Mar 12 12:45:53 PM PDT 24 Mar 12 12:46:02 PM PDT 24 1127681225 ps
T2199 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.426811450 Mar 12 12:59:38 PM PDT 24 Mar 12 12:59:39 PM PDT 24 26055767 ps
T2200 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.215101306 Mar 12 12:46:09 PM PDT 24 Mar 12 12:46:13 PM PDT 24 73110135 ps
T2201 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.459394285 Mar 12 12:59:49 PM PDT 24 Mar 12 12:59:51 PM PDT 24 14165087 ps
T2202 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2128471210 Mar 12 12:46:24 PM PDT 24 Mar 12 12:46:25 PM PDT 24 118013992 ps
T2203 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1838275555 Mar 12 12:45:47 PM PDT 24 Mar 12 12:45:48 PM PDT 24 27502340 ps
T2204 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2274799618 Mar 12 12:45:56 PM PDT 24 Mar 12 12:45:59 PM PDT 24 81303572 ps
T2205 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.4192764280 Mar 12 12:59:46 PM PDT 24 Mar 12 12:59:58 PM PDT 24 196787306 ps
T2206 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3744312138 Mar 12 12:59:30 PM PDT 24 Mar 12 12:59:54 PM PDT 24 1238629823 ps
T2207 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3658863099 Mar 12 12:59:52 PM PDT 24 Mar 12 12:59:54 PM PDT 24 23393387 ps
T2208 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.909773363 Mar 12 12:46:14 PM PDT 24 Mar 12 12:46:17 PM PDT 24 296884463 ps
T2209 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1007298249 Mar 12 12:46:24 PM PDT 24 Mar 12 12:46:26 PM PDT 24 32162421 ps
T2210 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.928453197 Mar 12 12:46:07 PM PDT 24 Mar 12 12:46:10 PM PDT 24 15435949 ps
T2211 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1877006913 Mar 12 12:46:12 PM PDT 24 Mar 12 12:46:17 PM PDT 24 142024603 ps
T2212 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2483506666 Mar 12 01:01:36 PM PDT 24 Mar 12 01:01:39 PM PDT 24 42712854 ps
T2213 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1974279352 Mar 12 12:46:28 PM PDT 24 Mar 12 12:46:31 PM PDT 24 130238852 ps
T2214 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.358349679 Mar 12 12:46:25 PM PDT 24 Mar 12 12:46:27 PM PDT 24 42448242 ps
T2215 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2822698478 Mar 12 12:45:57 PM PDT 24 Mar 12 12:46:00 PM PDT 24 378377619 ps
T2216 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2912680346 Mar 12 12:46:05 PM PDT 24 Mar 12 12:46:07 PM PDT 24 56199535 ps
T2217 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2404779825 Mar 12 12:45:59 PM PDT 24 Mar 12 12:46:02 PM PDT 24 280692807 ps
T2218 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.144767668 Mar 12 12:46:19 PM PDT 24 Mar 12 12:46:21 PM PDT 24 104709059 ps
T2219 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2102986573 Mar 12 12:46:13 PM PDT 24 Mar 12 12:46:17 PM PDT 24 186461771 ps
T2220 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.891862686 Mar 12 12:59:23 PM PDT 24 Mar 12 12:59:23 PM PDT 24 30142373 ps
T2221 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3124150646 Mar 12 12:46:06 PM PDT 24 Mar 12 12:46:21 PM PDT 24 579301479 ps
T2222 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.598601892 Mar 12 12:59:29 PM PDT 24 Mar 12 12:59:33 PM PDT 24 57296041 ps
T2223 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3611957391 Mar 12 12:59:31 PM PDT 24 Mar 12 12:59:35 PM PDT 24 174211276 ps
T2224 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.567946939 Mar 12 12:45:50 PM PDT 24 Mar 12 12:45:54 PM PDT 24 111538100 ps
T2225 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.104333255 Mar 12 12:46:09 PM PDT 24 Mar 12 12:46:14 PM PDT 24 243999465 ps

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2988467043
Short name T5
Test name
Test status
Simulation time 278587079111 ps
CPU time 299.59 seconds
Started Mar 12 01:11:20 PM PDT 24
Finished Mar 12 01:16:20 PM PDT 24
Peak memory 255488 kb
Host smart-63f9ccb9-7057-4cfd-91b2-42c7e4202e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988467043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2988467043
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3186133423
Short name T14
Test name
Test status
Simulation time 12920815813 ps
CPU time 26.96 seconds
Started Mar 12 01:11:50 PM PDT 24
Finished Mar 12 01:12:17 PM PDT 24
Peak memory 216132 kb
Host smart-599f4506-ff21-4d02-aef3-f2ea073feeab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186133423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3186133423
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.4011644015
Short name T36
Test name
Test status
Simulation time 34680780463 ps
CPU time 362.91 seconds
Started Mar 12 03:07:20 PM PDT 24
Finished Mar 12 03:13:24 PM PDT 24
Peak memory 281356 kb
Host smart-0f1b7db7-389b-4f58-af4b-0e614465f497
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011644015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.4011644015
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2062926390
Short name T8
Test name
Test status
Simulation time 257465917 ps
CPU time 4.83 seconds
Started Mar 12 03:06:20 PM PDT 24
Finished Mar 12 03:06:25 PM PDT 24
Peak memory 233352 kb
Host smart-8ada5bbe-9864-46de-9db7-639d2bded663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062926390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2062926390
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3250411003
Short name T23
Test name
Test status
Simulation time 451616850514 ps
CPU time 517.96 seconds
Started Mar 12 01:11:46 PM PDT 24
Finished Mar 12 01:20:25 PM PDT 24
Peak memory 285876 kb
Host smart-78a6e0c4-a917-42ed-b517-380c63f3a62b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250411003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3250411003
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1676868505
Short name T93
Test name
Test status
Simulation time 510644495 ps
CPU time 3.67 seconds
Started Mar 12 12:46:24 PM PDT 24
Finished Mar 12 12:46:29 PM PDT 24
Peak memory 215560 kb
Host smart-ef668944-1ff5-4e0b-8378-4d34ab71c7c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676868505 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1676868505
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.4263027643
Short name T17
Test name
Test status
Simulation time 244723194556 ps
CPU time 398.63 seconds
Started Mar 12 03:08:15 PM PDT 24
Finished Mar 12 03:14:54 PM PDT 24
Peak memory 249004 kb
Host smart-8128bb87-631e-423b-971c-d9ba96319dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263027643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.4263027643
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.3563656212
Short name T345
Test name
Test status
Simulation time 17342127 ps
CPU time 0.77 seconds
Started Mar 12 03:04:58 PM PDT 24
Finished Mar 12 03:05:01 PM PDT 24
Peak memory 215944 kb
Host smart-d98d3477-0338-4640-b0ed-aed2de6e0841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563656212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.3563656212
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1685698310
Short name T35
Test name
Test status
Simulation time 28206129892 ps
CPU time 164.68 seconds
Started Mar 12 01:11:12 PM PDT 24
Finished Mar 12 01:13:57 PM PDT 24
Peak memory 268624 kb
Host smart-8c2a9fa3-bbc3-476c-8f53-90733757363d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685698310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1685698310
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.858654486
Short name T61
Test name
Test status
Simulation time 182086825 ps
CPU time 1.2 seconds
Started Mar 12 03:05:11 PM PDT 24
Finished Mar 12 03:05:12 PM PDT 24
Peak memory 235232 kb
Host smart-d7270386-7119-4fe9-a0c3-4fe2b8c4a9d1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858654486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.858654486
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.4037338988
Short name T187
Test name
Test status
Simulation time 107782793450 ps
CPU time 545.7 seconds
Started Mar 12 01:11:17 PM PDT 24
Finished Mar 12 01:20:22 PM PDT 24
Peak memory 305292 kb
Host smart-d641269a-d2b0-435f-8bcb-3ba82688d69c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037338988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.4037338988
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2570636592
Short name T46
Test name
Test status
Simulation time 4048667989 ps
CPU time 81.16 seconds
Started Mar 12 01:11:31 PM PDT 24
Finished Mar 12 01:12:54 PM PDT 24
Peak memory 265824 kb
Host smart-73c5a367-8a6b-4588-bddb-c30f6e1f51ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570636592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2570636592
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3277302078
Short name T145
Test name
Test status
Simulation time 14360271557 ps
CPU time 26.13 seconds
Started Mar 12 01:10:16 PM PDT 24
Finished Mar 12 01:10:43 PM PDT 24
Peak memory 232328 kb
Host smart-19a6f044-712a-40cd-8843-e33dd8e666b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277302078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3277302078
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3074885991
Short name T25
Test name
Test status
Simulation time 870301159372 ps
CPU time 715.24 seconds
Started Mar 12 03:06:29 PM PDT 24
Finished Mar 12 03:18:25 PM PDT 24
Peak memory 272804 kb
Host smart-1cfb7d66-498d-493b-a6ac-e8037e077402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074885991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3074885991
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1381096078
Short name T181
Test name
Test status
Simulation time 4015592389 ps
CPU time 25.52 seconds
Started Mar 12 12:59:44 PM PDT 24
Finished Mar 12 01:00:09 PM PDT 24
Peak memory 215280 kb
Host smart-aab3317e-921d-4eba-8621-b3729e48bd88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381096078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1381096078
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.50701314
Short name T154
Test name
Test status
Simulation time 112544493634 ps
CPU time 247.08 seconds
Started Mar 12 03:09:07 PM PDT 24
Finished Mar 12 03:13:14 PM PDT 24
Peak memory 272940 kb
Host smart-7f1fa941-a334-4834-9c86-e2d467f1d4da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50701314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stress
_all.50701314
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1513173484
Short name T122
Test name
Test status
Simulation time 73610935 ps
CPU time 2.43 seconds
Started Mar 12 12:46:10 PM PDT 24
Finished Mar 12 12:46:15 PM PDT 24
Peak memory 215328 kb
Host smart-535e0513-977f-4ddc-9bbb-e17071bbc9ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513173484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1513173484
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3670949461
Short name T103
Test name
Test status
Simulation time 383870454 ps
CPU time 4.71 seconds
Started Mar 12 12:59:38 PM PDT 24
Finished Mar 12 12:59:43 PM PDT 24
Peak memory 215436 kb
Host smart-1ae3da31-eb7e-4c4c-83e3-6f3d6094d374
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670949461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3670949461
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.1237567165
Short name T26
Test name
Test status
Simulation time 89009876 ps
CPU time 1.05 seconds
Started Mar 12 03:04:42 PM PDT 24
Finished Mar 12 03:04:43 PM PDT 24
Peak memory 217608 kb
Host smart-f0b683a3-e472-4383-a645-09122f411469
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237567165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.1237567165
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1559629095
Short name T138
Test name
Test status
Simulation time 773214803278 ps
CPU time 465.66 seconds
Started Mar 12 01:12:48 PM PDT 24
Finished Mar 12 01:20:34 PM PDT 24
Peak memory 273412 kb
Host smart-b1c4142b-83ad-479f-a93e-e66d52b4f717
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559629095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1559629095
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.901934478
Short name T280
Test name
Test status
Simulation time 353367858094 ps
CPU time 824.84 seconds
Started Mar 12 01:12:43 PM PDT 24
Finished Mar 12 01:26:29 PM PDT 24
Peak memory 322528 kb
Host smart-f51d906b-ad10-4364-99c3-3ae37bd78976
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901934478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.901934478
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1293157944
Short name T223
Test name
Test status
Simulation time 159355136155 ps
CPU time 560.23 seconds
Started Mar 12 03:09:59 PM PDT 24
Finished Mar 12 03:19:20 PM PDT 24
Peak memory 250844 kb
Host smart-55046311-add8-41fb-8b78-81bd1720f832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293157944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1293157944
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.1403951080
Short name T305
Test name
Test status
Simulation time 517939757640 ps
CPU time 776.42 seconds
Started Mar 12 01:12:43 PM PDT 24
Finished Mar 12 01:25:39 PM PDT 24
Peak memory 286312 kb
Host smart-c63e6885-8580-4330-8f39-f0f05b609a90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403951080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.1403951080
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.394946477
Short name T37
Test name
Test status
Simulation time 99935736056 ps
CPU time 485.11 seconds
Started Mar 12 03:09:17 PM PDT 24
Finished Mar 12 03:17:22 PM PDT 24
Peak memory 271068 kb
Host smart-d3a4e202-d2c5-44e7-91e1-98ddebd884ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394946477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.394946477
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2951604840
Short name T60
Test name
Test status
Simulation time 58198390 ps
CPU time 0.76 seconds
Started Mar 12 03:05:30 PM PDT 24
Finished Mar 12 03:05:35 PM PDT 24
Peak memory 204188 kb
Host smart-5567d96c-2f0c-4a7f-97bf-fde2088924af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951604840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
951604840
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2606973116
Short name T98
Test name
Test status
Simulation time 163788608 ps
CPU time 3.48 seconds
Started Mar 12 12:59:17 PM PDT 24
Finished Mar 12 12:59:21 PM PDT 24
Peak memory 216520 kb
Host smart-a75718d7-706c-4d11-b6a1-47c296ce8dc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606973116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
606973116
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1155533780
Short name T316
Test name
Test status
Simulation time 8238656721 ps
CPU time 41.26 seconds
Started Mar 12 03:06:51 PM PDT 24
Finished Mar 12 03:07:32 PM PDT 24
Peak memory 215980 kb
Host smart-ed917572-f848-4ab6-ab7a-fd41984bc011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155533780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1155533780
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.646420242
Short name T302
Test name
Test status
Simulation time 153196781657 ps
CPU time 263.01 seconds
Started Mar 12 03:09:24 PM PDT 24
Finished Mar 12 03:13:48 PM PDT 24
Peak memory 249488 kb
Host smart-3456fc55-211e-424e-b195-5c4a7b78eab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646420242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle
.646420242
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.713029152
Short name T1112
Test name
Test status
Simulation time 77066981701 ps
CPU time 217.54 seconds
Started Mar 12 03:09:58 PM PDT 24
Finished Mar 12 03:13:35 PM PDT 24
Peak memory 272168 kb
Host smart-4c7349dd-2085-4b35-98e5-2f61da78e757
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713029152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.713029152
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.79791781
Short name T2084
Test name
Test status
Simulation time 559229137 ps
CPU time 13.97 seconds
Started Mar 12 12:45:46 PM PDT 24
Finished Mar 12 12:46:00 PM PDT 24
Peak memory 215368 kb
Host smart-004cbea9-d0d0-45be-81d3-659394af47d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79791781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_t
l_intg_err.79791781
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1756150484
Short name T288
Test name
Test status
Simulation time 77629256041 ps
CPU time 371.02 seconds
Started Mar 12 01:11:32 PM PDT 24
Finished Mar 12 01:17:44 PM PDT 24
Peak memory 265004 kb
Host smart-6dc1474a-1d18-4d68-840e-0e76a19209f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756150484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1756150484
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1620320628
Short name T1649
Test name
Test status
Simulation time 38795763390 ps
CPU time 220.13 seconds
Started Mar 12 03:11:02 PM PDT 24
Finished Mar 12 03:14:42 PM PDT 24
Peak memory 256628 kb
Host smart-cc9b7577-8460-4b48-8435-6dda3a575cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620320628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1620320628
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1844760799
Short name T290
Test name
Test status
Simulation time 240661536849 ps
CPU time 389.65 seconds
Started Mar 12 03:11:02 PM PDT 24
Finished Mar 12 03:17:32 PM PDT 24
Peak memory 258276 kb
Host smart-14e1bbd6-675b-40cc-b96e-bed8ee86f41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844760799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1844760799
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3944258445
Short name T148
Test name
Test status
Simulation time 25442901865 ps
CPU time 64.45 seconds
Started Mar 12 01:13:03 PM PDT 24
Finished Mar 12 01:14:08 PM PDT 24
Peak memory 249476 kb
Host smart-749b9dce-f6f4-4b12-960b-358f9024fbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944258445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3944258445
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.4093548931
Short name T180
Test name
Test status
Simulation time 772620647 ps
CPU time 20.24 seconds
Started Mar 12 12:59:32 PM PDT 24
Finished Mar 12 12:59:52 PM PDT 24
Peak memory 216028 kb
Host smart-47847db1-00d1-446c-b1e4-6508ff3c6a32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093548931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.4093548931
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2375973792
Short name T308
Test name
Test status
Simulation time 117735007729 ps
CPU time 175.44 seconds
Started Mar 12 03:04:51 PM PDT 24
Finished Mar 12 03:07:47 PM PDT 24
Peak memory 271172 kb
Host smart-ba37bc64-051e-44e5-b9f2-b6fb8e84e602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375973792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2375973792
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1472554182
Short name T297
Test name
Test status
Simulation time 59322026953 ps
CPU time 304.62 seconds
Started Mar 12 01:12:45 PM PDT 24
Finished Mar 12 01:17:50 PM PDT 24
Peak memory 270348 kb
Host smart-3f139b9e-bda3-4c29-b414-b5024e89561f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472554182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1472554182
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2361005093
Short name T82
Test name
Test status
Simulation time 23286609432 ps
CPU time 52.68 seconds
Started Mar 12 03:08:14 PM PDT 24
Finished Mar 12 03:09:08 PM PDT 24
Peak memory 216032 kb
Host smart-3fa9723f-8768-4510-aef5-f67805f4c30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361005093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2361005093
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_upload.302216428
Short name T22
Test name
Test status
Simulation time 2259565485 ps
CPU time 6.77 seconds
Started Mar 12 03:07:06 PM PDT 24
Finished Mar 12 03:07:13 PM PDT 24
Peak memory 234668 kb
Host smart-50c67d48-ea82-4a73-b101-44cb2f60a21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302216428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.302216428
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2106969100
Short name T173
Test name
Test status
Simulation time 629360962 ps
CPU time 3.94 seconds
Started Mar 12 12:59:49 PM PDT 24
Finished Mar 12 12:59:53 PM PDT 24
Peak memory 215512 kb
Host smart-a1304c7b-9f30-4bab-afb7-58563305f7f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106969100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2106969100
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3953119726
Short name T139
Test name
Test status
Simulation time 6597231734 ps
CPU time 70.28 seconds
Started Mar 12 03:04:54 PM PDT 24
Finished Mar 12 03:06:05 PM PDT 24
Peak memory 250680 kb
Host smart-509b46d3-adf8-46f8-ac10-65149ac80fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953119726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3953119726
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.974318296
Short name T1651
Test name
Test status
Simulation time 25145423886 ps
CPU time 142.35 seconds
Started Mar 12 03:06:46 PM PDT 24
Finished Mar 12 03:09:09 PM PDT 24
Peak memory 265364 kb
Host smart-a9789a85-238a-406e-ad95-ffd90fd4e49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974318296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.974318296
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1717100386
Short name T80
Test name
Test status
Simulation time 14612180 ps
CPU time 0.95 seconds
Started Mar 12 12:45:51 PM PDT 24
Finished Mar 12 12:45:52 PM PDT 24
Peak memory 206636 kb
Host smart-87549092-da0b-4cac-bb21-d524f8d1266f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717100386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1717100386
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2935605208
Short name T92
Test name
Test status
Simulation time 9955188034 ps
CPU time 114.67 seconds
Started Mar 12 01:11:19 PM PDT 24
Finished Mar 12 01:13:14 PM PDT 24
Peak memory 254772 kb
Host smart-2d0bda7c-c654-4bba-a480-c76f4e5f5ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935605208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2935605208
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.435669765
Short name T109
Test name
Test status
Simulation time 915601522 ps
CPU time 1.81 seconds
Started Mar 12 12:59:18 PM PDT 24
Finished Mar 12 12:59:20 PM PDT 24
Peak memory 215492 kb
Host smart-f67d5172-5c07-443a-8de1-ce337c24c3e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435669765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.435669765
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1713612492
Short name T2170
Test name
Test status
Simulation time 817450395 ps
CPU time 16.81 seconds
Started Mar 12 12:45:47 PM PDT 24
Finished Mar 12 12:46:03 PM PDT 24
Peak memory 207136 kb
Host smart-3172f278-4d19-4ab6-b7d3-aa44d7176960
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713612492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1713612492
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3110004081
Short name T2172
Test name
Test status
Simulation time 1896544679 ps
CPU time 23.93 seconds
Started Mar 12 12:59:13 PM PDT 24
Finished Mar 12 12:59:37 PM PDT 24
Peak memory 215332 kb
Host smart-a801da10-cc64-42ab-a90b-4b1ed77b8a85
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110004081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3110004081
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1834189435
Short name T1987
Test name
Test status
Simulation time 6719807350 ps
CPU time 37.4 seconds
Started Mar 12 12:45:45 PM PDT 24
Finished Mar 12 12:46:23 PM PDT 24
Peak memory 207140 kb
Host smart-655249ff-ab73-4aca-a60c-28cc5397d90f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834189435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1834189435
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3117419218
Short name T2112
Test name
Test status
Simulation time 1070153792 ps
CPU time 33.92 seconds
Started Mar 12 12:59:17 PM PDT 24
Finished Mar 12 12:59:51 PM PDT 24
Peak memory 206964 kb
Host smart-a3c5165a-b61f-4481-a581-72fb93884230
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117419218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3117419218
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2023363875
Short name T76
Test name
Test status
Simulation time 114469471 ps
CPU time 0.98 seconds
Started Mar 12 12:59:09 PM PDT 24
Finished Mar 12 12:59:10 PM PDT 24
Peak memory 206732 kb
Host smart-6973465a-121b-462e-afdd-cde06f5eb067
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023363875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2023363875
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4064891542
Short name T107
Test name
Test status
Simulation time 81625108 ps
CPU time 2.92 seconds
Started Mar 12 12:59:14 PM PDT 24
Finished Mar 12 12:59:17 PM PDT 24
Peak memory 217260 kb
Host smart-c10153c9-ba6e-439e-9dcd-6a808f8ef66d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064891542 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.4064891542
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.567946939
Short name T2224
Test name
Test status
Simulation time 111538100 ps
CPU time 3.77 seconds
Started Mar 12 12:45:50 PM PDT 24
Finished Mar 12 12:45:54 PM PDT 24
Peak memory 216956 kb
Host smart-4f3e5b11-7c2f-4faa-8d9c-b32a2ecdc16b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567946939 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.567946939
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1251995141
Short name T2096
Test name
Test status
Simulation time 806114044 ps
CPU time 1.35 seconds
Started Mar 12 12:45:51 PM PDT 24
Finished Mar 12 12:45:52 PM PDT 24
Peak memory 206988 kb
Host smart-48e2144b-e8b9-4364-b765-e8327d44c0bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251995141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
251995141
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2927793090
Short name T1961
Test name
Test status
Simulation time 19607899 ps
CPU time 1.28 seconds
Started Mar 12 12:59:13 PM PDT 24
Finished Mar 12 12:59:14 PM PDT 24
Peak memory 207156 kb
Host smart-838fe9d1-bf85-4a51-9a29-3109672cb6cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927793090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
927793090
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2191026952
Short name T1997
Test name
Test status
Simulation time 35985761 ps
CPU time 0.73 seconds
Started Mar 12 12:59:15 PM PDT 24
Finished Mar 12 12:59:16 PM PDT 24
Peak memory 203428 kb
Host smart-dcb3d5e6-4e8f-4615-9646-300139ad15f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191026952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
191026952
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.539930677
Short name T1976
Test name
Test status
Simulation time 32079844 ps
CPU time 0.69 seconds
Started Mar 12 12:45:46 PM PDT 24
Finished Mar 12 12:45:47 PM PDT 24
Peak memory 203416 kb
Host smart-f7e2e64f-e505-4b41-af9d-a379b077a471
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539930677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.539930677
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2031587353
Short name T2113
Test name
Test status
Simulation time 125329779 ps
CPU time 1.25 seconds
Started Mar 12 12:45:48 PM PDT 24
Finished Mar 12 12:45:49 PM PDT 24
Peak memory 215052 kb
Host smart-1ea5d331-6126-4db9-b9e9-a2aee66dd9f4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031587353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2031587353
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3941753643
Short name T126
Test name
Test status
Simulation time 49088407 ps
CPU time 1.81 seconds
Started Mar 12 12:59:10 PM PDT 24
Finished Mar 12 12:59:12 PM PDT 24
Peak memory 215376 kb
Host smart-77ef9fe4-a3c2-44d7-8dbc-d12a19c15de3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941753643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3941753643
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1838275555
Short name T2203
Test name
Test status
Simulation time 27502340 ps
CPU time 0.65 seconds
Started Mar 12 12:45:47 PM PDT 24
Finished Mar 12 12:45:48 PM PDT 24
Peak memory 203332 kb
Host smart-a15e8a75-2cea-4588-8c62-4efc70565cef
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838275555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1838275555
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3383350160
Short name T1964
Test name
Test status
Simulation time 11355319 ps
CPU time 0.68 seconds
Started Mar 12 12:59:13 PM PDT 24
Finished Mar 12 12:59:14 PM PDT 24
Peak memory 203328 kb
Host smart-4ec4fb41-2515-429d-8669-8d25549569b8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383350160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3383350160
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1428144605
Short name T150
Test name
Test status
Simulation time 541091275 ps
CPU time 3.08 seconds
Started Mar 12 12:59:17 PM PDT 24
Finished Mar 12 12:59:20 PM PDT 24
Peak memory 215116 kb
Host smart-12852fbd-bae6-4148-9c05-8a25964f6a14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428144605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1428144605
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1957172938
Short name T1969
Test name
Test status
Simulation time 165961271 ps
CPU time 2.81 seconds
Started Mar 12 12:45:49 PM PDT 24
Finished Mar 12 12:45:52 PM PDT 24
Peak memory 215300 kb
Host smart-ff68d408-195e-45bc-8edb-b9d646033b6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957172938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1957172938
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.290805600
Short name T2175
Test name
Test status
Simulation time 47792813 ps
CPU time 3.2 seconds
Started Mar 12 12:45:47 PM PDT 24
Finished Mar 12 12:45:50 PM PDT 24
Peak memory 215708 kb
Host smart-e4336cb1-2ca4-4b15-88a9-d3081b74624c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290805600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.290805600
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2438580109
Short name T178
Test name
Test status
Simulation time 1140719513 ps
CPU time 14.72 seconds
Started Mar 12 01:01:34 PM PDT 24
Finished Mar 12 01:01:49 PM PDT 24
Peak memory 215136 kb
Host smart-965d3203-155f-4ee7-a03e-5bb3287e4f0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438580109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2438580109
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1805923111
Short name T2127
Test name
Test status
Simulation time 10005875405 ps
CPU time 23.5 seconds
Started Mar 12 12:45:51 PM PDT 24
Finished Mar 12 12:46:14 PM PDT 24
Peak memory 215388 kb
Host smart-edda4d38-6b79-4954-9a24-39dfcd6ec1a9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805923111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1805923111
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3744312138
Short name T2206
Test name
Test status
Simulation time 1238629823 ps
CPU time 23.81 seconds
Started Mar 12 12:59:30 PM PDT 24
Finished Mar 12 12:59:54 PM PDT 24
Peak memory 215384 kb
Host smart-907d5539-ea3d-45e4-bef2-795f16328ca5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744312138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3744312138
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1900862272
Short name T132
Test name
Test status
Simulation time 365870955 ps
CPU time 21.84 seconds
Started Mar 12 12:45:51 PM PDT 24
Finished Mar 12 12:46:13 PM PDT 24
Peak memory 206752 kb
Host smart-bbbf2ef3-4ad6-4a70-893c-8f89d1fcae99
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900862272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1900862272
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3145514311
Short name T121
Test name
Test status
Simulation time 16399073117 ps
CPU time 27.12 seconds
Started Mar 12 12:59:29 PM PDT 24
Finished Mar 12 12:59:56 PM PDT 24
Peak memory 207196 kb
Host smart-8c5cf9af-1b8b-4c93-9bc3-3bbd14b611d5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145514311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3145514311
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1061590898
Short name T81
Test name
Test status
Simulation time 18031503 ps
CPU time 0.93 seconds
Started Mar 12 12:59:14 PM PDT 24
Finished Mar 12 12:59:15 PM PDT 24
Peak memory 206552 kb
Host smart-3790782e-e45b-46f5-9534-5606959a59d8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061590898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1061590898
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.129711945
Short name T79
Test name
Test status
Simulation time 125805952 ps
CPU time 1.22 seconds
Started Mar 12 12:45:53 PM PDT 24
Finished Mar 12 12:45:55 PM PDT 24
Peak memory 206720 kb
Host smart-c8f66180-9543-4068-9c2f-301ca02e255e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129711945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.129711945
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.438888291
Short name T96
Test name
Test status
Simulation time 116566764 ps
CPU time 2.93 seconds
Started Mar 12 12:59:14 PM PDT 24
Finished Mar 12 12:59:17 PM PDT 24
Peak memory 216916 kb
Host smart-cfb7997c-37d8-407c-9b0c-b068098eb35c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438888291 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.438888291
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.835692069
Short name T111
Test name
Test status
Simulation time 199084426 ps
CPU time 3.48 seconds
Started Mar 12 12:45:46 PM PDT 24
Finished Mar 12 12:45:49 PM PDT 24
Peak memory 216668 kb
Host smart-f7890d0c-4c9f-4d49-9264-28ae0d283edb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835692069 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.835692069
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1461261511
Short name T2145
Test name
Test status
Simulation time 214012992 ps
CPU time 2.62 seconds
Started Mar 12 12:45:48 PM PDT 24
Finished Mar 12 12:45:50 PM PDT 24
Peak memory 215320 kb
Host smart-b0b9031e-48f6-488b-93bb-2840ed709893
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461261511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
461261511
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.686658945
Short name T2124
Test name
Test status
Simulation time 51280634 ps
CPU time 1.77 seconds
Started Mar 12 12:59:26 PM PDT 24
Finished Mar 12 12:59:28 PM PDT 24
Peak memory 215308 kb
Host smart-0c10d65b-ea19-450a-b427-7e9885db859f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686658945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.686658945
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1400071159
Short name T1981
Test name
Test status
Simulation time 36509723 ps
CPU time 0.75 seconds
Started Mar 12 12:45:51 PM PDT 24
Finished Mar 12 12:45:52 PM PDT 24
Peak memory 203388 kb
Host smart-ea5d6b25-35ce-4fd1-b48e-00e3c29602b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400071159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
400071159
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3910141517
Short name T2136
Test name
Test status
Simulation time 24751897 ps
CPU time 0.71 seconds
Started Mar 12 12:59:14 PM PDT 24
Finished Mar 12 12:59:15 PM PDT 24
Peak memory 202848 kb
Host smart-263b71fd-392e-42d0-a217-2f89ce5a6220
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910141517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
910141517
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1439539554
Short name T2167
Test name
Test status
Simulation time 24780112 ps
CPU time 1.47 seconds
Started Mar 12 12:59:14 PM PDT 24
Finished Mar 12 12:59:16 PM PDT 24
Peak memory 214676 kb
Host smart-47cd988d-dadd-46f3-9182-e6932a99bce6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439539554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1439539554
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.973206104
Short name T2037
Test name
Test status
Simulation time 19585106 ps
CPU time 1.22 seconds
Started Mar 12 12:46:02 PM PDT 24
Finished Mar 12 12:46:04 PM PDT 24
Peak memory 215316 kb
Host smart-e6dd7888-1742-4add-b5b9-612deb03046a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973206104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.973206104
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1739068650
Short name T2044
Test name
Test status
Simulation time 15090749 ps
CPU time 0.68 seconds
Started Mar 12 12:59:14 PM PDT 24
Finished Mar 12 12:59:15 PM PDT 24
Peak memory 203352 kb
Host smart-bb3dee30-f888-4f8c-b859-c401755d0671
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739068650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.1739068650
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.420166980
Short name T2042
Test name
Test status
Simulation time 11963290 ps
CPU time 0.69 seconds
Started Mar 12 12:45:51 PM PDT 24
Finished Mar 12 12:45:51 PM PDT 24
Peak memory 203296 kb
Host smart-dd94de3f-aad0-403f-bb75-743fa10117f9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420166980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.420166980
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3915283036
Short name T2059
Test name
Test status
Simulation time 133168032 ps
CPU time 1.63 seconds
Started Mar 12 12:45:48 PM PDT 24
Finished Mar 12 12:45:50 PM PDT 24
Peak memory 207048 kb
Host smart-263b276d-b8aa-4d96-8743-477d9fee0962
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915283036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3915283036
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.4269908826
Short name T2193
Test name
Test status
Simulation time 46277234 ps
CPU time 1.79 seconds
Started Mar 12 12:59:15 PM PDT 24
Finished Mar 12 12:59:17 PM PDT 24
Peak memory 215280 kb
Host smart-7743fac4-fde5-40c4-b911-68dc5fdcc4f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269908826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.4269908826
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1062197410
Short name T2023
Test name
Test status
Simulation time 84489168 ps
CPU time 1.83 seconds
Started Mar 12 12:59:12 PM PDT 24
Finished Mar 12 12:59:14 PM PDT 24
Peak memory 215684 kb
Host smart-858759ec-525b-4dc8-9054-066fe25723de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062197410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
062197410
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.508714266
Short name T2166
Test name
Test status
Simulation time 47323611 ps
CPU time 3.04 seconds
Started Mar 12 12:45:49 PM PDT 24
Finished Mar 12 12:45:52 PM PDT 24
Peak memory 215508 kb
Host smart-962b7621-ca2e-41d2-91fb-b0aa31332a0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508714266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.508714266
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1443477020
Short name T2022
Test name
Test status
Simulation time 534056981 ps
CPU time 14.99 seconds
Started Mar 12 12:59:24 PM PDT 24
Finished Mar 12 12:59:39 PM PDT 24
Peak memory 216504 kb
Host smart-5cd1005b-fa4e-477a-ac74-c58dc7d30274
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443477020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1443477020
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1731431087
Short name T2198
Test name
Test status
Simulation time 1127681225 ps
CPU time 8.41 seconds
Started Mar 12 12:45:53 PM PDT 24
Finished Mar 12 12:46:02 PM PDT 24
Peak memory 214908 kb
Host smart-56f8a2ac-c704-4fb4-9c92-78e6a5fcd0e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731431087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1731431087
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2800853734
Short name T2065
Test name
Test status
Simulation time 28286156 ps
CPU time 2.03 seconds
Started Mar 12 12:59:24 PM PDT 24
Finished Mar 12 12:59:26 PM PDT 24
Peak memory 215524 kb
Host smart-6af103c0-0f29-4963-a425-2898af930b8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800853734 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2800853734
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2912680346
Short name T2216
Test name
Test status
Simulation time 56199535 ps
CPU time 1.83 seconds
Started Mar 12 12:46:05 PM PDT 24
Finished Mar 12 12:46:07 PM PDT 24
Peak memory 215432 kb
Host smart-69c75e97-0d0e-4375-a1a4-c6460b506851
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912680346 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2912680346
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.215101306
Short name T2200
Test name
Test status
Simulation time 73110135 ps
CPU time 1.36 seconds
Started Mar 12 12:46:09 PM PDT 24
Finished Mar 12 12:46:13 PM PDT 24
Peak memory 207072 kb
Host smart-e14f5fbe-1624-4e2e-9b37-85406f30aa8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215101306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.215101306
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2453302173
Short name T2073
Test name
Test status
Simulation time 109423162 ps
CPU time 1.85 seconds
Started Mar 12 12:59:33 PM PDT 24
Finished Mar 12 12:59:35 PM PDT 24
Peak memory 215148 kb
Host smart-355f2e8f-b99d-4318-8ddf-6177a7398300
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453302173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2453302173
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1451882194
Short name T2197
Test name
Test status
Simulation time 49446235 ps
CPU time 0.8 seconds
Started Mar 12 12:46:07 PM PDT 24
Finished Mar 12 12:46:10 PM PDT 24
Peak memory 203504 kb
Host smart-4c8afcb2-8f04-4460-b3ce-5becb3e76795
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451882194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1451882194
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.891862686
Short name T2220
Test name
Test status
Simulation time 30142373 ps
CPU time 0.7 seconds
Started Mar 12 12:59:23 PM PDT 24
Finished Mar 12 12:59:23 PM PDT 24
Peak memory 203404 kb
Host smart-8e07162e-691d-4515-a2ef-efff99dcc898
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891862686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.891862686
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2163810257
Short name T2143
Test name
Test status
Simulation time 435949352 ps
CPU time 2.91 seconds
Started Mar 12 12:46:08 PM PDT 24
Finished Mar 12 12:46:15 PM PDT 24
Peak memory 215352 kb
Host smart-4f548b5c-802a-420d-a6f2-05fb433206de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163810257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2163810257
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.460145768
Short name T151
Test name
Test status
Simulation time 73634816 ps
CPU time 1.98 seconds
Started Mar 12 12:59:24 PM PDT 24
Finished Mar 12 12:59:26 PM PDT 24
Peak memory 215360 kb
Host smart-e3b203b4-6be9-4bc7-b02b-0ac6e2179430
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460145768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.460145768
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.224983350
Short name T2031
Test name
Test status
Simulation time 64105710 ps
CPU time 1.87 seconds
Started Mar 12 12:46:07 PM PDT 24
Finished Mar 12 12:46:10 PM PDT 24
Peak memory 215468 kb
Host smart-64a11918-769d-4643-9154-1d8fd34aa15e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224983350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.224983350
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2946819919
Short name T2053
Test name
Test status
Simulation time 371364584 ps
CPU time 3 seconds
Started Mar 12 12:59:46 PM PDT 24
Finished Mar 12 12:59:49 PM PDT 24
Peak memory 215488 kb
Host smart-764debca-0151-419b-8a1c-af5877268dc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946819919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2946819919
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3327796201
Short name T2156
Test name
Test status
Simulation time 779374431 ps
CPU time 20.13 seconds
Started Mar 12 12:46:13 PM PDT 24
Finished Mar 12 12:46:34 PM PDT 24
Peak memory 215316 kb
Host smart-9212918d-23c2-43c9-875c-e5824dd2bbe0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327796201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3327796201
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.4096022796
Short name T2004
Test name
Test status
Simulation time 207697684 ps
CPU time 3.34 seconds
Started Mar 12 12:59:16 PM PDT 24
Finished Mar 12 12:59:20 PM PDT 24
Peak memory 217120 kb
Host smart-5d055a95-04e7-4ff6-ab8d-f01203a20418
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096022796 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.4096022796
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.617838330
Short name T2105
Test name
Test status
Simulation time 83098513 ps
CPU time 3.27 seconds
Started Mar 12 12:46:11 PM PDT 24
Finished Mar 12 12:46:17 PM PDT 24
Peak memory 217508 kb
Host smart-f490001f-f08b-4dee-96c4-17e4a49090cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617838330 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.617838330
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.104333255
Short name T2225
Test name
Test status
Simulation time 243999465 ps
CPU time 1.92 seconds
Started Mar 12 12:46:09 PM PDT 24
Finished Mar 12 12:46:14 PM PDT 24
Peak memory 207080 kb
Host smart-236891bb-54d8-4dc6-bbd5-1694fe870b4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104333255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.104333255
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.756060607
Short name T2102
Test name
Test status
Simulation time 243717206 ps
CPU time 1.98 seconds
Started Mar 12 12:59:32 PM PDT 24
Finished Mar 12 12:59:34 PM PDT 24
Peak memory 215312 kb
Host smart-c2645718-bb53-4e85-b962-4fecbccb093e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756060607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.756060607
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1186711919
Short name T2099
Test name
Test status
Simulation time 12022065 ps
CPU time 0.73 seconds
Started Mar 12 12:59:25 PM PDT 24
Finished Mar 12 12:59:26 PM PDT 24
Peak memory 203440 kb
Host smart-e16d73b1-bebd-43d7-8cd5-bcbe3f8197ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186711919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1186711919
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3105958716
Short name T2158
Test name
Test status
Simulation time 58487017 ps
CPU time 0.75 seconds
Started Mar 12 12:46:08 PM PDT 24
Finished Mar 12 12:46:12 PM PDT 24
Peak memory 203408 kb
Host smart-2241a53c-72c3-4aee-83f2-ea7116eb479f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105958716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3105958716
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1691876647
Short name T2191
Test name
Test status
Simulation time 325100216 ps
CPU time 3.85 seconds
Started Mar 12 12:46:07 PM PDT 24
Finished Mar 12 12:46:14 PM PDT 24
Peak memory 215188 kb
Host smart-2a91ea9f-706c-4eed-a7d5-a6498ad9d343
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691876647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1691876647
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.976432584
Short name T2107
Test name
Test status
Simulation time 27377295 ps
CPU time 1.8 seconds
Started Mar 12 12:59:34 PM PDT 24
Finished Mar 12 12:59:36 PM PDT 24
Peak memory 207028 kb
Host smart-a9ee50b9-3fd2-4943-845b-25f079cc898a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976432584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.976432584
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3437591757
Short name T2160
Test name
Test status
Simulation time 386555772 ps
CPU time 3.15 seconds
Started Mar 12 12:46:08 PM PDT 24
Finished Mar 12 12:46:14 PM PDT 24
Peak memory 215420 kb
Host smart-8a8fe33f-e15c-486e-84d0-3e02387da309
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437591757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3437591757
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.598601892
Short name T2222
Test name
Test status
Simulation time 57296041 ps
CPU time 3.87 seconds
Started Mar 12 12:59:29 PM PDT 24
Finished Mar 12 12:59:33 PM PDT 24
Peak memory 215484 kb
Host smart-b5b7b707-0d92-40af-8222-1b30d80a74e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598601892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.598601892
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2782478642
Short name T2056
Test name
Test status
Simulation time 1739567277 ps
CPU time 7.25 seconds
Started Mar 12 12:46:08 PM PDT 24
Finished Mar 12 12:46:18 PM PDT 24
Peak memory 215172 kb
Host smart-4ccb52a7-0bb1-40c0-a5f2-3087eb69bf26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782478642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2782478642
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.731785002
Short name T97
Test name
Test status
Simulation time 324265361 ps
CPU time 7 seconds
Started Mar 12 12:59:23 PM PDT 24
Finished Mar 12 12:59:30 PM PDT 24
Peak memory 215272 kb
Host smart-21fff8a7-6328-418a-8260-743d8558ab74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731785002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.731785002
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1287697884
Short name T2010
Test name
Test status
Simulation time 39541014 ps
CPU time 2.54 seconds
Started Mar 12 12:59:20 PM PDT 24
Finished Mar 12 12:59:22 PM PDT 24
Peak memory 215688 kb
Host smart-0b548fdb-a899-45b5-b6d7-1a5c74a14c1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287697884 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1287697884
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3416434927
Short name T2137
Test name
Test status
Simulation time 367745608 ps
CPU time 2.81 seconds
Started Mar 12 12:46:12 PM PDT 24
Finished Mar 12 12:46:17 PM PDT 24
Peak memory 216560 kb
Host smart-cc1c10b5-2cc0-4f92-a773-33a97bc359c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416434927 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3416434927
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1104179319
Short name T2070
Test name
Test status
Simulation time 88281642 ps
CPU time 2.45 seconds
Started Mar 12 12:46:09 PM PDT 24
Finished Mar 12 12:46:15 PM PDT 24
Peak memory 215356 kb
Host smart-2ba4bd59-f088-413b-851b-573084270bb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104179319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1104179319
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1577682015
Short name T127
Test name
Test status
Simulation time 332473023 ps
CPU time 2.43 seconds
Started Mar 12 12:59:17 PM PDT 24
Finished Mar 12 12:59:20 PM PDT 24
Peak memory 215336 kb
Host smart-65b44d41-3e00-47c9-8916-dc51e3666186
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577682015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1577682015
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2655267033
Short name T1941
Test name
Test status
Simulation time 15276854 ps
CPU time 0.73 seconds
Started Mar 12 12:59:26 PM PDT 24
Finished Mar 12 12:59:27 PM PDT 24
Peak memory 203400 kb
Host smart-2d07b5e7-facd-4c3e-95c0-1d85b22f7187
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655267033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2655267033
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.95409596
Short name T2087
Test name
Test status
Simulation time 15410617 ps
CPU time 0.71 seconds
Started Mar 12 12:46:09 PM PDT 24
Finished Mar 12 12:46:13 PM PDT 24
Peak memory 203508 kb
Host smart-4fbda8c9-71c9-4f76-99f8-3a571b1316a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95409596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.95409596
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2243548806
Short name T2007
Test name
Test status
Simulation time 96486344 ps
CPU time 1.67 seconds
Started Mar 12 12:46:09 PM PDT 24
Finished Mar 12 12:46:14 PM PDT 24
Peak memory 207088 kb
Host smart-085c33f9-c50d-427f-99a8-9b2fc212870d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243548806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2243548806
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3979115179
Short name T2182
Test name
Test status
Simulation time 180641667 ps
CPU time 3.26 seconds
Started Mar 12 12:59:31 PM PDT 24
Finished Mar 12 12:59:34 PM PDT 24
Peak memory 215320 kb
Host smart-b7d01991-90c7-40e5-9b76-3b1af8f3f267
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979115179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3979115179
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1379795252
Short name T2128
Test name
Test status
Simulation time 40637356 ps
CPU time 1.59 seconds
Started Mar 12 12:46:09 PM PDT 24
Finished Mar 12 12:46:14 PM PDT 24
Peak memory 215428 kb
Host smart-7a4f3fbf-c8a6-4816-be3a-f344dfc060aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379795252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1379795252
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3611957391
Short name T2223
Test name
Test status
Simulation time 174211276 ps
CPU time 3.64 seconds
Started Mar 12 12:59:31 PM PDT 24
Finished Mar 12 12:59:35 PM PDT 24
Peak memory 215440 kb
Host smart-063e0e1a-bde2-4291-a4ee-319deaf9fa4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611957391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3611957391
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2861098365
Short name T2111
Test name
Test status
Simulation time 1331697644 ps
CPU time 21.09 seconds
Started Mar 12 12:46:08 PM PDT 24
Finished Mar 12 12:46:33 PM PDT 24
Peak memory 215572 kb
Host smart-2ef57c36-6596-4446-89fe-485bcd50f3bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861098365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2861098365
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1799439534
Short name T114
Test name
Test status
Simulation time 199832996 ps
CPU time 3.96 seconds
Started Mar 12 12:46:11 PM PDT 24
Finished Mar 12 12:46:18 PM PDT 24
Peak memory 217312 kb
Host smart-1d06d67b-f2b2-4c4a-ae62-a3f9695b1b94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799439534 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1799439534
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2363388384
Short name T2040
Test name
Test status
Simulation time 104441406 ps
CPU time 2.68 seconds
Started Mar 12 12:59:26 PM PDT 24
Finished Mar 12 12:59:29 PM PDT 24
Peak memory 216392 kb
Host smart-d16914d0-2d3d-4b68-8f0a-ef06150fff93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363388384 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2363388384
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2144049240
Short name T2119
Test name
Test status
Simulation time 275033638 ps
CPU time 1.87 seconds
Started Mar 12 12:59:20 PM PDT 24
Finished Mar 12 12:59:22 PM PDT 24
Peak memory 215560 kb
Host smart-505c8b20-9ce9-4529-85d0-833e8407eecb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144049240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2144049240
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1040817188
Short name T1991
Test name
Test status
Simulation time 11619756 ps
CPU time 0.69 seconds
Started Mar 12 12:46:09 PM PDT 24
Finished Mar 12 12:46:13 PM PDT 24
Peak memory 203460 kb
Host smart-b7319b1c-f46d-473e-bd96-7bef6dbfb702
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040817188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1040817188
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2646792953
Short name T2186
Test name
Test status
Simulation time 26146336 ps
CPU time 0.77 seconds
Started Mar 12 12:59:21 PM PDT 24
Finished Mar 12 12:59:22 PM PDT 24
Peak memory 203464 kb
Host smart-eb11c83b-4233-4dd7-b0ad-45572f9c107c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646792953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2646792953
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.200530613
Short name T2089
Test name
Test status
Simulation time 164406719 ps
CPU time 3.33 seconds
Started Mar 12 12:46:08 PM PDT 24
Finished Mar 12 12:46:15 PM PDT 24
Peak memory 215344 kb
Host smart-89b3fbe3-a547-4912-b2d1-bceeb4be4fed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200530613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.200530613
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.374061144
Short name T1948
Test name
Test status
Simulation time 2145488721 ps
CPU time 4.11 seconds
Started Mar 12 12:59:31 PM PDT 24
Finished Mar 12 12:59:35 PM PDT 24
Peak memory 215304 kb
Host smart-8b9f4681-86bd-478a-abbe-c5610d46a9fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374061144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.374061144
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2487286997
Short name T2055
Test name
Test status
Simulation time 68713337 ps
CPU time 2.33 seconds
Started Mar 12 12:59:16 PM PDT 24
Finished Mar 12 12:59:19 PM PDT 24
Peak memory 216460 kb
Host smart-425c6c03-736a-4abc-9ef3-1f1cb5446de7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487286997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2487286997
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.756980234
Short name T2020
Test name
Test status
Simulation time 283744314 ps
CPU time 3.47 seconds
Started Mar 12 12:46:08 PM PDT 24
Finished Mar 12 12:46:15 PM PDT 24
Peak memory 215612 kb
Host smart-acb16fd9-176c-4e80-9161-ba011c715f5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756980234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.756980234
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.896487795
Short name T177
Test name
Test status
Simulation time 786712905 ps
CPU time 12.12 seconds
Started Mar 12 12:59:26 PM PDT 24
Finished Mar 12 12:59:38 PM PDT 24
Peak memory 215312 kb
Host smart-440982ad-6c6d-49dc-bf4f-a40c65ccc7cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896487795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.896487795
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.936278944
Short name T176
Test name
Test status
Simulation time 602946322 ps
CPU time 14.28 seconds
Started Mar 12 12:46:07 PM PDT 24
Finished Mar 12 12:46:22 PM PDT 24
Peak memory 215284 kb
Host smart-7bb0834d-df8b-4041-8cf8-f032c1bcdd38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936278944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.936278944
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1877006913
Short name T2211
Test name
Test status
Simulation time 142024603 ps
CPU time 2.91 seconds
Started Mar 12 12:46:12 PM PDT 24
Finished Mar 12 12:46:17 PM PDT 24
Peak memory 216404 kb
Host smart-b8afc126-e840-4024-b26e-0fd3b6c7673c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877006913 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1877006913
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.556979171
Short name T2114
Test name
Test status
Simulation time 235988996 ps
CPU time 3.37 seconds
Started Mar 12 12:59:36 PM PDT 24
Finished Mar 12 12:59:39 PM PDT 24
Peak memory 217484 kb
Host smart-b9501f86-df07-4660-b0b2-126a3697c171
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556979171 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.556979171
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.16457375
Short name T2049
Test name
Test status
Simulation time 19551506 ps
CPU time 1.22 seconds
Started Mar 12 12:59:24 PM PDT 24
Finished Mar 12 12:59:25 PM PDT 24
Peak memory 207056 kb
Host smart-d96a803c-78d5-4611-a8e7-099cc556e9d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16457375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.16457375
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2102986573
Short name T2219
Test name
Test status
Simulation time 186461771 ps
CPU time 2.57 seconds
Started Mar 12 12:46:13 PM PDT 24
Finished Mar 12 12:46:17 PM PDT 24
Peak memory 215340 kb
Host smart-86ab5742-ee4a-4a82-9146-eae0a4dc1b55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102986573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2102986573
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2024424878
Short name T1992
Test name
Test status
Simulation time 20832095 ps
CPU time 0.74 seconds
Started Mar 12 12:46:13 PM PDT 24
Finished Mar 12 12:46:15 PM PDT 24
Peak memory 203428 kb
Host smart-c14be331-b90c-4896-a334-86c3b226c2b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024424878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2024424878
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2613346340
Short name T2019
Test name
Test status
Simulation time 48402822 ps
CPU time 0.72 seconds
Started Mar 12 12:59:29 PM PDT 24
Finished Mar 12 12:59:29 PM PDT 24
Peak memory 203540 kb
Host smart-2a0c32d7-c3e2-4057-98c7-b9ae90f4c760
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613346340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2613346340
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3885904405
Short name T2187
Test name
Test status
Simulation time 30770540 ps
CPU time 1.75 seconds
Started Mar 12 12:46:06 PM PDT 24
Finished Mar 12 12:46:09 PM PDT 24
Peak memory 207132 kb
Host smart-ad5c5aa8-3ac0-4a24-821a-0d789fde5b43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885904405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3885904405
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.449160000
Short name T2052
Test name
Test status
Simulation time 402048866 ps
CPU time 4.17 seconds
Started Mar 12 12:59:20 PM PDT 24
Finished Mar 12 12:59:24 PM PDT 24
Peak memory 215344 kb
Host smart-31124ce4-affb-4de7-9892-ca2b91b27030
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449160000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.449160000
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3488404267
Short name T2095
Test name
Test status
Simulation time 104407791 ps
CPU time 2.48 seconds
Started Mar 12 12:46:09 PM PDT 24
Finished Mar 12 12:46:14 PM PDT 24
Peak memory 215504 kb
Host smart-5e6916f7-7318-4450-84ca-aa5a53d5c30b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488404267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3488404267
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1368307796
Short name T116
Test name
Test status
Simulation time 213225297 ps
CPU time 13.13 seconds
Started Mar 12 12:46:11 PM PDT 24
Finished Mar 12 12:46:27 PM PDT 24
Peak memory 215340 kb
Host smart-1be282de-7bba-4a69-9e81-12735e2c05f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368307796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1368307796
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.4080427529
Short name T2189
Test name
Test status
Simulation time 608728329 ps
CPU time 15.07 seconds
Started Mar 12 12:59:39 PM PDT 24
Finished Mar 12 12:59:54 PM PDT 24
Peak memory 215164 kb
Host smart-93d27ac8-c757-4cda-a088-55564b02a4cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080427529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.4080427529
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2225819154
Short name T95
Test name
Test status
Simulation time 258834455 ps
CPU time 3.4 seconds
Started Mar 12 12:46:08 PM PDT 24
Finished Mar 12 12:46:15 PM PDT 24
Peak memory 216712 kb
Host smart-98c4817d-6937-4ab6-87c9-8b4a08232f1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225819154 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2225819154
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2600653247
Short name T1975
Test name
Test status
Simulation time 83573133 ps
CPU time 2.77 seconds
Started Mar 12 12:59:49 PM PDT 24
Finished Mar 12 12:59:52 PM PDT 24
Peak memory 216472 kb
Host smart-570f6364-4b33-4710-b9bc-cf0bcd63e720
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600653247 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2600653247
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1992113828
Short name T133
Test name
Test status
Simulation time 312573540 ps
CPU time 2.4 seconds
Started Mar 12 12:59:47 PM PDT 24
Finished Mar 12 12:59:50 PM PDT 24
Peak memory 207044 kb
Host smart-d2e17e82-c21c-48a0-88d7-29f7dface3df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992113828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1992113828
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.909773363
Short name T2208
Test name
Test status
Simulation time 296884463 ps
CPU time 2.43 seconds
Started Mar 12 12:46:14 PM PDT 24
Finished Mar 12 12:46:17 PM PDT 24
Peak memory 215260 kb
Host smart-39641174-1dc2-4c59-ab97-b945cd7c2b24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909773363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.909773363
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.304738087
Short name T2131
Test name
Test status
Simulation time 18487101 ps
CPU time 0.75 seconds
Started Mar 12 12:46:14 PM PDT 24
Finished Mar 12 12:46:15 PM PDT 24
Peak memory 203392 kb
Host smart-f176d71c-11fa-4bd5-9a9b-611cab83eb7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304738087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.304738087
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.426811450
Short name T2199
Test name
Test status
Simulation time 26055767 ps
CPU time 0.79 seconds
Started Mar 12 12:59:38 PM PDT 24
Finished Mar 12 12:59:39 PM PDT 24
Peak memory 203412 kb
Host smart-80f38fae-d7db-484e-9964-ab5b870f0676
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426811450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.426811450
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1833193485
Short name T1966
Test name
Test status
Simulation time 66068658 ps
CPU time 4.04 seconds
Started Mar 12 12:59:53 PM PDT 24
Finished Mar 12 12:59:57 PM PDT 24
Peak memory 215348 kb
Host smart-7860f2ab-5df3-450a-b5c3-6161104eebc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833193485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1833193485
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2370433512
Short name T2123
Test name
Test status
Simulation time 226230413 ps
CPU time 4.26 seconds
Started Mar 12 12:46:14 PM PDT 24
Finished Mar 12 12:46:19 PM PDT 24
Peak memory 215320 kb
Host smart-021b5c57-710d-4b47-914c-b5fc60edc0cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370433512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2370433512
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3355186334
Short name T110
Test name
Test status
Simulation time 58229931 ps
CPU time 3.88 seconds
Started Mar 12 12:46:10 PM PDT 24
Finished Mar 12 12:46:16 PM PDT 24
Peak memory 215588 kb
Host smart-88adb201-f089-40f2-9efd-1939b0030aa7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355186334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3355186334
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.4190362712
Short name T2017
Test name
Test status
Simulation time 138465185 ps
CPU time 1.5 seconds
Started Mar 12 12:59:22 PM PDT 24
Finished Mar 12 12:59:24 PM PDT 24
Peak memory 215436 kb
Host smart-a9334e48-5e5e-4741-822c-ada53762b022
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190362712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
4190362712
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1338813101
Short name T2093
Test name
Test status
Simulation time 222150987 ps
CPU time 7.55 seconds
Started Mar 12 12:46:11 PM PDT 24
Finished Mar 12 12:46:21 PM PDT 24
Peak memory 215672 kb
Host smart-e5453b2a-66b6-4a8b-bfba-6aaa2a2e9f52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338813101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1338813101
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.4078619015
Short name T182
Test name
Test status
Simulation time 339975015 ps
CPU time 8.48 seconds
Started Mar 12 12:59:33 PM PDT 24
Finished Mar 12 12:59:41 PM PDT 24
Peak memory 215212 kb
Host smart-2be5d22f-8134-48a1-9b4f-1c0b016c3b74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078619015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.4078619015
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1906524823
Short name T2041
Test name
Test status
Simulation time 47596100 ps
CPU time 2.11 seconds
Started Mar 12 12:59:52 PM PDT 24
Finished Mar 12 12:59:54 PM PDT 24
Peak memory 215468 kb
Host smart-954b591c-7b21-402f-a62b-72e70d807219
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906524823 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1906524823
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2870972629
Short name T1973
Test name
Test status
Simulation time 486526079 ps
CPU time 3.22 seconds
Started Mar 12 12:46:08 PM PDT 24
Finished Mar 12 12:46:15 PM PDT 24
Peak memory 216992 kb
Host smart-7cce13e0-05d1-4bcf-976b-56c4dd582097
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870972629 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2870972629
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.630268219
Short name T2024
Test name
Test status
Simulation time 349731364 ps
CPU time 2.14 seconds
Started Mar 12 01:00:01 PM PDT 24
Finished Mar 12 01:00:04 PM PDT 24
Peak memory 215348 kb
Host smart-d1edf147-0c7d-4b3d-8438-a3a6a758c81c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630268219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.630268219
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.997221533
Short name T2103
Test name
Test status
Simulation time 40385165 ps
CPU time 1.4 seconds
Started Mar 12 12:46:09 PM PDT 24
Finished Mar 12 12:46:14 PM PDT 24
Peak memory 207092 kb
Host smart-30cb3e58-2969-47cd-9afa-12511b31608a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997221533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.997221533
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3481614274
Short name T1943
Test name
Test status
Simulation time 59612524 ps
CPU time 0.77 seconds
Started Mar 12 12:59:46 PM PDT 24
Finished Mar 12 12:59:47 PM PDT 24
Peak memory 203364 kb
Host smart-32c7f170-80f0-46ae-9891-839f6c5816e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481614274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3481614274
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.764111108
Short name T2185
Test name
Test status
Simulation time 33881047 ps
CPU time 0.68 seconds
Started Mar 12 12:46:12 PM PDT 24
Finished Mar 12 12:46:15 PM PDT 24
Peak memory 203292 kb
Host smart-67e67767-3405-4ca0-99ee-bea4fec22437
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764111108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.764111108
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3362775269
Short name T2169
Test name
Test status
Simulation time 485395345 ps
CPU time 2.93 seconds
Started Mar 12 12:59:46 PM PDT 24
Finished Mar 12 12:59:49 PM PDT 24
Peak memory 215276 kb
Host smart-06bbc15d-c1bf-42f4-81be-76773c999347
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362775269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3362775269
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3703647930
Short name T2163
Test name
Test status
Simulation time 1050470584 ps
CPU time 4.33 seconds
Started Mar 12 12:46:12 PM PDT 24
Finished Mar 12 12:46:18 PM PDT 24
Peak memory 215352 kb
Host smart-a8eb697f-47c0-454c-9dda-e6a5dae7ff88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703647930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3703647930
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2146255864
Short name T175
Test name
Test status
Simulation time 1116929724 ps
CPU time 5.35 seconds
Started Mar 12 12:59:44 PM PDT 24
Finished Mar 12 12:59:50 PM PDT 24
Peak memory 215476 kb
Host smart-46c43db7-0185-4dfb-8e76-4656ddb25a36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146255864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2146255864
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2580065419
Short name T2142
Test name
Test status
Simulation time 137530475 ps
CPU time 3.39 seconds
Started Mar 12 12:46:12 PM PDT 24
Finished Mar 12 12:46:17 PM PDT 24
Peak memory 215592 kb
Host smart-8d66fc34-b722-4dc7-947b-85dc2ba481ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580065419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2580065419
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2950233055
Short name T2033
Test name
Test status
Simulation time 1723527059 ps
CPU time 22.08 seconds
Started Mar 12 12:59:49 PM PDT 24
Finished Mar 12 01:00:11 PM PDT 24
Peak memory 215844 kb
Host smart-717a5ea1-9d64-42fc-a873-21fc30288e1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950233055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2950233055
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3062377498
Short name T1993
Test name
Test status
Simulation time 343974688 ps
CPU time 8.26 seconds
Started Mar 12 12:46:12 PM PDT 24
Finished Mar 12 12:46:22 PM PDT 24
Peak memory 215404 kb
Host smart-d16115b8-02e6-46bb-bc54-5db957ba39d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062377498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3062377498
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.334238016
Short name T2057
Test name
Test status
Simulation time 112908517 ps
CPU time 2.59 seconds
Started Mar 12 12:59:46 PM PDT 24
Finished Mar 12 12:59:49 PM PDT 24
Peak memory 216788 kb
Host smart-6dd1b361-9a98-4186-aa47-4d0fece59052
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334238016 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.334238016
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.636610347
Short name T2034
Test name
Test status
Simulation time 823257291 ps
CPU time 2.97 seconds
Started Mar 12 12:46:22 PM PDT 24
Finished Mar 12 12:46:26 PM PDT 24
Peak memory 217576 kb
Host smart-1b263d44-7ef4-416b-95ef-3c4fe1f20f42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636610347 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.636610347
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2152895593
Short name T2074
Test name
Test status
Simulation time 111371049 ps
CPU time 1.22 seconds
Started Mar 12 12:46:30 PM PDT 24
Finished Mar 12 12:46:32 PM PDT 24
Peak memory 207012 kb
Host smart-74da632b-7ce7-4eb1-a10e-c99e8b091bfa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152895593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2152895593
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3209037932
Short name T2016
Test name
Test status
Simulation time 178786720 ps
CPU time 1.24 seconds
Started Mar 12 12:59:41 PM PDT 24
Finished Mar 12 12:59:42 PM PDT 24
Peak memory 207112 kb
Host smart-76c257c3-b580-4b5b-98b0-473877734c4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209037932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3209037932
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.120204964
Short name T2082
Test name
Test status
Simulation time 48783939 ps
CPU time 0.72 seconds
Started Mar 12 12:59:36 PM PDT 24
Finished Mar 12 12:59:37 PM PDT 24
Peak memory 203484 kb
Host smart-97b26dac-4698-4d40-bb44-c68f757d11ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120204964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.120204964
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.146639400
Short name T1958
Test name
Test status
Simulation time 46408858 ps
CPU time 0.76 seconds
Started Mar 12 12:46:24 PM PDT 24
Finished Mar 12 12:46:25 PM PDT 24
Peak memory 203388 kb
Host smart-356e5cb0-61b4-43ad-b00b-8cb3bf54f063
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146639400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.146639400
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2218819725
Short name T2006
Test name
Test status
Simulation time 59940788 ps
CPU time 1.94 seconds
Started Mar 12 12:59:44 PM PDT 24
Finished Mar 12 12:59:46 PM PDT 24
Peak memory 215196 kb
Host smart-1413daf7-f117-4816-9cfb-7f0f8c2ffcd5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218819725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2218819725
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.905175557
Short name T2184
Test name
Test status
Simulation time 150336412 ps
CPU time 3.73 seconds
Started Mar 12 12:46:18 PM PDT 24
Finished Mar 12 12:46:22 PM PDT 24
Peak memory 215316 kb
Host smart-bd586304-01ba-436b-99fd-214db158ca17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905175557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.905175557
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1974279352
Short name T2213
Test name
Test status
Simulation time 130238852 ps
CPU time 2.38 seconds
Started Mar 12 12:46:28 PM PDT 24
Finished Mar 12 12:46:31 PM PDT 24
Peak memory 215440 kb
Host smart-e3ea8b23-072e-4edd-ae79-7cfbc37424fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974279352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1974279352
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.298230905
Short name T2071
Test name
Test status
Simulation time 54915266 ps
CPU time 1.97 seconds
Started Mar 12 12:59:34 PM PDT 24
Finished Mar 12 12:59:36 PM PDT 24
Peak memory 215604 kb
Host smart-0b72ba17-c92e-4eb8-a75e-ca99cacc1aa4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298230905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.298230905
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3019743736
Short name T2153
Test name
Test status
Simulation time 724298769 ps
CPU time 14.79 seconds
Started Mar 12 12:59:45 PM PDT 24
Finished Mar 12 01:00:00 PM PDT 24
Peak memory 215304 kb
Host smart-095fba2d-7b5d-441a-ba91-f8307688dcfe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019743736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3019743736
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3936063036
Short name T184
Test name
Test status
Simulation time 582901643 ps
CPU time 7.56 seconds
Started Mar 12 12:46:19 PM PDT 24
Finished Mar 12 12:46:27 PM PDT 24
Peak memory 215304 kb
Host smart-a2c491d9-7566-4438-bef8-9765a700baf6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936063036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3936063036
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2773168293
Short name T1998
Test name
Test status
Simulation time 41812987 ps
CPU time 2.76 seconds
Started Mar 12 12:46:21 PM PDT 24
Finished Mar 12 12:46:24 PM PDT 24
Peak memory 216384 kb
Host smart-93b44b6b-5e1a-42d0-9d30-685a831afa46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773168293 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2773168293
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.510663335
Short name T106
Test name
Test status
Simulation time 173452524 ps
CPU time 3.76 seconds
Started Mar 12 12:59:48 PM PDT 24
Finished Mar 12 12:59:52 PM PDT 24
Peak memory 216728 kb
Host smart-46ab58f3-4568-4bf4-b097-0f3466e3eb4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510663335 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.510663335
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.144767668
Short name T2218
Test name
Test status
Simulation time 104709059 ps
CPU time 1.7 seconds
Started Mar 12 12:46:19 PM PDT 24
Finished Mar 12 12:46:21 PM PDT 24
Peak memory 215280 kb
Host smart-03a0a39b-0cfe-4bc6-a909-97f4c272b26e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144767668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.144767668
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3563004869
Short name T2064
Test name
Test status
Simulation time 58500474 ps
CPU time 2 seconds
Started Mar 12 12:59:49 PM PDT 24
Finished Mar 12 12:59:52 PM PDT 24
Peak memory 215304 kb
Host smart-9e0788fc-e1da-46fa-8da8-26e27607eab2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563004869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3563004869
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1843481791
Short name T1999
Test name
Test status
Simulation time 11269849 ps
CPU time 0.69 seconds
Started Mar 12 12:46:19 PM PDT 24
Finished Mar 12 12:46:20 PM PDT 24
Peak memory 203400 kb
Host smart-b184fb73-3b60-4b0a-87fc-a40a597f675d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843481791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1843481791
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2228669881
Short name T1967
Test name
Test status
Simulation time 13774478 ps
CPU time 0.7 seconds
Started Mar 12 12:59:35 PM PDT 24
Finished Mar 12 12:59:36 PM PDT 24
Peak memory 203408 kb
Host smart-2bae473f-d0db-4818-9fad-c7f5d96a2e66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228669881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2228669881
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.355288573
Short name T2100
Test name
Test status
Simulation time 27237639 ps
CPU time 1.66 seconds
Started Mar 12 12:46:19 PM PDT 24
Finished Mar 12 12:46:21 PM PDT 24
Peak memory 215280 kb
Host smart-44de5881-48d0-4ab2-8399-5d1258092939
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355288573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.355288573
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4112856623
Short name T2195
Test name
Test status
Simulation time 144570914 ps
CPU time 3.34 seconds
Started Mar 12 12:59:42 PM PDT 24
Finished Mar 12 12:59:46 PM PDT 24
Peak memory 215240 kb
Host smart-c678386c-2683-4114-8dd7-04e712ee7e26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112856623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.4112856623
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2170897024
Short name T2008
Test name
Test status
Simulation time 180326842 ps
CPU time 1.39 seconds
Started Mar 12 12:46:18 PM PDT 24
Finished Mar 12 12:46:19 PM PDT 24
Peak memory 216492 kb
Host smart-65bd72d3-6f4c-4a5f-bfce-6fe1eec70fad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170897024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2170897024
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.769982378
Short name T2135
Test name
Test status
Simulation time 2645679285 ps
CPU time 8.05 seconds
Started Mar 12 12:59:47 PM PDT 24
Finished Mar 12 12:59:55 PM PDT 24
Peak memory 215288 kb
Host smart-373f8d6d-7bd4-45e8-904a-50fba5f98841
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769982378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.769982378
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.900804566
Short name T183
Test name
Test status
Simulation time 303290577 ps
CPU time 16.87 seconds
Started Mar 12 12:46:22 PM PDT 24
Finished Mar 12 12:46:39 PM PDT 24
Peak memory 215368 kb
Host smart-fa329121-e836-48e7-98b6-519e486e47e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900804566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.900804566
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1921789461
Short name T2154
Test name
Test status
Simulation time 301913852 ps
CPU time 2.77 seconds
Started Mar 12 12:59:42 PM PDT 24
Finished Mar 12 12:59:45 PM PDT 24
Peak memory 216420 kb
Host smart-f76f785c-dc32-4c04-98fe-1c88d4e253aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921789461 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1921789461
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.359690241
Short name T135
Test name
Test status
Simulation time 67830476 ps
CPU time 1.25 seconds
Started Mar 12 12:59:43 PM PDT 24
Finished Mar 12 12:59:44 PM PDT 24
Peak memory 215332 kb
Host smart-9a807ed6-60c2-4186-8b02-596dfbb41a0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359690241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.359690241
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.4067636129
Short name T128
Test name
Test status
Simulation time 41289952 ps
CPU time 2.5 seconds
Started Mar 12 12:46:20 PM PDT 24
Finished Mar 12 12:46:23 PM PDT 24
Peak memory 215260 kb
Host smart-0fc89646-57d5-40b7-803b-1ac524e70892
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067636129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
4067636129
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3215141631
Short name T2149
Test name
Test status
Simulation time 67682641 ps
CPU time 0.71 seconds
Started Mar 12 12:59:37 PM PDT 24
Finished Mar 12 12:59:38 PM PDT 24
Peak memory 203508 kb
Host smart-44c439c6-7dc8-438e-9f69-51291fac14b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215141631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3215141631
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3417960211
Short name T1946
Test name
Test status
Simulation time 40528981 ps
CPU time 0.78 seconds
Started Mar 12 12:46:20 PM PDT 24
Finished Mar 12 12:46:21 PM PDT 24
Peak memory 203380 kb
Host smart-ae7c565a-e758-4d82-aeb0-c5b31fccf62b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417960211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3417960211
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2854054567
Short name T1994
Test name
Test status
Simulation time 179463358 ps
CPU time 4.12 seconds
Started Mar 12 12:59:51 PM PDT 24
Finished Mar 12 12:59:55 PM PDT 24
Peak memory 215296 kb
Host smart-f1dd46c5-f177-4e46-9f9b-d60eda11a030
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854054567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2854054567
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.32275171
Short name T2058
Test name
Test status
Simulation time 175279321 ps
CPU time 3.79 seconds
Started Mar 12 12:46:20 PM PDT 24
Finished Mar 12 12:46:24 PM PDT 24
Peak memory 215312 kb
Host smart-5d2eefa7-ede1-430a-bb53-a027316a238f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32275171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sp
i_device_same_csr_outstanding.32275171
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1994588886
Short name T2141
Test name
Test status
Simulation time 353886646 ps
CPU time 1.96 seconds
Started Mar 12 12:59:55 PM PDT 24
Finished Mar 12 12:59:58 PM PDT 24
Peak memory 215576 kb
Host smart-0a006328-faad-44d9-bacd-f62f40fd93ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994588886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1994588886
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.51295783
Short name T1995
Test name
Test status
Simulation time 157143073 ps
CPU time 1.41 seconds
Started Mar 12 12:46:21 PM PDT 24
Finished Mar 12 12:46:23 PM PDT 24
Peak memory 215456 kb
Host smart-27ba18c7-d6e2-4312-9fed-6c2c2e29d16e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51295783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.51295783
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.266641857
Short name T117
Test name
Test status
Simulation time 3006281152 ps
CPU time 13.48 seconds
Started Mar 12 12:59:33 PM PDT 24
Finished Mar 12 12:59:47 PM PDT 24
Peak memory 215360 kb
Host smart-13f41c82-f69b-4fd1-acc5-4d223957f681
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266641857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.266641857
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3888488408
Short name T2144
Test name
Test status
Simulation time 983182476 ps
CPU time 21.05 seconds
Started Mar 12 12:46:20 PM PDT 24
Finished Mar 12 12:46:41 PM PDT 24
Peak memory 215260 kb
Host smart-8e8cd325-64cb-4073-8135-084b647ba7b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888488408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3888488408
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2354345748
Short name T125
Test name
Test status
Simulation time 410127976 ps
CPU time 7.5 seconds
Started Mar 12 12:59:22 PM PDT 24
Finished Mar 12 12:59:30 PM PDT 24
Peak memory 215324 kb
Host smart-c4f984b0-fcb1-4fd1-9b41-f280a3b1eaac
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354345748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2354345748
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.85637548
Short name T1944
Test name
Test status
Simulation time 332809181 ps
CPU time 15.88 seconds
Started Mar 12 12:46:00 PM PDT 24
Finished Mar 12 12:46:16 PM PDT 24
Peak memory 207140 kb
Host smart-05a68442-b180-4f52-8325-d0e12e1c28c2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85637548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_
aliasing.85637548
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1278175527
Short name T2039
Test name
Test status
Simulation time 189992186 ps
CPU time 11.67 seconds
Started Mar 12 12:59:17 PM PDT 24
Finished Mar 12 12:59:29 PM PDT 24
Peak memory 207120 kb
Host smart-fbb451b9-04a5-4b96-8a82-d580e6ac6de5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278175527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1278175527
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.46498779
Short name T2162
Test name
Test status
Simulation time 738884764 ps
CPU time 12.73 seconds
Started Mar 12 12:45:57 PM PDT 24
Finished Mar 12 12:46:10 PM PDT 24
Peak memory 207024 kb
Host smart-50f78cec-238c-4142-8a39-f99e95193b22
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46498779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_
bit_bash.46498779
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1378704328
Short name T77
Test name
Test status
Simulation time 77055829 ps
CPU time 1.39 seconds
Started Mar 12 12:45:56 PM PDT 24
Finished Mar 12 12:45:57 PM PDT 24
Peak memory 207080 kb
Host smart-6a5669be-525c-49b7-ba02-65d5477b5c14
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378704328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1378704328
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3197784746
Short name T1963
Test name
Test status
Simulation time 63318565 ps
CPU time 0.94 seconds
Started Mar 12 12:59:40 PM PDT 24
Finished Mar 12 12:59:41 PM PDT 24
Peak memory 206820 kb
Host smart-8dd102bb-812b-457e-8cf3-baa85093050f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197784746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3197784746
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2483506666
Short name T2212
Test name
Test status
Simulation time 42712854 ps
CPU time 2.64 seconds
Started Mar 12 01:01:36 PM PDT 24
Finished Mar 12 01:01:39 PM PDT 24
Peak memory 216544 kb
Host smart-eb74b767-4f2b-4ebe-a137-9fad4313120a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483506666 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2483506666
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3431047388
Short name T115
Test name
Test status
Simulation time 103028647 ps
CPU time 2.59 seconds
Started Mar 12 12:45:57 PM PDT 24
Finished Mar 12 12:46:00 PM PDT 24
Peak memory 216484 kb
Host smart-83c00e11-ea44-486c-a40d-c6ab6f361a0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431047388 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3431047388
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3950401205
Short name T2121
Test name
Test status
Simulation time 668608420 ps
CPU time 2.87 seconds
Started Mar 12 12:45:58 PM PDT 24
Finished Mar 12 12:46:01 PM PDT 24
Peak memory 215324 kb
Host smart-c030bf1e-c4af-4529-994e-c7392b5fa9f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950401205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
950401205
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.795713212
Short name T2122
Test name
Test status
Simulation time 75493570 ps
CPU time 1.22 seconds
Started Mar 12 01:01:24 PM PDT 24
Finished Mar 12 01:01:26 PM PDT 24
Peak memory 206928 kb
Host smart-2a724663-c40b-4c64-a73b-79ea5d2ece36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795713212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.795713212
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.263935152
Short name T2168
Test name
Test status
Simulation time 12124473 ps
CPU time 0.7 seconds
Started Mar 12 12:59:11 PM PDT 24
Finished Mar 12 12:59:12 PM PDT 24
Peak memory 203436 kb
Host smart-eef40056-bd4e-496e-8c25-c9d910980a76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263935152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.263935152
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.636558813
Short name T2190
Test name
Test status
Simulation time 10678124 ps
CPU time 0.72 seconds
Started Mar 12 12:45:56 PM PDT 24
Finished Mar 12 12:45:57 PM PDT 24
Peak memory 203432 kb
Host smart-96c34651-db4c-4b20-b6ba-783baed0a71d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636558813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.636558813
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1431409627
Short name T2165
Test name
Test status
Simulation time 173982212 ps
CPU time 1.71 seconds
Started Mar 12 12:45:55 PM PDT 24
Finished Mar 12 12:45:56 PM PDT 24
Peak memory 215348 kb
Host smart-787a4a56-b06b-449a-82c7-32982171eef0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431409627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1431409627
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3929260881
Short name T2155
Test name
Test status
Simulation time 34168627 ps
CPU time 1.3 seconds
Started Mar 12 12:59:24 PM PDT 24
Finished Mar 12 12:59:25 PM PDT 24
Peak memory 215312 kb
Host smart-f572a4b5-bebc-4023-892f-68e7cb1859bd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929260881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3929260881
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2692508067
Short name T2025
Test name
Test status
Simulation time 37609218 ps
CPU time 0.66 seconds
Started Mar 12 12:45:53 PM PDT 24
Finished Mar 12 12:45:54 PM PDT 24
Peak memory 203352 kb
Host smart-d953f0aa-6d3e-41b9-aa32-813e6155ed5c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692508067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2692508067
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3531912329
Short name T2048
Test name
Test status
Simulation time 26717861 ps
CPU time 0.66 seconds
Started Mar 12 12:59:17 PM PDT 24
Finished Mar 12 12:59:18 PM PDT 24
Peak memory 203352 kb
Host smart-6a1642b3-c6c6-4ed8-9845-061f6f555653
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531912329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3531912329
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.23811103
Short name T2079
Test name
Test status
Simulation time 65872279 ps
CPU time 4.03 seconds
Started Mar 12 12:59:13 PM PDT 24
Finished Mar 12 12:59:17 PM PDT 24
Peak memory 215384 kb
Host smart-7d581f66-1a73-492f-a52d-d50b86679ab6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23811103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_same_csr_outstanding.23811103
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.870602892
Short name T1988
Test name
Test status
Simulation time 150275909 ps
CPU time 1.97 seconds
Started Mar 12 12:45:56 PM PDT 24
Finished Mar 12 12:45:58 PM PDT 24
Peak memory 207096 kb
Host smart-a17660f9-370e-4759-9c80-6a04b64555b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870602892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.870602892
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2813573065
Short name T2147
Test name
Test status
Simulation time 122565368 ps
CPU time 2.42 seconds
Started Mar 12 12:45:50 PM PDT 24
Finished Mar 12 12:45:52 PM PDT 24
Peak memory 215608 kb
Host smart-036824e5-ce75-4341-91ea-6cb5e86f5623
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813573065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
813573065
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3419447894
Short name T2159
Test name
Test status
Simulation time 119693818 ps
CPU time 2.24 seconds
Started Mar 12 12:59:24 PM PDT 24
Finished Mar 12 12:59:26 PM PDT 24
Peak memory 215556 kb
Host smart-1e6f3049-08ad-46e5-bde0-2b2f35a8f53a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419447894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
419447894
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2772087164
Short name T113
Test name
Test status
Simulation time 3307060454 ps
CPU time 19.53 seconds
Started Mar 12 01:00:54 PM PDT 24
Finished Mar 12 01:01:14 PM PDT 24
Peak memory 214120 kb
Host smart-3bc4f97a-4989-4937-9d3c-a6e866b4dc0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772087164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2772087164
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2949750685
Short name T2176
Test name
Test status
Simulation time 491878187 ps
CPU time 6.18 seconds
Started Mar 12 12:45:57 PM PDT 24
Finished Mar 12 12:46:04 PM PDT 24
Peak memory 215688 kb
Host smart-c823acf4-1751-48e2-9108-1f498d8ca39c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949750685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2949750685
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2320459389
Short name T1968
Test name
Test status
Simulation time 21215754 ps
CPU time 0.72 seconds
Started Mar 12 12:46:25 PM PDT 24
Finished Mar 12 12:46:26 PM PDT 24
Peak memory 203380 kb
Host smart-24cfcecb-30df-4286-8772-17f794e9b5a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320459389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2320459389
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2619388461
Short name T2146
Test name
Test status
Simulation time 12218043 ps
CPU time 0.77 seconds
Started Mar 12 12:59:51 PM PDT 24
Finished Mar 12 12:59:53 PM PDT 24
Peak memory 203432 kb
Host smart-4d655a29-b403-4a05-a4a4-c4e2428ef9c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619388461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2619388461
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.4147822273
Short name T1979
Test name
Test status
Simulation time 38479121 ps
CPU time 0.7 seconds
Started Mar 12 12:46:24 PM PDT 24
Finished Mar 12 12:46:25 PM PDT 24
Peak memory 203392 kb
Host smart-8b032a48-3ff3-4d03-b50b-93fb6855deef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147822273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
4147822273
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.4219689753
Short name T1956
Test name
Test status
Simulation time 43068082 ps
CPU time 0.76 seconds
Started Mar 12 12:59:47 PM PDT 24
Finished Mar 12 12:59:48 PM PDT 24
Peak memory 203488 kb
Host smart-92d70415-da28-4cfe-bf25-5392a103fdf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219689753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
4219689753
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2670360298
Short name T2047
Test name
Test status
Simulation time 12796391 ps
CPU time 0.74 seconds
Started Mar 12 12:46:23 PM PDT 24
Finished Mar 12 12:46:25 PM PDT 24
Peak memory 203484 kb
Host smart-5ab34b4d-4e91-4c48-a87f-1e132c076d9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670360298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2670360298
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3886160783
Short name T2012
Test name
Test status
Simulation time 150618357 ps
CPU time 0.69 seconds
Started Mar 12 12:59:53 PM PDT 24
Finished Mar 12 12:59:54 PM PDT 24
Peak memory 203420 kb
Host smart-faa550cf-26d9-4f72-8e7d-b81e1d177709
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886160783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3886160783
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2870209392
Short name T2026
Test name
Test status
Simulation time 40058295 ps
CPU time 0.74 seconds
Started Mar 12 12:46:21 PM PDT 24
Finished Mar 12 12:46:22 PM PDT 24
Peak memory 203524 kb
Host smart-da88c26d-2f4f-4212-a13b-81efb8c3c86c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870209392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2870209392
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.459394285
Short name T2201
Test name
Test status
Simulation time 14165087 ps
CPU time 0.72 seconds
Started Mar 12 12:59:49 PM PDT 24
Finished Mar 12 12:59:51 PM PDT 24
Peak memory 203504 kb
Host smart-5d92a6c0-91f8-4c52-b07e-cd22408c9237
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459394285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.459394285
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1054018322
Short name T2086
Test name
Test status
Simulation time 27155882 ps
CPU time 0.73 seconds
Started Mar 12 12:46:24 PM PDT 24
Finished Mar 12 12:46:25 PM PDT 24
Peak memory 203404 kb
Host smart-9eeae867-5e73-457b-a511-922de53a38d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054018322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1054018322
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.284747499
Short name T2140
Test name
Test status
Simulation time 45277752 ps
CPU time 0.71 seconds
Started Mar 12 12:59:45 PM PDT 24
Finished Mar 12 12:59:46 PM PDT 24
Peak memory 203336 kb
Host smart-d2096d79-9543-4a1a-a25d-ab013b97cc20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284747499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.284747499
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2634389291
Short name T1990
Test name
Test status
Simulation time 15092513 ps
CPU time 0.71 seconds
Started Mar 12 12:59:47 PM PDT 24
Finished Mar 12 12:59:48 PM PDT 24
Peak memory 203420 kb
Host smart-61ed7f71-87a2-4636-9ce7-0344e1102dd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634389291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2634389291
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.451315914
Short name T1971
Test name
Test status
Simulation time 23900865 ps
CPU time 0.71 seconds
Started Mar 12 12:46:20 PM PDT 24
Finished Mar 12 12:46:21 PM PDT 24
Peak memory 203400 kb
Host smart-b1895ff1-4b02-450a-ad73-a2ca534dcd30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451315914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.451315914
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2128471210
Short name T2202
Test name
Test status
Simulation time 118013992 ps
CPU time 0.74 seconds
Started Mar 12 12:46:24 PM PDT 24
Finished Mar 12 12:46:25 PM PDT 24
Peak memory 203392 kb
Host smart-691e35a8-226c-49c5-a264-0fc04bf317a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128471210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2128471210
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3197466044
Short name T2032
Test name
Test status
Simulation time 16962870 ps
CPU time 0.78 seconds
Started Mar 12 12:59:57 PM PDT 24
Finished Mar 12 12:59:58 PM PDT 24
Peak memory 203548 kb
Host smart-f9518e62-d21e-4a2a-8bf8-ac043f285a29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197466044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3197466044
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.153201769
Short name T2097
Test name
Test status
Simulation time 22003081 ps
CPU time 0.75 seconds
Started Mar 12 12:59:49 PM PDT 24
Finished Mar 12 12:59:50 PM PDT 24
Peak memory 203256 kb
Host smart-3745450f-9acc-476c-b5be-f56f6b97fea7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153201769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.153201769
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.582775718
Short name T2150
Test name
Test status
Simulation time 19842579 ps
CPU time 0.72 seconds
Started Mar 12 12:46:25 PM PDT 24
Finished Mar 12 12:46:26 PM PDT 24
Peak memory 203364 kb
Host smart-19048a5f-4a50-4f1d-af19-973e00922a3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582775718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.582775718
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1946412459
Short name T1954
Test name
Test status
Simulation time 13769293 ps
CPU time 0.7 seconds
Started Mar 12 12:59:55 PM PDT 24
Finished Mar 12 12:59:56 PM PDT 24
Peak memory 203372 kb
Host smart-86535316-35e0-4694-88c4-4ed21a6092db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946412459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1946412459
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3972658191
Short name T2108
Test name
Test status
Simulation time 37826644 ps
CPU time 0.7 seconds
Started Mar 12 12:46:28 PM PDT 24
Finished Mar 12 12:46:29 PM PDT 24
Peak memory 203416 kb
Host smart-71f769c5-5782-4bd0-8515-45a326387c1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972658191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3972658191
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2316081322
Short name T2152
Test name
Test status
Simulation time 37855375 ps
CPU time 0.67 seconds
Started Mar 12 12:46:27 PM PDT 24
Finished Mar 12 12:46:28 PM PDT 24
Peak memory 203420 kb
Host smart-307e8c87-7fdb-4713-ab12-6cd1118eb5fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316081322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2316081322
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3658863099
Short name T2207
Test name
Test status
Simulation time 23393387 ps
CPU time 0.81 seconds
Started Mar 12 12:59:52 PM PDT 24
Finished Mar 12 12:59:54 PM PDT 24
Peak memory 203468 kb
Host smart-b6271316-13b8-4ae2-9936-c0b907aa8d0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658863099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3658863099
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2770423454
Short name T2164
Test name
Test status
Simulation time 810043826 ps
CPU time 8.8 seconds
Started Mar 12 12:46:01 PM PDT 24
Finished Mar 12 12:46:10 PM PDT 24
Peak memory 215220 kb
Host smart-68d10676-34f1-4190-a8e5-f97e24f19171
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770423454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2770423454
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3506412490
Short name T2000
Test name
Test status
Simulation time 698176477 ps
CPU time 16.82 seconds
Started Mar 12 12:59:22 PM PDT 24
Finished Mar 12 12:59:39 PM PDT 24
Peak memory 215312 kb
Host smart-3e748a19-581e-4fa8-994b-1b6077e53fa1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506412490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3506412490
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2220009329
Short name T2139
Test name
Test status
Simulation time 10821547454 ps
CPU time 39.77 seconds
Started Mar 12 12:45:55 PM PDT 24
Finished Mar 12 12:46:35 PM PDT 24
Peak memory 215364 kb
Host smart-301c7b53-8438-495d-9f8e-9bf7e1e84615
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220009329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2220009329
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3993467185
Short name T2030
Test name
Test status
Simulation time 1205936626 ps
CPU time 25.7 seconds
Started Mar 12 12:59:10 PM PDT 24
Finished Mar 12 12:59:36 PM PDT 24
Peak memory 207016 kb
Host smart-6783771e-9125-4f51-9bb7-9de1dde4614f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993467185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3993467185
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1878237553
Short name T2076
Test name
Test status
Simulation time 64565802 ps
CPU time 1.24 seconds
Started Mar 12 12:45:57 PM PDT 24
Finished Mar 12 12:45:58 PM PDT 24
Peak memory 207108 kb
Host smart-3b494a7b-f5ee-4931-a8d3-3be6846ece99
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878237553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1878237553
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.238527646
Short name T2001
Test name
Test status
Simulation time 27261660 ps
CPU time 1.01 seconds
Started Mar 12 12:59:09 PM PDT 24
Finished Mar 12 12:59:11 PM PDT 24
Peak memory 206636 kb
Host smart-2e93b562-40da-423b-b72d-0fbd2789d966
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238527646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.238527646
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2274799618
Short name T2204
Test name
Test status
Simulation time 81303572 ps
CPU time 2.28 seconds
Started Mar 12 12:45:56 PM PDT 24
Finished Mar 12 12:45:59 PM PDT 24
Peak memory 216688 kb
Host smart-338105f1-eb82-4235-a3df-68e8fc8e3716
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274799618 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2274799618
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2295144338
Short name T2104
Test name
Test status
Simulation time 309340062 ps
CPU time 3.62 seconds
Started Mar 12 12:59:17 PM PDT 24
Finished Mar 12 12:59:21 PM PDT 24
Peak memory 217852 kb
Host smart-0055b5d6-244b-424b-bbf3-f7ccad5baa39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295144338 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2295144338
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2090210197
Short name T123
Test name
Test status
Simulation time 32828444 ps
CPU time 1.3 seconds
Started Mar 12 12:45:57 PM PDT 24
Finished Mar 12 12:45:59 PM PDT 24
Peak memory 207120 kb
Host smart-4e73c6a9-fae6-4dd6-8070-632012f7a09b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090210197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
090210197
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3135433177
Short name T120
Test name
Test status
Simulation time 119227797 ps
CPU time 2.15 seconds
Started Mar 12 01:01:23 PM PDT 24
Finished Mar 12 01:01:27 PM PDT 24
Peak memory 215176 kb
Host smart-c21e8ca2-adef-4958-993e-bf275f358c18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135433177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
135433177
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3373276816
Short name T2069
Test name
Test status
Simulation time 32380035 ps
CPU time 0.66 seconds
Started Mar 12 12:46:01 PM PDT 24
Finished Mar 12 12:46:01 PM PDT 24
Peak memory 203276 kb
Host smart-1260de13-c46e-42a5-b418-1bdb3ee9543d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373276816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
373276816
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.622507151
Short name T1984
Test name
Test status
Simulation time 13159934 ps
CPU time 0.72 seconds
Started Mar 12 12:59:13 PM PDT 24
Finished Mar 12 12:59:14 PM PDT 24
Peak memory 203388 kb
Host smart-42c0b694-1cf1-4c59-bc5f-afe2e02789f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622507151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.622507151
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2053177421
Short name T2013
Test name
Test status
Simulation time 63586519 ps
CPU time 1.28 seconds
Started Mar 12 01:01:34 PM PDT 24
Finished Mar 12 01:01:35 PM PDT 24
Peak memory 215088 kb
Host smart-fc0acfdf-5998-4cd9-819d-5cf0a3be187c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053177421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2053177421
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2952078452
Short name T134
Test name
Test status
Simulation time 65051517 ps
CPU time 1.26 seconds
Started Mar 12 12:45:57 PM PDT 24
Finished Mar 12 12:45:59 PM PDT 24
Peak memory 215276 kb
Host smart-b48477e7-f605-449b-b215-9c361f8d005d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952078452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2952078452
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3741632414
Short name T2068
Test name
Test status
Simulation time 10528558 ps
CPU time 0.72 seconds
Started Mar 12 12:59:17 PM PDT 24
Finished Mar 12 12:59:18 PM PDT 24
Peak memory 203340 kb
Host smart-c8b40b14-9787-43d0-9eb6-11ebfe3cfc08
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741632414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3741632414
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.795254980
Short name T2050
Test name
Test status
Simulation time 29606058 ps
CPU time 0.68 seconds
Started Mar 12 12:45:56 PM PDT 24
Finished Mar 12 12:45:57 PM PDT 24
Peak memory 203360 kb
Host smart-f297412d-91d6-4ff9-bdb7-df0c6e941d80
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795254980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.795254980
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.529103744
Short name T149
Test name
Test status
Simulation time 150857729 ps
CPU time 3.14 seconds
Started Mar 12 12:45:56 PM PDT 24
Finished Mar 12 12:45:59 PM PDT 24
Peak memory 215156 kb
Host smart-2b46457d-94aa-42e1-a52b-e9fc7d618eca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529103744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.529103744
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.787346863
Short name T153
Test name
Test status
Simulation time 134045591 ps
CPU time 2.96 seconds
Started Mar 12 12:59:12 PM PDT 24
Finished Mar 12 12:59:15 PM PDT 24
Peak memory 215368 kb
Host smart-a890abf7-687d-437c-a087-033fb036b81f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787346863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.787346863
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1055584286
Short name T174
Test name
Test status
Simulation time 263561831 ps
CPU time 3.75 seconds
Started Mar 12 12:45:56 PM PDT 24
Finished Mar 12 12:46:00 PM PDT 24
Peak memory 215548 kb
Host smart-8360944c-3a68-4234-9c91-01606a30b53c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055584286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
055584286
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.526614086
Short name T99
Test name
Test status
Simulation time 90954147 ps
CPU time 2.48 seconds
Started Mar 12 01:01:30 PM PDT 24
Finished Mar 12 01:01:33 PM PDT 24
Peak memory 215336 kb
Host smart-fc45279d-0493-4fc8-bfd6-48574bfba4e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526614086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.526614086
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2001070117
Short name T100
Test name
Test status
Simulation time 713033116 ps
CPU time 15.2 seconds
Started Mar 12 12:45:54 PM PDT 24
Finished Mar 12 12:46:09 PM PDT 24
Peak memory 215220 kb
Host smart-da702d33-3a43-4052-b4ae-b9e2400dec30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001070117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2001070117
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2974105522
Short name T179
Test name
Test status
Simulation time 539807148 ps
CPU time 12.99 seconds
Started Mar 12 01:01:34 PM PDT 24
Finished Mar 12 01:01:47 PM PDT 24
Peak memory 215360 kb
Host smart-5d4c09e9-ea52-4a48-823b-e598753056a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974105522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2974105522
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3822219194
Short name T2148
Test name
Test status
Simulation time 17658232 ps
CPU time 0.8 seconds
Started Mar 12 12:59:46 PM PDT 24
Finished Mar 12 12:59:47 PM PDT 24
Peak memory 203480 kb
Host smart-1c03ae11-50b5-4201-b24e-13983539cee1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822219194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3822219194
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.584550151
Short name T2051
Test name
Test status
Simulation time 14472801 ps
CPU time 0.75 seconds
Started Mar 12 12:46:26 PM PDT 24
Finished Mar 12 12:46:27 PM PDT 24
Peak memory 203496 kb
Host smart-4e1c45a6-9e1d-406a-ace2-96a9d6eca9df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584550151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.584550151
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2273126805
Short name T1985
Test name
Test status
Simulation time 20542442 ps
CPU time 0.72 seconds
Started Mar 12 12:46:27 PM PDT 24
Finished Mar 12 12:46:28 PM PDT 24
Peak memory 203432 kb
Host smart-1a64eb7c-671f-4d50-8eb6-d6dc3def0472
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273126805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
2273126805
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3746275500
Short name T1949
Test name
Test status
Simulation time 23914894 ps
CPU time 0.7 seconds
Started Mar 12 12:59:53 PM PDT 24
Finished Mar 12 12:59:54 PM PDT 24
Peak memory 203356 kb
Host smart-6256ec74-e116-42a0-9cd9-bb13070787af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746275500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3746275500
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2808825847
Short name T2028
Test name
Test status
Simulation time 16661895 ps
CPU time 0.73 seconds
Started Mar 12 12:46:28 PM PDT 24
Finished Mar 12 12:46:29 PM PDT 24
Peak memory 203396 kb
Host smart-02761301-0979-4832-9abb-50f589a8982e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808825847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2808825847
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.938184128
Short name T2046
Test name
Test status
Simulation time 43859355 ps
CPU time 0.74 seconds
Started Mar 12 12:59:45 PM PDT 24
Finished Mar 12 12:59:51 PM PDT 24
Peak memory 203400 kb
Host smart-f5df81e5-9e94-4256-83f7-60bec66d8858
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938184128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.938184128
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1378918065
Short name T2138
Test name
Test status
Simulation time 16098204 ps
CPU time 0.73 seconds
Started Mar 12 12:46:25 PM PDT 24
Finished Mar 12 12:46:26 PM PDT 24
Peak memory 203380 kb
Host smart-1c95c587-efee-4bde-b9b1-21d3699df319
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378918065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1378918065
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1614045827
Short name T2161
Test name
Test status
Simulation time 27926170 ps
CPU time 0.68 seconds
Started Mar 12 12:59:48 PM PDT 24
Finished Mar 12 12:59:48 PM PDT 24
Peak memory 203420 kb
Host smart-58265428-9f99-42ca-af6c-92aeca5095bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614045827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1614045827
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3947889993
Short name T1977
Test name
Test status
Simulation time 23989139 ps
CPU time 0.79 seconds
Started Mar 12 12:59:50 PM PDT 24
Finished Mar 12 12:59:51 PM PDT 24
Peak memory 203440 kb
Host smart-51327ba8-23a8-4545-8c10-543cf10512b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947889993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3947889993
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.934051063
Short name T2011
Test name
Test status
Simulation time 17883789 ps
CPU time 0.71 seconds
Started Mar 12 12:46:26 PM PDT 24
Finished Mar 12 12:46:27 PM PDT 24
Peak memory 203412 kb
Host smart-d836caaf-9dcc-447d-8560-e301c629ffd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934051063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.934051063
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1525832210
Short name T2080
Test name
Test status
Simulation time 44934442 ps
CPU time 0.7 seconds
Started Mar 12 12:46:27 PM PDT 24
Finished Mar 12 12:46:28 PM PDT 24
Peak memory 203524 kb
Host smart-3a494f4f-a3ba-4253-96b8-df70f1848437
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525832210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1525832210
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1969561499
Short name T1945
Test name
Test status
Simulation time 16961343 ps
CPU time 0.73 seconds
Started Mar 12 12:59:52 PM PDT 24
Finished Mar 12 12:59:53 PM PDT 24
Peak memory 203388 kb
Host smart-3f9df60e-6183-4be4-9848-6afcdc297bba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969561499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1969561499
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1284937169
Short name T2134
Test name
Test status
Simulation time 16075246 ps
CPU time 0.75 seconds
Started Mar 12 12:46:24 PM PDT 24
Finished Mar 12 12:46:26 PM PDT 24
Peak memory 203436 kb
Host smart-9160ab8e-59b4-4a1a-b8ab-304e1809c5b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284937169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1284937169
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2994310003
Short name T2077
Test name
Test status
Simulation time 37037709 ps
CPU time 0.78 seconds
Started Mar 12 12:59:38 PM PDT 24
Finished Mar 12 12:59:38 PM PDT 24
Peak memory 203348 kb
Host smart-d6d895ed-3051-4d3d-96bc-56e390f95cd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994310003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2994310003
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2176995463
Short name T2045
Test name
Test status
Simulation time 41878440 ps
CPU time 0.76 seconds
Started Mar 12 12:59:56 PM PDT 24
Finished Mar 12 12:59:57 PM PDT 24
Peak memory 203480 kb
Host smart-e9a2a1a2-78d2-4d4f-8da5-444bd0b9b3ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176995463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2176995463
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2257725062
Short name T1996
Test name
Test status
Simulation time 11459740 ps
CPU time 0.68 seconds
Started Mar 12 12:46:24 PM PDT 24
Finished Mar 12 12:46:31 PM PDT 24
Peak memory 203440 kb
Host smart-65ecaabb-3ffb-43cc-a66f-e6ccba11d0b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257725062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2257725062
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2100369437
Short name T1983
Test name
Test status
Simulation time 11893957 ps
CPU time 0.75 seconds
Started Mar 12 12:59:48 PM PDT 24
Finished Mar 12 12:59:48 PM PDT 24
Peak memory 203468 kb
Host smart-1fb1221d-d41a-44da-bb4d-24e5dcfa1f71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100369437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2100369437
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.474877605
Short name T2094
Test name
Test status
Simulation time 13249328 ps
CPU time 0.74 seconds
Started Mar 12 12:46:22 PM PDT 24
Finished Mar 12 12:46:23 PM PDT 24
Peak memory 203364 kb
Host smart-231ed9eb-deb9-4f7a-905c-cb48cadf3acb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474877605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.474877605
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1777538055
Short name T1957
Test name
Test status
Simulation time 13925645 ps
CPU time 0.71 seconds
Started Mar 12 12:59:50 PM PDT 24
Finished Mar 12 12:59:51 PM PDT 24
Peak memory 203464 kb
Host smart-4092630b-914c-4609-bad2-422776fd5d61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777538055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1777538055
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3307399675
Short name T2002
Test name
Test status
Simulation time 26858079 ps
CPU time 0.72 seconds
Started Mar 12 12:46:22 PM PDT 24
Finished Mar 12 12:46:24 PM PDT 24
Peak memory 203432 kb
Host smart-74a1f5d3-4616-4a16-b1b7-189fe4442f26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307399675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3307399675
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1661643651
Short name T130
Test name
Test status
Simulation time 766384547 ps
CPU time 8.81 seconds
Started Mar 12 12:59:24 PM PDT 24
Finished Mar 12 12:59:33 PM PDT 24
Peak memory 215272 kb
Host smart-ce41b1c7-8bb2-4a2d-898e-5cde26ad9fd7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661643651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1661643651
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2443871075
Short name T2177
Test name
Test status
Simulation time 206602227 ps
CPU time 15.05 seconds
Started Mar 12 12:45:56 PM PDT 24
Finished Mar 12 12:46:11 PM PDT 24
Peak memory 215348 kb
Host smart-1f0a1599-a75f-4bbb-998b-8433c085cc50
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443871075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2443871075
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1055471759
Short name T1953
Test name
Test status
Simulation time 1479452570 ps
CPU time 11.23 seconds
Started Mar 12 12:46:03 PM PDT 24
Finished Mar 12 12:46:15 PM PDT 24
Peak memory 207080 kb
Host smart-fd69aff2-f297-403f-b85c-b5aae33565c1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055471759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1055471759
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3767801396
Short name T2110
Test name
Test status
Simulation time 1396769745 ps
CPU time 23.37 seconds
Started Mar 12 12:59:13 PM PDT 24
Finished Mar 12 12:59:36 PM PDT 24
Peak memory 207064 kb
Host smart-be1e4167-05d8-40ae-a0bc-1496130932bc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767801396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3767801396
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1140591094
Short name T78
Test name
Test status
Simulation time 21721478 ps
CPU time 1.12 seconds
Started Mar 12 12:46:02 PM PDT 24
Finished Mar 12 12:46:04 PM PDT 24
Peak memory 215280 kb
Host smart-a649b90c-3710-478b-bb9f-0f786f3a67fe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140591094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1140591094
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.9045855
Short name T129
Test name
Test status
Simulation time 35038650 ps
CPU time 1.15 seconds
Started Mar 12 12:59:15 PM PDT 24
Finished Mar 12 12:59:16 PM PDT 24
Peak memory 206848 kb
Host smart-465018f9-40dd-4318-afdb-565bf7bc4b58
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9045855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_h
w_reset.9045855
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4037241500
Short name T2129
Test name
Test status
Simulation time 179998644 ps
CPU time 1.72 seconds
Started Mar 12 12:59:39 PM PDT 24
Finished Mar 12 12:59:41 PM PDT 24
Peak memory 215400 kb
Host smart-1a8c1a75-586b-487b-a872-0679801aa881
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037241500 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.4037241500
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4173510221
Short name T101
Test name
Test status
Simulation time 58440186 ps
CPU time 3.65 seconds
Started Mar 12 12:45:57 PM PDT 24
Finished Mar 12 12:46:01 PM PDT 24
Peak memory 217736 kb
Host smart-45a9feb9-743c-4519-afce-bd1472c8d074
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173510221 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.4173510221
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3058372683
Short name T131
Test name
Test status
Simulation time 76802609 ps
CPU time 1.29 seconds
Started Mar 12 12:59:15 PM PDT 24
Finished Mar 12 12:59:17 PM PDT 24
Peak memory 207156 kb
Host smart-ffca893b-93b4-4f41-881f-7e35c3f0ecbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058372683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
058372683
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3576543271
Short name T2178
Test name
Test status
Simulation time 29457232 ps
CPU time 1.88 seconds
Started Mar 12 12:45:56 PM PDT 24
Finished Mar 12 12:45:58 PM PDT 24
Peak memory 215308 kb
Host smart-c36d75c8-a410-4757-a13f-65100d12cab2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576543271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
576543271
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3714904230
Short name T1972
Test name
Test status
Simulation time 31635881 ps
CPU time 0.72 seconds
Started Mar 12 12:45:55 PM PDT 24
Finished Mar 12 12:45:56 PM PDT 24
Peak memory 203432 kb
Host smart-c24f0b8a-8ddc-4a8f-9ac1-ad6209309353
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714904230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
714904230
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.906633708
Short name T1986
Test name
Test status
Simulation time 129418387 ps
CPU time 0.71 seconds
Started Mar 12 01:01:30 PM PDT 24
Finished Mar 12 01:01:31 PM PDT 24
Peak memory 203332 kb
Host smart-694e92ec-18f6-41ef-aad4-d6cca0c67d20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906633708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.906633708
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1397467794
Short name T119
Test name
Test status
Simulation time 105106017 ps
CPU time 1.76 seconds
Started Mar 12 12:46:04 PM PDT 24
Finished Mar 12 12:46:05 PM PDT 24
Peak memory 215348 kb
Host smart-fff49636-83fb-448b-beda-12bb6ed2355e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397467794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1397467794
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.450594790
Short name T2075
Test name
Test status
Simulation time 122030008 ps
CPU time 1.62 seconds
Started Mar 12 12:59:12 PM PDT 24
Finished Mar 12 12:59:14 PM PDT 24
Peak memory 215364 kb
Host smart-cff0463c-c30c-4263-ab79-1bbc03fd8baf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450594790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.450594790
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2564396080
Short name T1950
Test name
Test status
Simulation time 68320314 ps
CPU time 0.63 seconds
Started Mar 12 12:59:20 PM PDT 24
Finished Mar 12 12:59:20 PM PDT 24
Peak memory 203344 kb
Host smart-acdb34fe-38cb-4c43-8cf2-c8124fa4d9af
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564396080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2564396080
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2733693030
Short name T2174
Test name
Test status
Simulation time 19995271 ps
CPU time 0.64 seconds
Started Mar 12 12:45:57 PM PDT 24
Finished Mar 12 12:45:58 PM PDT 24
Peak memory 203268 kb
Host smart-c4598f97-dfd3-4e21-ab7c-467f2e20d59e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733693030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2733693030
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1355690843
Short name T2035
Test name
Test status
Simulation time 162506861 ps
CPU time 4.26 seconds
Started Mar 12 12:45:58 PM PDT 24
Finished Mar 12 12:46:02 PM PDT 24
Peak memory 215256 kb
Host smart-1de055da-5f76-491f-80cd-264a62cdef6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355690843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1355690843
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1856521989
Short name T1982
Test name
Test status
Simulation time 223047409 ps
CPU time 1.89 seconds
Started Mar 12 12:59:21 PM PDT 24
Finished Mar 12 12:59:22 PM PDT 24
Peak memory 215280 kb
Host smart-b0949fa5-2663-44f7-a2ab-9eb6e915fedc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856521989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1856521989
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2915699161
Short name T2018
Test name
Test status
Simulation time 205450687 ps
CPU time 2.75 seconds
Started Mar 12 12:45:56 PM PDT 24
Finished Mar 12 12:45:59 PM PDT 24
Peak memory 215696 kb
Host smart-09316263-4f8c-4913-9eac-2cf4e76ece01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915699161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
915699161
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1023465509
Short name T2180
Test name
Test status
Simulation time 1780197430 ps
CPU time 15.01 seconds
Started Mar 12 12:45:55 PM PDT 24
Finished Mar 12 12:46:10 PM PDT 24
Peak memory 215340 kb
Host smart-25fd22cf-9057-429b-a086-e30e4d9637b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023465509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1023465509
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.78793312
Short name T2054
Test name
Test status
Simulation time 1675131193 ps
CPU time 13.94 seconds
Started Mar 12 12:59:13 PM PDT 24
Finished Mar 12 12:59:27 PM PDT 24
Peak memory 215312 kb
Host smart-4c366cb3-3ee7-46b2-8578-147544125291
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78793312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_t
l_intg_err.78793312
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3380436914
Short name T2009
Test name
Test status
Simulation time 15750822 ps
CPU time 0.7 seconds
Started Mar 12 12:46:23 PM PDT 24
Finished Mar 12 12:46:24 PM PDT 24
Peak memory 203432 kb
Host smart-9a36a442-dc39-4567-9672-93eccc76da0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380436914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3380436914
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3780033143
Short name T2133
Test name
Test status
Simulation time 18683646 ps
CPU time 0.81 seconds
Started Mar 12 12:59:46 PM PDT 24
Finished Mar 12 12:59:47 PM PDT 24
Peak memory 203368 kb
Host smart-5e70a311-1866-4d49-a57f-d892699b5546
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780033143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3780033143
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2130658491
Short name T1955
Test name
Test status
Simulation time 24646832 ps
CPU time 0.71 seconds
Started Mar 12 12:46:28 PM PDT 24
Finished Mar 12 12:46:30 PM PDT 24
Peak memory 203392 kb
Host smart-b311a885-8c88-4497-bee8-1fa0fe269059
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130658491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2130658491
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2815234669
Short name T1980
Test name
Test status
Simulation time 37126968 ps
CPU time 0.69 seconds
Started Mar 12 12:59:52 PM PDT 24
Finished Mar 12 12:59:54 PM PDT 24
Peak memory 203384 kb
Host smart-da3bd5d9-30fe-4be5-b8f5-34fcbe874508
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815234669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2815234669
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2032155287
Short name T1942
Test name
Test status
Simulation time 15992046 ps
CPU time 0.76 seconds
Started Mar 12 12:46:25 PM PDT 24
Finished Mar 12 12:46:27 PM PDT 24
Peak memory 203428 kb
Host smart-77b9d5c7-2d45-4377-9c2f-286893b6e18b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032155287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2032155287
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2431576346
Short name T2120
Test name
Test status
Simulation time 19360669 ps
CPU time 0.75 seconds
Started Mar 12 12:59:45 PM PDT 24
Finished Mar 12 12:59:46 PM PDT 24
Peak memory 203488 kb
Host smart-34fbc011-c99f-4699-9bfd-2de7c5803197
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431576346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2431576346
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2393790112
Short name T1947
Test name
Test status
Simulation time 17254053 ps
CPU time 0.65 seconds
Started Mar 12 12:59:36 PM PDT 24
Finished Mar 12 12:59:37 PM PDT 24
Peak memory 203316 kb
Host smart-1737d901-35dc-475b-ad8b-d4b0be67be4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393790112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2393790112
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3410368458
Short name T2043
Test name
Test status
Simulation time 18181567 ps
CPU time 0.77 seconds
Started Mar 12 12:46:25 PM PDT 24
Finished Mar 12 12:46:27 PM PDT 24
Peak memory 203436 kb
Host smart-e88105f2-41a1-4972-ac8c-26444b55c40c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410368458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3410368458
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2636341917
Short name T1960
Test name
Test status
Simulation time 12733697 ps
CPU time 0.8 seconds
Started Mar 12 12:59:54 PM PDT 24
Finished Mar 12 12:59:55 PM PDT 24
Peak memory 203376 kb
Host smart-a0707c96-8f1e-43f5-a61e-5d2514b080b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636341917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2636341917
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3636486582
Short name T2072
Test name
Test status
Simulation time 12501623 ps
CPU time 0.73 seconds
Started Mar 12 12:46:25 PM PDT 24
Finished Mar 12 12:46:26 PM PDT 24
Peak memory 203496 kb
Host smart-6fc059bd-6e9a-40bf-a952-fdb1fa349f59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636486582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3636486582
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1764004891
Short name T2192
Test name
Test status
Simulation time 19663110 ps
CPU time 0.76 seconds
Started Mar 12 12:46:25 PM PDT 24
Finished Mar 12 12:46:26 PM PDT 24
Peak memory 203492 kb
Host smart-c17581a5-fa40-498b-ada8-352fe08ef982
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764004891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1764004891
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2152978949
Short name T2109
Test name
Test status
Simulation time 42049539 ps
CPU time 0.69 seconds
Started Mar 12 12:59:37 PM PDT 24
Finished Mar 12 12:59:38 PM PDT 24
Peak memory 203376 kb
Host smart-24f8a6b6-f964-4b71-8c03-c48ad405dbd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152978949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2152978949
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1176355723
Short name T1962
Test name
Test status
Simulation time 27061212 ps
CPU time 0.73 seconds
Started Mar 12 12:46:24 PM PDT 24
Finished Mar 12 12:46:26 PM PDT 24
Peak memory 203504 kb
Host smart-dbcdc263-f57f-4db2-b7fb-4d07868d50c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176355723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1176355723
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.562837973
Short name T2157
Test name
Test status
Simulation time 13838042 ps
CPU time 0.76 seconds
Started Mar 12 12:59:57 PM PDT 24
Finished Mar 12 12:59:58 PM PDT 24
Peak memory 203512 kb
Host smart-ab258936-3bb3-4b4d-9149-ec664a0257d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562837973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.562837973
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1007298249
Short name T2209
Test name
Test status
Simulation time 32162421 ps
CPU time 0.68 seconds
Started Mar 12 12:46:24 PM PDT 24
Finished Mar 12 12:46:26 PM PDT 24
Peak memory 203456 kb
Host smart-4fd1c155-4f21-4970-babd-d734617197d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007298249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1007298249
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.212703808
Short name T1974
Test name
Test status
Simulation time 43121509 ps
CPU time 0.71 seconds
Started Mar 12 12:59:56 PM PDT 24
Finished Mar 12 12:59:57 PM PDT 24
Peak memory 203400 kb
Host smart-8ac2e787-a710-4d51-85c5-ed01c3513208
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212703808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.212703808
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1314551457
Short name T2126
Test name
Test status
Simulation time 17911574 ps
CPU time 0.81 seconds
Started Mar 12 12:59:46 PM PDT 24
Finished Mar 12 12:59:47 PM PDT 24
Peak memory 203408 kb
Host smart-c4355124-2f18-41f7-a126-eaf6b5e78cdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314551457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
1314551457
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.358349679
Short name T2214
Test name
Test status
Simulation time 42448242 ps
CPU time 0.76 seconds
Started Mar 12 12:46:25 PM PDT 24
Finished Mar 12 12:46:27 PM PDT 24
Peak memory 203452 kb
Host smart-6b02c4aa-a7f7-41f1-9b31-862ee1de6d4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358349679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.358349679
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.531862051
Short name T2183
Test name
Test status
Simulation time 35171920 ps
CPU time 0.69 seconds
Started Mar 12 12:46:23 PM PDT 24
Finished Mar 12 12:46:24 PM PDT 24
Peak memory 203368 kb
Host smart-858580bc-dc52-4778-bcae-58fa3e1048c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531862051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.531862051
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.638232314
Short name T2029
Test name
Test status
Simulation time 14778736 ps
CPU time 0.71 seconds
Started Mar 12 12:59:52 PM PDT 24
Finished Mar 12 12:59:54 PM PDT 24
Peak memory 203416 kb
Host smart-4c01055b-e0ac-4c8a-969d-a812f155b2be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638232314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.638232314
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2035177626
Short name T2014
Test name
Test status
Simulation time 93869479 ps
CPU time 2.72 seconds
Started Mar 12 12:59:38 PM PDT 24
Finished Mar 12 12:59:41 PM PDT 24
Peak memory 216676 kb
Host smart-914a27ce-b07d-4077-ba00-a2319affb276
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035177626 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2035177626
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2236349046
Short name T112
Test name
Test status
Simulation time 70588722 ps
CPU time 2.56 seconds
Started Mar 12 12:46:03 PM PDT 24
Finished Mar 12 12:46:06 PM PDT 24
Peak memory 216584 kb
Host smart-21359bda-c422-49ad-b43d-1aac6f31e9d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236349046 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2236349046
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1800233770
Short name T124
Test name
Test status
Simulation time 185508856 ps
CPU time 2.83 seconds
Started Mar 12 12:59:38 PM PDT 24
Finished Mar 12 12:59:41 PM PDT 24
Peak memory 215240 kb
Host smart-4b411a5b-9da9-4f33-989c-0d692e44c973
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800233770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
800233770
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3822124046
Short name T2106
Test name
Test status
Simulation time 157102837 ps
CPU time 2.48 seconds
Started Mar 12 12:46:03 PM PDT 24
Finished Mar 12 12:46:06 PM PDT 24
Peak memory 215272 kb
Host smart-590cbcc8-93fe-4a34-b84a-bb2ca24b76a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822124046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
822124046
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1271024528
Short name T2101
Test name
Test status
Simulation time 96130005 ps
CPU time 0.69 seconds
Started Mar 12 12:45:58 PM PDT 24
Finished Mar 12 12:45:59 PM PDT 24
Peak memory 203476 kb
Host smart-bd4c7a9c-7c3b-4e18-998e-5deda9600923
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271024528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
271024528
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3012364682
Short name T1970
Test name
Test status
Simulation time 15609221 ps
CPU time 0.7 seconds
Started Mar 12 12:59:38 PM PDT 24
Finished Mar 12 12:59:39 PM PDT 24
Peak memory 203352 kb
Host smart-b1a312fc-ad42-40a3-b19a-02074d4dc9d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012364682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
012364682
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2844273690
Short name T2061
Test name
Test status
Simulation time 226044485 ps
CPU time 1.84 seconds
Started Mar 12 12:45:59 PM PDT 24
Finished Mar 12 12:46:01 PM PDT 24
Peak memory 207096 kb
Host smart-169849d0-1577-47e6-b548-affbf349eb08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844273690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2844273690
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4016540133
Short name T2003
Test name
Test status
Simulation time 82000660 ps
CPU time 2.75 seconds
Started Mar 12 12:59:35 PM PDT 24
Finished Mar 12 12:59:38 PM PDT 24
Peak memory 215308 kb
Host smart-62bc41d2-8885-4b40-afd1-3c05f77287af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016540133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.4016540133
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2404779825
Short name T2217
Test name
Test status
Simulation time 280692807 ps
CPU time 2.05 seconds
Started Mar 12 12:45:59 PM PDT 24
Finished Mar 12 12:46:02 PM PDT 24
Peak memory 215468 kb
Host smart-5765e4be-30bb-4406-98cb-b33428a48c82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404779825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
404779825
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2659526543
Short name T2063
Test name
Test status
Simulation time 288407864 ps
CPU time 2.59 seconds
Started Mar 12 12:59:33 PM PDT 24
Finished Mar 12 12:59:35 PM PDT 24
Peak memory 215424 kb
Host smart-032acb3b-25c0-44d9-bd33-162e57937e45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659526543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
659526543
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1291880637
Short name T2036
Test name
Test status
Simulation time 3987376026 ps
CPU time 23.28 seconds
Started Mar 12 12:59:18 PM PDT 24
Finished Mar 12 12:59:41 PM PDT 24
Peak memory 215716 kb
Host smart-ff7a434c-164c-4633-b4c8-23c73ceefea3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291880637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1291880637
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3149103171
Short name T2115
Test name
Test status
Simulation time 1564124029 ps
CPU time 18.03 seconds
Started Mar 12 12:45:55 PM PDT 24
Finished Mar 12 12:46:13 PM PDT 24
Peak memory 215348 kb
Host smart-8470c681-4710-4f2f-a427-18e922d9a93f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149103171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3149103171
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1145374707
Short name T2062
Test name
Test status
Simulation time 240279494 ps
CPU time 3.74 seconds
Started Mar 12 12:45:59 PM PDT 24
Finished Mar 12 12:46:03 PM PDT 24
Peak memory 217032 kb
Host smart-c73a064c-8464-4888-8c8e-f8147fe033d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145374707 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1145374707
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3088610586
Short name T2078
Test name
Test status
Simulation time 87090198 ps
CPU time 1.64 seconds
Started Mar 12 12:59:34 PM PDT 24
Finished Mar 12 12:59:35 PM PDT 24
Peak memory 215356 kb
Host smart-b9aef986-3b7d-4269-9301-2465d4d1629a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088610586 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3088610586
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.15578385
Short name T2179
Test name
Test status
Simulation time 598787513 ps
CPU time 1.35 seconds
Started Mar 12 12:46:02 PM PDT 24
Finished Mar 12 12:46:05 PM PDT 24
Peak memory 207092 kb
Host smart-ed1f9276-2f84-4b50-ad07-45ae55913425
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15578385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.15578385
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2128877754
Short name T2117
Test name
Test status
Simulation time 534805754 ps
CPU time 2.78 seconds
Started Mar 12 12:59:20 PM PDT 24
Finished Mar 12 12:59:23 PM PDT 24
Peak memory 215272 kb
Host smart-bc60e1e0-17a0-401e-bef2-fa65267b0c71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128877754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
128877754
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.354631636
Short name T1951
Test name
Test status
Simulation time 45847721 ps
CPU time 0.75 seconds
Started Mar 12 12:46:00 PM PDT 24
Finished Mar 12 12:46:01 PM PDT 24
Peak memory 203428 kb
Host smart-26f6fead-199c-4ea5-b1d4-a3d9db416bb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354631636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.354631636
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3557460229
Short name T2066
Test name
Test status
Simulation time 15688110 ps
CPU time 0.73 seconds
Started Mar 12 12:59:17 PM PDT 24
Finished Mar 12 12:59:18 PM PDT 24
Peak memory 203420 kb
Host smart-222e6595-7c77-4d77-9883-51d33cd28114
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557460229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
557460229
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2822698478
Short name T2215
Test name
Test status
Simulation time 378377619 ps
CPU time 2.7 seconds
Started Mar 12 12:45:57 PM PDT 24
Finished Mar 12 12:46:00 PM PDT 24
Peak memory 215328 kb
Host smart-55de973f-c205-41e5-bae3-78f08e3f64e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822698478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2822698478
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3243300794
Short name T2181
Test name
Test status
Simulation time 2620772040 ps
CPU time 3.19 seconds
Started Mar 12 12:59:36 PM PDT 24
Finished Mar 12 12:59:40 PM PDT 24
Peak memory 215276 kb
Host smart-16b04117-deb1-4c90-8c42-5ba96421d1cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243300794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3243300794
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2081172150
Short name T104
Test name
Test status
Simulation time 57589037 ps
CPU time 2.04 seconds
Started Mar 12 12:59:48 PM PDT 24
Finished Mar 12 12:59:50 PM PDT 24
Peak memory 216524 kb
Host smart-b281792c-b3bb-4f9a-ba74-e1db1eb189af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081172150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
081172150
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.600747750
Short name T2067
Test name
Test status
Simulation time 100318129 ps
CPU time 2.87 seconds
Started Mar 12 12:45:56 PM PDT 24
Finished Mar 12 12:45:59 PM PDT 24
Peak memory 215448 kb
Host smart-62afcfb8-c25f-4335-b797-586039d691b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600747750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.600747750
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1667511717
Short name T2015
Test name
Test status
Simulation time 471986892 ps
CPU time 8.45 seconds
Started Mar 12 12:59:38 PM PDT 24
Finished Mar 12 12:59:47 PM PDT 24
Peak memory 215628 kb
Host smart-6e3e8f84-473b-47a9-bf34-adeab19dfe60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667511717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1667511717
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.861613183
Short name T94
Test name
Test status
Simulation time 1270401043 ps
CPU time 9.11 seconds
Started Mar 12 12:45:57 PM PDT 24
Finished Mar 12 12:46:07 PM PDT 24
Peak memory 215272 kb
Host smart-8e674dbc-4f11-4d12-9acf-18795037c9cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861613183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.861613183
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3915894219
Short name T2027
Test name
Test status
Simulation time 720499040 ps
CPU time 1.72 seconds
Started Mar 12 12:46:09 PM PDT 24
Finished Mar 12 12:46:14 PM PDT 24
Peak memory 215372 kb
Host smart-aee14c94-a68d-4dc4-a85c-3a61fb1c5dc3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915894219 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3915894219
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.66851662
Short name T1989
Test name
Test status
Simulation time 40986438 ps
CPU time 2.76 seconds
Started Mar 12 12:59:22 PM PDT 24
Finished Mar 12 12:59:25 PM PDT 24
Peak memory 216456 kb
Host smart-347174ef-5843-4d46-9838-ff0f7b4559d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66851662 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.66851662
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2630899938
Short name T2130
Test name
Test status
Simulation time 82052746 ps
CPU time 2.65 seconds
Started Mar 12 12:46:09 PM PDT 24
Finished Mar 12 12:46:14 PM PDT 24
Peak memory 215336 kb
Host smart-e3d18774-201a-43d7-916f-7407a31804c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630899938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
630899938
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.611685045
Short name T1965
Test name
Test status
Simulation time 20300243 ps
CPU time 1.21 seconds
Started Mar 12 12:59:33 PM PDT 24
Finished Mar 12 12:59:34 PM PDT 24
Peak memory 207028 kb
Host smart-05c0d811-6a86-4f90-8180-f1a265ffad0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611685045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.611685045
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2404559864
Short name T2090
Test name
Test status
Simulation time 18110383 ps
CPU time 0.72 seconds
Started Mar 12 12:59:43 PM PDT 24
Finished Mar 12 12:59:44 PM PDT 24
Peak memory 203496 kb
Host smart-43d21399-be8b-47b0-b04d-986a25543958
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404559864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
404559864
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.327909509
Short name T1978
Test name
Test status
Simulation time 19587415 ps
CPU time 0.8 seconds
Started Mar 12 12:46:07 PM PDT 24
Finished Mar 12 12:46:08 PM PDT 24
Peak memory 203488 kb
Host smart-a229195f-93a5-498f-9cdd-6628c982925d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327909509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.327909509
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1456599361
Short name T2038
Test name
Test status
Simulation time 444826844 ps
CPU time 4.72 seconds
Started Mar 12 12:46:05 PM PDT 24
Finished Mar 12 12:46:10 PM PDT 24
Peak memory 215300 kb
Host smart-2b8231ba-7367-486e-b5f6-a8a48b2660a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456599361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1456599361
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2293955004
Short name T152
Test name
Test status
Simulation time 210653842 ps
CPU time 4.37 seconds
Started Mar 12 12:59:48 PM PDT 24
Finished Mar 12 12:59:53 PM PDT 24
Peak memory 215256 kb
Host smart-53352545-37db-47b6-b6f7-9c174f833197
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293955004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2293955004
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2855775978
Short name T105
Test name
Test status
Simulation time 148798861 ps
CPU time 3.7 seconds
Started Mar 12 12:59:25 PM PDT 24
Finished Mar 12 12:59:28 PM PDT 24
Peak memory 215572 kb
Host smart-93f0d1bc-93bc-4887-a603-ca0cf5cb4dbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855775978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
855775978
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.639800421
Short name T2081
Test name
Test status
Simulation time 155901124 ps
CPU time 3.22 seconds
Started Mar 12 12:45:57 PM PDT 24
Finished Mar 12 12:46:00 PM PDT 24
Peak memory 216808 kb
Host smart-a4b8ec48-2ad2-4610-bed5-03804354a835
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639800421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.639800421
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1172295788
Short name T2085
Test name
Test status
Simulation time 730808310 ps
CPU time 6.76 seconds
Started Mar 12 12:45:57 PM PDT 24
Finished Mar 12 12:46:04 PM PDT 24
Peak memory 215312 kb
Host smart-e8969a7e-516f-4f3c-ba41-5da482c51fa4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172295788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1172295788
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1854435754
Short name T2194
Test name
Test status
Simulation time 224669482 ps
CPU time 12.2 seconds
Started Mar 12 12:59:26 PM PDT 24
Finished Mar 12 12:59:39 PM PDT 24
Peak memory 215244 kb
Host smart-0ee1e64b-9608-4285-9d89-5f0d5cf4f8b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854435754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1854435754
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2270195698
Short name T2171
Test name
Test status
Simulation time 41215022 ps
CPU time 3.07 seconds
Started Mar 12 12:59:47 PM PDT 24
Finished Mar 12 12:59:51 PM PDT 24
Peak memory 216616 kb
Host smart-391752d6-2acd-4bab-b691-07bd8fb9e64d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270195698 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2270195698
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2374642295
Short name T2188
Test name
Test status
Simulation time 137328285 ps
CPU time 3.95 seconds
Started Mar 12 12:46:06 PM PDT 24
Finished Mar 12 12:46:11 PM PDT 24
Peak memory 217524 kb
Host smart-cd669ffe-bc73-4016-a633-13181d158dc0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374642295 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2374642295
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2177760869
Short name T2005
Test name
Test status
Simulation time 71890523 ps
CPU time 2.13 seconds
Started Mar 12 12:59:22 PM PDT 24
Finished Mar 12 12:59:24 PM PDT 24
Peak memory 215152 kb
Host smart-663930a0-5730-4d7f-8b32-a9419d6bcc15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177760869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
177760869
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3614366317
Short name T2118
Test name
Test status
Simulation time 380336275 ps
CPU time 2.41 seconds
Started Mar 12 12:46:08 PM PDT 24
Finished Mar 12 12:46:14 PM PDT 24
Peak memory 207012 kb
Host smart-2a19e685-c755-4463-b241-807b5c19fac5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614366317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
614366317
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2140703022
Short name T2088
Test name
Test status
Simulation time 73821788 ps
CPU time 0.74 seconds
Started Mar 12 12:59:33 PM PDT 24
Finished Mar 12 12:59:34 PM PDT 24
Peak memory 202900 kb
Host smart-82c9f559-2fce-4613-bdcd-1618df1b76dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140703022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
140703022
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.928453197
Short name T2210
Test name
Test status
Simulation time 15435949 ps
CPU time 0.73 seconds
Started Mar 12 12:46:07 PM PDT 24
Finished Mar 12 12:46:10 PM PDT 24
Peak memory 203384 kb
Host smart-ad9c8c3b-b966-4494-992b-340bfe030ad5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928453197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.928453197
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3305789124
Short name T1952
Test name
Test status
Simulation time 60433609 ps
CPU time 3.92 seconds
Started Mar 12 12:46:07 PM PDT 24
Finished Mar 12 12:46:12 PM PDT 24
Peak memory 215532 kb
Host smart-f6c211cc-5a9e-4f36-bb9c-96415a66fc79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305789124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3305789124
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3843231977
Short name T2021
Test name
Test status
Simulation time 485006759 ps
CPU time 4.18 seconds
Started Mar 12 12:59:40 PM PDT 24
Finished Mar 12 12:59:45 PM PDT 24
Peak memory 207104 kb
Host smart-383b7662-f796-4206-8eb1-756fb1ae5805
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843231977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3843231977
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.229492463
Short name T2116
Test name
Test status
Simulation time 228253597 ps
CPU time 5.63 seconds
Started Mar 12 12:59:33 PM PDT 24
Finished Mar 12 12:59:39 PM PDT 24
Peak memory 215520 kb
Host smart-cd731ff3-943a-4773-b6b6-75c93fb9fdc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229492463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.229492463
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2927201044
Short name T102
Test name
Test status
Simulation time 541666363 ps
CPU time 3.38 seconds
Started Mar 12 12:46:06 PM PDT 24
Finished Mar 12 12:46:10 PM PDT 24
Peak memory 215592 kb
Host smart-64b199c7-c71e-4a73-98e7-8bc3513c128f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927201044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
927201044
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2942600433
Short name T2091
Test name
Test status
Simulation time 724594626 ps
CPU time 18.38 seconds
Started Mar 12 12:59:35 PM PDT 24
Finished Mar 12 12:59:54 PM PDT 24
Peak memory 215300 kb
Host smart-51f4a505-1d3f-4553-bb04-9e802cac7351
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942600433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2942600433
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3956582527
Short name T2125
Test name
Test status
Simulation time 413133690 ps
CPU time 11.03 seconds
Started Mar 12 12:46:07 PM PDT 24
Finished Mar 12 12:46:19 PM PDT 24
Peak memory 215672 kb
Host smart-82813078-8d3e-4fce-95e1-c330aa116679
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956582527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3956582527
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.240518321
Short name T2196
Test name
Test status
Simulation time 84311478 ps
CPU time 2.73 seconds
Started Mar 12 12:59:16 PM PDT 24
Finished Mar 12 12:59:19 PM PDT 24
Peak memory 216468 kb
Host smart-5ff2bfce-750f-4e8b-901b-36f0ddab11a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240518321 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.240518321
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3400049828
Short name T2132
Test name
Test status
Simulation time 228998842 ps
CPU time 1.81 seconds
Started Mar 12 12:46:06 PM PDT 24
Finished Mar 12 12:46:08 PM PDT 24
Peak memory 215288 kb
Host smart-b4363a73-a7e5-4ad2-9c6d-e33fada64e75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400049828 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3400049828
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3495936399
Short name T2098
Test name
Test status
Simulation time 30679188 ps
CPU time 1.86 seconds
Started Mar 12 12:59:26 PM PDT 24
Finished Mar 12 12:59:28 PM PDT 24
Peak memory 215308 kb
Host smart-1b3692d2-0061-436b-8b78-5c74271dbfa7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495936399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
495936399
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.4165162564
Short name T2173
Test name
Test status
Simulation time 123809256 ps
CPU time 1.36 seconds
Started Mar 12 12:46:07 PM PDT 24
Finished Mar 12 12:46:12 PM PDT 24
Peak memory 215312 kb
Host smart-40514a28-6ddf-4793-a6fb-604a79d3c9bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165162564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.4
165162564
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2173642591
Short name T2092
Test name
Test status
Simulation time 13434243 ps
CPU time 0.8 seconds
Started Mar 12 12:46:07 PM PDT 24
Finished Mar 12 12:46:09 PM PDT 24
Peak memory 203408 kb
Host smart-0711383e-bb03-4460-9b4c-f0e59ff396cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173642591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
173642591
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.4100383245
Short name T2060
Test name
Test status
Simulation time 24567419 ps
CPU time 0.72 seconds
Started Mar 12 12:59:42 PM PDT 24
Finished Mar 12 12:59:43 PM PDT 24
Peak memory 203440 kb
Host smart-4fe8daed-4641-415b-b7a9-81996c375c3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100383245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.4
100383245
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2835615096
Short name T2083
Test name
Test status
Simulation time 69598532 ps
CPU time 1.83 seconds
Started Mar 12 12:59:33 PM PDT 24
Finished Mar 12 12:59:35 PM PDT 24
Peak memory 214884 kb
Host smart-1084d247-8ed8-4d10-a0a9-0d6bc9a5a83b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835615096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2835615096
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3681455884
Short name T1959
Test name
Test status
Simulation time 53272480 ps
CPU time 2.05 seconds
Started Mar 12 12:46:07 PM PDT 24
Finished Mar 12 12:46:09 PM PDT 24
Peak memory 215324 kb
Host smart-883baa05-331d-419a-8200-c873eecbb13c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681455884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3681455884
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1301674823
Short name T2151
Test name
Test status
Simulation time 62797243 ps
CPU time 3.94 seconds
Started Mar 12 12:46:07 PM PDT 24
Finished Mar 12 12:46:13 PM PDT 24
Peak memory 215476 kb
Host smart-15bca05a-1c3f-44ff-9e2d-3979acf0dec2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301674823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
301674823
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1407547817
Short name T108
Test name
Test status
Simulation time 93185285 ps
CPU time 2.42 seconds
Started Mar 12 12:59:20 PM PDT 24
Finished Mar 12 12:59:22 PM PDT 24
Peak memory 215488 kb
Host smart-b93c8f0b-32dc-4a1d-a666-1bc8774fe208
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407547817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
407547817
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3124150646
Short name T2221
Test name
Test status
Simulation time 579301479 ps
CPU time 14.39 seconds
Started Mar 12 12:46:06 PM PDT 24
Finished Mar 12 12:46:21 PM PDT 24
Peak memory 215296 kb
Host smart-b5814fb5-5e36-40bc-b9f2-19af421637a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124150646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3124150646
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.4192764280
Short name T2205
Test name
Test status
Simulation time 196787306 ps
CPU time 12.53 seconds
Started Mar 12 12:59:46 PM PDT 24
Finished Mar 12 12:59:58 PM PDT 24
Peak memory 215352 kb
Host smart-0a7e19fe-67e5-4409-ba22-1e17b4b40331
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192764280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.4192764280
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2803331314
Short name T1221
Test name
Test status
Simulation time 40469751 ps
CPU time 0.77 seconds
Started Mar 12 03:04:59 PM PDT 24
Finished Mar 12 03:05:01 PM PDT 24
Peak memory 204792 kb
Host smart-02b22fbd-1106-427e-9382-3f376b4727d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803331314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
803331314
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.794627012
Short name T1010
Test name
Test status
Simulation time 51696066 ps
CPU time 0.69 seconds
Started Mar 12 01:10:17 PM PDT 24
Finished Mar 12 01:10:19 PM PDT 24
Peak memory 204232 kb
Host smart-61d870e7-9a6b-45a3-9a50-8c7adb9e9774
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794627012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.794627012
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1488129133
Short name T790
Test name
Test status
Simulation time 941378897 ps
CPU time 5.27 seconds
Started Mar 12 01:10:06 PM PDT 24
Finished Mar 12 01:10:11 PM PDT 24
Peak memory 233036 kb
Host smart-69afbf7e-68c7-46e2-aa76-8fac0b47021e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488129133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1488129133
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.500170773
Short name T242
Test name
Test status
Simulation time 7042022116 ps
CPU time 6.62 seconds
Started Mar 12 03:04:53 PM PDT 24
Finished Mar 12 03:04:59 PM PDT 24
Peak memory 219604 kb
Host smart-b30053c6-5b14-427f-a0fd-11e2ad9aef50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500170773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.500170773
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.826881036
Short name T1641
Test name
Test status
Simulation time 323926063 ps
CPU time 0.79 seconds
Started Mar 12 03:04:43 PM PDT 24
Finished Mar 12 03:04:45 PM PDT 24
Peak memory 205960 kb
Host smart-19c33d6b-52c6-4301-87bc-2ab5d7e32527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826881036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.826881036
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.937240046
Short name T1543
Test name
Test status
Simulation time 50914814 ps
CPU time 0.75 seconds
Started Mar 12 01:10:09 PM PDT 24
Finished Mar 12 01:10:10 PM PDT 24
Peak memory 205920 kb
Host smart-d6ec1c4a-cbba-4815-b632-cff3fdbe8444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937240046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.937240046
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.1939999677
Short name T1519
Test name
Test status
Simulation time 444813385238 ps
CPU time 236.63 seconds
Started Mar 12 01:10:09 PM PDT 24
Finished Mar 12 01:14:06 PM PDT 24
Peak memory 265208 kb
Host smart-cfe6bf5e-599e-4eda-9f63-724c90f1640c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939999677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1939999677
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3437969673
Short name T1256
Test name
Test status
Simulation time 4526685810 ps
CPU time 60.13 seconds
Started Mar 12 03:04:51 PM PDT 24
Finished Mar 12 03:05:52 PM PDT 24
Peak memory 255676 kb
Host smart-f8f850c8-2bfc-4642-a928-cdc0e881b324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437969673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3437969673
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3941227437
Short name T639
Test name
Test status
Simulation time 41856798927 ps
CPU time 41.7 seconds
Started Mar 12 01:10:18 PM PDT 24
Finished Mar 12 01:11:00 PM PDT 24
Peak memory 248792 kb
Host smart-98a63f97-8dc8-4b41-a0fb-2031b21ade48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941227437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3941227437
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3819147414
Short name T1309
Test name
Test status
Simulation time 156123322689 ps
CPU time 303.53 seconds
Started Mar 12 01:10:15 PM PDT 24
Finished Mar 12 01:15:19 PM PDT 24
Peak memory 256604 kb
Host smart-f5a15955-4c7c-4e8d-91d3-9f9076e6ea18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819147414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3819147414
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1713018937
Short name T1312
Test name
Test status
Simulation time 740609093 ps
CPU time 10.12 seconds
Started Mar 12 01:10:09 PM PDT 24
Finished Mar 12 01:10:19 PM PDT 24
Peak memory 232296 kb
Host smart-f4177687-65b8-49c6-9eeb-2058918d81d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713018937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1713018937
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2078559546
Short name T1034
Test name
Test status
Simulation time 4348819042 ps
CPU time 7.61 seconds
Started Mar 12 03:04:52 PM PDT 24
Finished Mar 12 03:05:00 PM PDT 24
Peak memory 232468 kb
Host smart-05e26974-9512-4e4f-a985-4a3f8a831e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078559546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2078559546
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1241149058
Short name T1482
Test name
Test status
Simulation time 23266839385 ps
CPU time 10.32 seconds
Started Mar 12 03:04:58 PM PDT 24
Finished Mar 12 03:05:10 PM PDT 24
Peak memory 219672 kb
Host smart-ea35b189-91af-40e7-bd03-c05d1292104a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241149058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1241149058
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_intercept.4166666489
Short name T643
Test name
Test status
Simulation time 4280749142 ps
CPU time 12.88 seconds
Started Mar 12 01:10:08 PM PDT 24
Finished Mar 12 01:10:22 PM PDT 24
Peak memory 219104 kb
Host smart-6953fc0f-6cab-4040-9f1d-cc0ad46ffdcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166666489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.4166666489
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2919829542
Short name T681
Test name
Test status
Simulation time 630543576 ps
CPU time 5.35 seconds
Started Mar 12 03:04:52 PM PDT 24
Finished Mar 12 03:04:58 PM PDT 24
Peak memory 236700 kb
Host smart-0978795c-3ccf-4bac-a0f8-831bbe508e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919829542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2919829542
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3081749463
Short name T264
Test name
Test status
Simulation time 1205471594 ps
CPU time 9.91 seconds
Started Mar 12 01:10:07 PM PDT 24
Finished Mar 12 01:10:17 PM PDT 24
Peak memory 238000 kb
Host smart-e90de49d-c5c8-4cc9-ae6f-13ff68d95bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081749463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3081749463
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.948116929
Short name T848
Test name
Test status
Simulation time 16031068 ps
CPU time 0.99 seconds
Started Mar 12 01:10:07 PM PDT 24
Finished Mar 12 01:10:08 PM PDT 24
Peak memory 216344 kb
Host smart-b76cbf4b-b96f-4f6f-95dc-0bc95e2939d0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948116929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.spi_device_mem_parity.948116929
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2819372172
Short name T1419
Test name
Test status
Simulation time 6910856723 ps
CPU time 22.34 seconds
Started Mar 12 03:04:54 PM PDT 24
Finished Mar 12 03:05:17 PM PDT 24
Peak memory 217044 kb
Host smart-0433caf2-1a86-4474-87a9-56d315ca0de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819372172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2819372172
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2908921870
Short name T1049
Test name
Test status
Simulation time 472652360 ps
CPU time 3.74 seconds
Started Mar 12 01:10:07 PM PDT 24
Finished Mar 12 01:10:11 PM PDT 24
Peak memory 224200 kb
Host smart-f213b1d7-86f6-4b59-bc2a-ceb94d091d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908921870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2908921870
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2875212418
Short name T198
Test name
Test status
Simulation time 76037314181 ps
CPU time 28.76 seconds
Started Mar 12 03:04:53 PM PDT 24
Finished Mar 12 03:05:22 PM PDT 24
Peak memory 235848 kb
Host smart-e45367c6-d596-44e0-888e-68e5ce6a833a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875212418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2875212418
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3256961973
Short name T832
Test name
Test status
Simulation time 3935547219 ps
CPU time 17.65 seconds
Started Mar 12 01:10:07 PM PDT 24
Finished Mar 12 01:10:25 PM PDT 24
Peak memory 220340 kb
Host smart-71d94979-2f91-410f-ae16-7a95f5a31670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256961973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3256961973
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.139760073
Short name T1894
Test name
Test status
Simulation time 17313289 ps
CPU time 0.72 seconds
Started Mar 12 01:10:04 PM PDT 24
Finished Mar 12 01:10:05 PM PDT 24
Peak memory 215984 kb
Host smart-feeb9e67-dd77-4ee5-be21-2e8e1a919037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139760073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.139760073
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3099238136
Short name T1402
Test name
Test status
Simulation time 31873079 ps
CPU time 0.76 seconds
Started Mar 12 03:04:43 PM PDT 24
Finished Mar 12 03:04:45 PM PDT 24
Peak memory 215932 kb
Host smart-38511c8e-8065-4c78-abc4-ae866c8b03c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099238136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3099238136
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1581294111
Short name T1360
Test name
Test status
Simulation time 8065209170 ps
CPU time 5.4 seconds
Started Mar 12 01:10:08 PM PDT 24
Finished Mar 12 01:10:14 PM PDT 24
Peak memory 217076 kb
Host smart-24e09f7f-8e63-4a02-b3ac-533635a9b939
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1581294111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1581294111
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.6229412
Short name T1231
Test name
Test status
Simulation time 1946481990 ps
CPU time 6.07 seconds
Started Mar 12 03:04:53 PM PDT 24
Finished Mar 12 03:04:59 PM PDT 24
Peak memory 222380 kb
Host smart-d278ddd7-58dd-4015-96af-2e216d5c0736
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=6229412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direct.6229412
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2134528499
Short name T73
Test name
Test status
Simulation time 381538592 ps
CPU time 0.98 seconds
Started Mar 12 01:10:18 PM PDT 24
Finished Mar 12 01:10:19 PM PDT 24
Peak memory 235196 kb
Host smart-abaeaf7d-3a8c-4b6d-a91e-040e4d9c2bae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134528499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2134528499
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3308315180
Short name T65
Test name
Test status
Simulation time 172768638 ps
CPU time 1.19 seconds
Started Mar 12 03:05:00 PM PDT 24
Finished Mar 12 03:05:01 PM PDT 24
Peak memory 235228 kb
Host smart-b6419e82-a241-44e1-a150-6ed7a1e032a5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308315180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3308315180
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3287692988
Short name T1533
Test name
Test status
Simulation time 39013791234 ps
CPU time 294.52 seconds
Started Mar 12 03:04:59 PM PDT 24
Finished Mar 12 03:09:54 PM PDT 24
Peak memory 306328 kb
Host smart-a1641979-aa2c-4525-869d-d291e71dbdd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287692988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3287692988
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3404721283
Short name T1855
Test name
Test status
Simulation time 61247367744 ps
CPU time 549.5 seconds
Started Mar 12 01:10:22 PM PDT 24
Finished Mar 12 01:19:32 PM PDT 24
Peak memory 281788 kb
Host smart-eea6490e-6183-4e63-b4b0-85fe1fc88185
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404721283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3404721283
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3779730304
Short name T969
Test name
Test status
Simulation time 4024256697 ps
CPU time 31.2 seconds
Started Mar 12 01:10:06 PM PDT 24
Finished Mar 12 01:10:38 PM PDT 24
Peak memory 216176 kb
Host smart-d30f39c4-211d-4dfe-8dde-291bc291756c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779730304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3779730304
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.4264391428
Short name T320
Test name
Test status
Simulation time 32113120040 ps
CPU time 87.36 seconds
Started Mar 12 03:04:53 PM PDT 24
Finished Mar 12 03:06:20 PM PDT 24
Peak memory 216108 kb
Host smart-df9f945d-b6b2-42fd-bf2c-0d481f76bb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264391428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.4264391428
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.152218503
Short name T1167
Test name
Test status
Simulation time 995989204 ps
CPU time 6.25 seconds
Started Mar 12 03:04:44 PM PDT 24
Finished Mar 12 03:04:50 PM PDT 24
Peak memory 216052 kb
Host smart-2be818fe-506d-423c-b1ff-f384e90a2cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152218503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.152218503
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2947021397
Short name T1279
Test name
Test status
Simulation time 4693827126 ps
CPU time 9.04 seconds
Started Mar 12 01:10:08 PM PDT 24
Finished Mar 12 01:10:18 PM PDT 24
Peak memory 216116 kb
Host smart-3c7d2835-1eb3-4e64-a672-03a8167d1921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947021397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2947021397
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1847291503
Short name T760
Test name
Test status
Simulation time 62071526 ps
CPU time 1.62 seconds
Started Mar 12 01:10:07 PM PDT 24
Finished Mar 12 01:10:10 PM PDT 24
Peak memory 216016 kb
Host smart-03323a16-c7af-42b2-8afc-20edd76899f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847291503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1847291503
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.4100820891
Short name T1147
Test name
Test status
Simulation time 597322526 ps
CPU time 2.03 seconds
Started Mar 12 03:04:56 PM PDT 24
Finished Mar 12 03:04:59 PM PDT 24
Peak memory 216376 kb
Host smart-dddcfd2a-5c71-471a-bad4-5fc1b2db7bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100820891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.4100820891
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1140717129
Short name T1824
Test name
Test status
Simulation time 111162606 ps
CPU time 0.93 seconds
Started Mar 12 03:04:51 PM PDT 24
Finished Mar 12 03:04:52 PM PDT 24
Peak memory 205252 kb
Host smart-c008b58f-5c4b-480f-a212-f014d7e5ce37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140717129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1140717129
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2164971336
Short name T602
Test name
Test status
Simulation time 67519885 ps
CPU time 0.87 seconds
Started Mar 12 01:10:07 PM PDT 24
Finished Mar 12 01:10:08 PM PDT 24
Peak memory 205240 kb
Host smart-e3311728-9089-49f1-9b7d-cc214be5d71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164971336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2164971336
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.206204451
Short name T1045
Test name
Test status
Simulation time 15808065273 ps
CPU time 17.25 seconds
Started Mar 12 01:10:08 PM PDT 24
Finished Mar 12 01:10:26 PM PDT 24
Peak memory 219468 kb
Host smart-2fd0c787-7512-4c61-8f4a-5bfa76e94ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206204451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.206204451
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/0.spi_device_upload.2372401652
Short name T1013
Test name
Test status
Simulation time 4994930778 ps
CPU time 13.58 seconds
Started Mar 12 03:04:54 PM PDT 24
Finished Mar 12 03:05:07 PM PDT 24
Peak memory 239732 kb
Host smart-5e5319e7-2378-4048-a229-388647c71b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372401652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2372401652
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.321828823
Short name T1308
Test name
Test status
Simulation time 35310627 ps
CPU time 0.67 seconds
Started Mar 12 01:10:15 PM PDT 24
Finished Mar 12 01:10:16 PM PDT 24
Peak memory 204116 kb
Host smart-d111442f-4d56-419e-a6c7-df7b5aec9e5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321828823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.321828823
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3695650198
Short name T1320
Test name
Test status
Simulation time 33714481 ps
CPU time 0.72 seconds
Started Mar 12 03:05:17 PM PDT 24
Finished Mar 12 03:05:18 PM PDT 24
Peak memory 204244 kb
Host smart-5513a905-e5e8-4b64-8e0c-1cee075e1fba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695650198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
695650198
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1347895569
Short name T228
Test name
Test status
Simulation time 6966927490 ps
CPU time 7.02 seconds
Started Mar 12 03:05:09 PM PDT 24
Finished Mar 12 03:05:17 PM PDT 24
Peak memory 239016 kb
Host smart-bd458f03-e4b8-4e85-ba96-f0cc4dcaeab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347895569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1347895569
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.786358751
Short name T240
Test name
Test status
Simulation time 4617785803 ps
CPU time 4.95 seconds
Started Mar 12 01:10:18 PM PDT 24
Finished Mar 12 01:10:24 PM PDT 24
Peak memory 218444 kb
Host smart-43b951d8-e68b-4e91-8b39-3d32a0f6b5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786358751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.786358751
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1736201025
Short name T1232
Test name
Test status
Simulation time 15988568 ps
CPU time 0.77 seconds
Started Mar 12 01:10:17 PM PDT 24
Finished Mar 12 01:10:18 PM PDT 24
Peak memory 204904 kb
Host smart-7d52af12-c8e4-448c-af9b-d67475fb7458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736201025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1736201025
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.836987594
Short name T1866
Test name
Test status
Simulation time 55729543 ps
CPU time 0.74 seconds
Started Mar 12 03:05:05 PM PDT 24
Finished Mar 12 03:05:07 PM PDT 24
Peak memory 204904 kb
Host smart-23fe716c-9588-41e3-afd9-d28491e4b661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836987594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.836987594
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2966950475
Short name T1560
Test name
Test status
Simulation time 4503775754 ps
CPU time 40.19 seconds
Started Mar 12 03:05:11 PM PDT 24
Finished Mar 12 03:05:53 PM PDT 24
Peak memory 265224 kb
Host smart-8cac0ff8-4518-49cb-8d22-3d90bf13b951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966950475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2966950475
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.81344625
Short name T1738
Test name
Test status
Simulation time 1690435883 ps
CPU time 26.93 seconds
Started Mar 12 01:10:18 PM PDT 24
Finished Mar 12 01:10:46 PM PDT 24
Peak memory 249788 kb
Host smart-fd5a7e57-a856-41d5-ab44-8c68cad93850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81344625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.81344625
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.987186669
Short name T1612
Test name
Test status
Simulation time 130332236222 ps
CPU time 171.27 seconds
Started Mar 12 01:10:21 PM PDT 24
Finished Mar 12 01:13:12 PM PDT 24
Peak memory 261768 kb
Host smart-dcc5bffd-9a6d-42e2-8110-92ed2844b42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987186669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.987186669
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2623975542
Short name T818
Test name
Test status
Simulation time 1601768816 ps
CPU time 19.04 seconds
Started Mar 12 01:10:17 PM PDT 24
Finished Mar 12 01:10:36 PM PDT 24
Peak memory 222112 kb
Host smart-d06127c6-6fe4-4899-af34-5e5df182a7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623975542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2623975542
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.934838193
Short name T656
Test name
Test status
Simulation time 80049813176 ps
CPU time 287.28 seconds
Started Mar 12 03:05:10 PM PDT 24
Finished Mar 12 03:09:58 PM PDT 24
Peak memory 252668 kb
Host smart-e1111566-3a06-4428-ad8b-54749b072228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934838193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
934838193
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.2078277849
Short name T1412
Test name
Test status
Simulation time 9806321982 ps
CPU time 18.27 seconds
Started Mar 12 03:05:07 PM PDT 24
Finished Mar 12 03:05:25 PM PDT 24
Peak memory 248728 kb
Host smart-30837018-019d-4401-ae5d-84f5a6c8c3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078277849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2078277849
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3824533509
Short name T891
Test name
Test status
Simulation time 1190707092 ps
CPU time 17.38 seconds
Started Mar 12 01:10:20 PM PDT 24
Finished Mar 12 01:10:38 PM PDT 24
Peak memory 240436 kb
Host smart-3db0950a-1807-450c-b09d-4077b5f28fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824533509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3824533509
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.433376527
Short name T10
Test name
Test status
Simulation time 1275668720 ps
CPU time 3.78 seconds
Started Mar 12 03:05:11 PM PDT 24
Finished Mar 12 03:05:15 PM PDT 24
Peak memory 217536 kb
Host smart-8f64b7cd-348e-4d65-87cd-8aac8cc3e23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433376527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.433376527
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_intercept.980051064
Short name T880
Test name
Test status
Simulation time 978457291 ps
CPU time 2.92 seconds
Started Mar 12 01:10:16 PM PDT 24
Finished Mar 12 01:10:19 PM PDT 24
Peak memory 224188 kb
Host smart-81d271ba-fe64-4957-a156-f7b8861df4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980051064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.980051064
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.100871268
Short name T660
Test name
Test status
Simulation time 1004546330 ps
CPU time 5.02 seconds
Started Mar 12 03:05:15 PM PDT 24
Finished Mar 12 03:05:22 PM PDT 24
Peak memory 219096 kb
Host smart-78910ad4-d429-475f-84f0-86f76dc9924a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100871268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.100871268
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3583395577
Short name T208
Test name
Test status
Simulation time 420232964 ps
CPU time 5.11 seconds
Started Mar 12 01:10:17 PM PDT 24
Finished Mar 12 01:10:22 PM PDT 24
Peak memory 224148 kb
Host smart-04d8e200-c406-4abe-8458-f2710bdcb51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583395577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3583395577
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.3048659942
Short name T1728
Test name
Test status
Simulation time 98087260 ps
CPU time 1.01 seconds
Started Mar 12 01:10:16 PM PDT 24
Finished Mar 12 01:10:18 PM PDT 24
Peak memory 216368 kb
Host smart-aaa4071c-fa35-4a5b-8568-ce0a23b2ff36
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048659942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.3048659942
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.3525496056
Short name T384
Test name
Test status
Simulation time 24911809 ps
CPU time 1.05 seconds
Started Mar 12 03:05:00 PM PDT 24
Finished Mar 12 03:05:01 PM PDT 24
Peak memory 217576 kb
Host smart-ac2542c8-8008-4785-87ff-9adfecc61aea
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525496056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.3525496056
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.275210168
Short name T1489
Test name
Test status
Simulation time 537949294 ps
CPU time 5.23 seconds
Started Mar 12 01:10:16 PM PDT 24
Finished Mar 12 01:10:22 PM PDT 24
Peak memory 217536 kb
Host smart-1cf9c972-201b-452b-b135-79a83492c4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275210168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.
275210168
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.704968481
Short name T194
Test name
Test status
Simulation time 460793323 ps
CPU time 5.33 seconds
Started Mar 12 03:05:11 PM PDT 24
Finished Mar 12 03:05:18 PM PDT 24
Peak memory 233624 kb
Host smart-5c84eda4-8627-4204-92fe-397ae3910a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704968481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.
704968481
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1209106423
Short name T1055
Test name
Test status
Simulation time 2297141512 ps
CPU time 7.18 seconds
Started Mar 12 03:05:09 PM PDT 24
Finished Mar 12 03:05:17 PM PDT 24
Peak memory 238468 kb
Host smart-37a4201c-c3e6-46ef-8cc0-b4e55ddac345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209106423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1209106423
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.980595405
Short name T690
Test name
Test status
Simulation time 24195267774 ps
CPU time 24.83 seconds
Started Mar 12 01:10:20 PM PDT 24
Finished Mar 12 01:10:46 PM PDT 24
Peak memory 240136 kb
Host smart-8026860d-c524-41d2-a0a1-206a50432dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980595405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.980595405
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.4262319596
Short name T529
Test name
Test status
Simulation time 42217580 ps
CPU time 0.72 seconds
Started Mar 12 01:10:18 PM PDT 24
Finished Mar 12 01:10:20 PM PDT 24
Peak memory 215944 kb
Host smart-7113e634-fa0b-40c9-8f86-b0e983b700be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262319596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.4262319596
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2864990867
Short name T1048
Test name
Test status
Simulation time 1061537938 ps
CPU time 5.7 seconds
Started Mar 12 03:05:12 PM PDT 24
Finished Mar 12 03:05:19 PM PDT 24
Peak memory 221800 kb
Host smart-072be476-db0c-4742-9aab-76c033046393
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2864990867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2864990867
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.408344805
Short name T1694
Test name
Test status
Simulation time 755583172 ps
CPU time 5.05 seconds
Started Mar 12 01:10:16 PM PDT 24
Finished Mar 12 01:10:21 PM PDT 24
Peak memory 218164 kb
Host smart-9d5ba986-fa8c-41c8-a36d-0d0f99c35feb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=408344805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc
t.408344805
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.278844618
Short name T71
Test name
Test status
Simulation time 135930768 ps
CPU time 0.92 seconds
Started Mar 12 01:10:17 PM PDT 24
Finished Mar 12 01:10:18 PM PDT 24
Peak memory 234216 kb
Host smart-9a84e0e7-c9fc-42f9-91e5-cd5fdda571c3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278844618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.278844618
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2156164663
Short name T1000
Test name
Test status
Simulation time 19148287405 ps
CPU time 98.77 seconds
Started Mar 12 01:10:14 PM PDT 24
Finished Mar 12 01:11:54 PM PDT 24
Peak memory 249008 kb
Host smart-cbfed345-df78-4ba5-bb2a-822e4f7b0f5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156164663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2156164663
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2485979439
Short name T321
Test name
Test status
Simulation time 15005855559 ps
CPU time 26.7 seconds
Started Mar 12 03:04:59 PM PDT 24
Finished Mar 12 03:05:27 PM PDT 24
Peak memory 216148 kb
Host smart-7326737d-eef4-49a6-9226-2b23b8606030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485979439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2485979439
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3597534793
Short name T317
Test name
Test status
Simulation time 4405126957 ps
CPU time 24.8 seconds
Started Mar 12 01:10:18 PM PDT 24
Finished Mar 12 01:10:43 PM PDT 24
Peak memory 216028 kb
Host smart-ea2ad46c-42ee-4fc6-adc1-1d3f960c95d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597534793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3597534793
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1612619826
Short name T1818
Test name
Test status
Simulation time 23367826650 ps
CPU time 9.73 seconds
Started Mar 12 03:05:01 PM PDT 24
Finished Mar 12 03:05:11 PM PDT 24
Peak memory 216108 kb
Host smart-bd65f4e4-05e2-4e5d-9671-d5da81b71d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612619826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1612619826
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.77295861
Short name T835
Test name
Test status
Simulation time 1491695755 ps
CPU time 8.14 seconds
Started Mar 12 01:10:18 PM PDT 24
Finished Mar 12 01:10:26 PM PDT 24
Peak memory 216088 kb
Host smart-23723a20-ee17-4125-b900-e1433c32aec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77295861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.77295861
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2518018501
Short name T514
Test name
Test status
Simulation time 380406921 ps
CPU time 1.58 seconds
Started Mar 12 03:05:06 PM PDT 24
Finished Mar 12 03:05:09 PM PDT 24
Peak memory 215928 kb
Host smart-6e325169-3c35-464d-be20-c72cec10f458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518018501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2518018501
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3028192114
Short name T1053
Test name
Test status
Simulation time 195532520 ps
CPU time 2.49 seconds
Started Mar 12 01:10:16 PM PDT 24
Finished Mar 12 01:10:19 PM PDT 24
Peak memory 215984 kb
Host smart-bf501018-6d3b-445e-aa7f-e0a43e256a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028192114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3028192114
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2945564067
Short name T518
Test name
Test status
Simulation time 207389575 ps
CPU time 1.28 seconds
Started Mar 12 03:04:59 PM PDT 24
Finished Mar 12 03:05:01 PM PDT 24
Peak memory 206272 kb
Host smart-0d82d918-3230-4a8b-b2a3-30034afc8420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945564067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2945564067
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.303356855
Short name T1603
Test name
Test status
Simulation time 18306537 ps
CPU time 0.78 seconds
Started Mar 12 01:10:18 PM PDT 24
Finished Mar 12 01:10:20 PM PDT 24
Peak memory 205256 kb
Host smart-dd3085e3-1c40-483d-820e-530423b97680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303356855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.303356855
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1755063416
Short name T764
Test name
Test status
Simulation time 4346272467 ps
CPU time 16.2 seconds
Started Mar 12 03:05:06 PM PDT 24
Finished Mar 12 03:05:23 PM PDT 24
Peak memory 222872 kb
Host smart-16e9b3b7-fec7-4d6d-bac8-02ddc46f7b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755063416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1755063416
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_upload.3550593171
Short name T1768
Test name
Test status
Simulation time 14750372065 ps
CPU time 33.56 seconds
Started Mar 12 01:10:16 PM PDT 24
Finished Mar 12 01:10:50 PM PDT 24
Peak memory 231024 kb
Host smart-399db779-7815-4397-9904-3a9fcac1ffe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550593171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3550593171
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2018700412
Short name T1778
Test name
Test status
Simulation time 20005648 ps
CPU time 0.75 seconds
Started Mar 12 03:06:45 PM PDT 24
Finished Mar 12 03:06:46 PM PDT 24
Peak memory 205120 kb
Host smart-7e1d983a-a9dd-49bc-a936-be0973677fbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018700412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2018700412
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2703018656
Short name T1578
Test name
Test status
Simulation time 27576273 ps
CPU time 0.78 seconds
Started Mar 12 01:11:05 PM PDT 24
Finished Mar 12 01:11:06 PM PDT 24
Peak memory 205160 kb
Host smart-8b661e3c-747d-4d27-9935-d18b9a22bf9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703018656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2703018656
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2341135631
Short name T415
Test name
Test status
Simulation time 280961750 ps
CPU time 2.93 seconds
Started Mar 12 03:06:37 PM PDT 24
Finished Mar 12 03:06:41 PM PDT 24
Peak memory 224156 kb
Host smart-12b5ad64-12cf-42ab-8c51-b36a1f9a12ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341135631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2341135631
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2574329740
Short name T1834
Test name
Test status
Simulation time 279746316 ps
CPU time 3.97 seconds
Started Mar 12 01:11:05 PM PDT 24
Finished Mar 12 01:11:10 PM PDT 24
Peak memory 232796 kb
Host smart-8be3d20b-1e3b-4a43-8ccb-3390799af303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574329740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2574329740
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2736742905
Short name T845
Test name
Test status
Simulation time 92660311 ps
CPU time 0.76 seconds
Started Mar 12 03:06:29 PM PDT 24
Finished Mar 12 03:06:30 PM PDT 24
Peak memory 204896 kb
Host smart-5f9fc8e9-b545-420a-8a4c-2610b80680c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736742905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2736742905
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.798531077
Short name T1002
Test name
Test status
Simulation time 49198183 ps
CPU time 0.74 seconds
Started Mar 12 01:11:04 PM PDT 24
Finished Mar 12 01:11:05 PM PDT 24
Peak memory 205260 kb
Host smart-830592e1-c190-49de-8296-e52924ee1d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798531077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.798531077
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1619334406
Short name T1640
Test name
Test status
Simulation time 46289734119 ps
CPU time 106.52 seconds
Started Mar 12 03:06:38 PM PDT 24
Finished Mar 12 03:08:25 PM PDT 24
Peak memory 236912 kb
Host smart-8a6d0367-6294-466a-ae78-01e7d0e414ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619334406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1619334406
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.3282011001
Short name T1500
Test name
Test status
Simulation time 4152197654 ps
CPU time 21.04 seconds
Started Mar 12 01:11:03 PM PDT 24
Finished Mar 12 01:11:24 PM PDT 24
Peak memory 251892 kb
Host smart-59459e25-0817-47f2-8c68-ab65b140fd52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282011001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3282011001
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2711036312
Short name T343
Test name
Test status
Simulation time 1098229666 ps
CPU time 19.84 seconds
Started Mar 12 01:11:06 PM PDT 24
Finished Mar 12 01:11:26 PM PDT 24
Peak memory 223116 kb
Host smart-07e09087-486d-4426-88ff-9415eb6870d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711036312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2711036312
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.443993475
Short name T1007
Test name
Test status
Simulation time 91750857538 ps
CPU time 328.59 seconds
Started Mar 12 03:06:37 PM PDT 24
Finished Mar 12 03:12:06 PM PDT 24
Peak memory 259480 kb
Host smart-3893440f-34c4-4358-9d5f-f7adf14e4ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443993475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.443993475
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2467546203
Short name T1518
Test name
Test status
Simulation time 20758322850 ps
CPU time 64.3 seconds
Started Mar 12 01:11:04 PM PDT 24
Finished Mar 12 01:12:09 PM PDT 24
Peak memory 248976 kb
Host smart-467ae30d-4a31-4776-ad1c-93d4988f6c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467546203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2467546203
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.727674867
Short name T140
Test name
Test status
Simulation time 14732232290 ps
CPU time 91.58 seconds
Started Mar 12 03:06:37 PM PDT 24
Finished Mar 12 03:08:09 PM PDT 24
Peak memory 248940 kb
Host smart-52c39067-c857-4fda-b730-c181d98d250c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727674867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.727674867
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3942205543
Short name T772
Test name
Test status
Simulation time 2315969090 ps
CPU time 9.39 seconds
Started Mar 12 03:06:37 PM PDT 24
Finished Mar 12 03:06:47 PM PDT 24
Peak memory 240560 kb
Host smart-0f51e3d4-ac4a-480f-a648-7123eb543232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942205543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3942205543
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2879373974
Short name T1910
Test name
Test status
Simulation time 2550009332 ps
CPU time 11.1 seconds
Started Mar 12 01:11:07 PM PDT 24
Finished Mar 12 01:11:18 PM PDT 24
Peak memory 224268 kb
Host smart-2a120b55-2c46-48e6-a619-dbc84ebd9f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879373974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2879373974
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3245843592
Short name T693
Test name
Test status
Simulation time 1380360567 ps
CPU time 6.12 seconds
Started Mar 12 03:06:41 PM PDT 24
Finished Mar 12 03:06:47 PM PDT 24
Peak memory 233408 kb
Host smart-70dac882-d739-48c2-9851-341642fd3463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245843592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3245843592
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1128913599
Short name T1539
Test name
Test status
Simulation time 1137924156 ps
CPU time 4.8 seconds
Started Mar 12 01:11:08 PM PDT 24
Finished Mar 12 01:11:13 PM PDT 24
Peak memory 236404 kb
Host smart-9047d070-5959-4b21-8dce-095563a07577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128913599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1128913599
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3145181148
Short name T851
Test name
Test status
Simulation time 1382096706 ps
CPU time 10.01 seconds
Started Mar 12 03:06:37 PM PDT 24
Finished Mar 12 03:06:48 PM PDT 24
Peak memory 232412 kb
Host smart-9eb35cc5-1ca0-4924-8e58-add5f5c93f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145181148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3145181148
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.2634266854
Short name T1260
Test name
Test status
Simulation time 49140578 ps
CPU time 1.02 seconds
Started Mar 12 03:06:28 PM PDT 24
Finished Mar 12 03:06:30 PM PDT 24
Peak memory 217612 kb
Host smart-2fc6527f-ff2a-445c-b228-bf59dab943c4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634266854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.2634266854
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3695884255
Short name T732
Test name
Test status
Simulation time 30941376 ps
CPU time 1.09 seconds
Started Mar 12 01:11:07 PM PDT 24
Finished Mar 12 01:11:09 PM PDT 24
Peak memory 217512 kb
Host smart-19878a0c-0965-4514-bb14-4e8eb0e3d6ec
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695884255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3695884255
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2585981772
Short name T1527
Test name
Test status
Simulation time 5948405343 ps
CPU time 6.94 seconds
Started Mar 12 01:11:06 PM PDT 24
Finished Mar 12 01:11:13 PM PDT 24
Peak memory 233204 kb
Host smart-74132a4d-f06a-492c-b97a-d38fed4ceda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585981772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2585981772
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3028534415
Short name T1454
Test name
Test status
Simulation time 4249144923 ps
CPU time 8.78 seconds
Started Mar 12 03:06:36 PM PDT 24
Finished Mar 12 03:06:45 PM PDT 24
Peak memory 217496 kb
Host smart-37f0f491-1b32-488a-a766-64efd717638e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028534415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3028534415
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2490621534
Short name T1350
Test name
Test status
Simulation time 228094062 ps
CPU time 4.84 seconds
Started Mar 12 03:06:38 PM PDT 24
Finished Mar 12 03:06:43 PM PDT 24
Peak memory 233140 kb
Host smart-3670c14a-b45c-4d1a-aa49-755d9fabaabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490621534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2490621534
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.507689146
Short name T224
Test name
Test status
Simulation time 16416285381 ps
CPU time 26.01 seconds
Started Mar 12 01:11:06 PM PDT 24
Finished Mar 12 01:11:32 PM PDT 24
Peak memory 227616 kb
Host smart-c613e4dc-b036-4f6d-8527-26c68b268cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507689146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.507689146
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.2611992147
Short name T1446
Test name
Test status
Simulation time 35625430 ps
CPU time 0.73 seconds
Started Mar 12 01:11:04 PM PDT 24
Finished Mar 12 01:11:06 PM PDT 24
Peak memory 215968 kb
Host smart-6562407c-0aac-4454-a78a-e674243bec81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611992147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.2611992147
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.3546498593
Short name T64
Test name
Test status
Simulation time 25943780 ps
CPU time 0.75 seconds
Started Mar 12 03:06:26 PM PDT 24
Finished Mar 12 03:06:28 PM PDT 24
Peak memory 215984 kb
Host smart-22f6c49c-a31b-4027-87a8-f290b0de6e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546498593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.3546498593
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3286370384
Short name T339
Test name
Test status
Simulation time 86068432 ps
CPU time 3.2 seconds
Started Mar 12 03:06:37 PM PDT 24
Finished Mar 12 03:06:40 PM PDT 24
Peak memory 218244 kb
Host smart-9aaa32ef-4591-4371-bdd8-526dc01fb806
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3286370384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3286370384
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3722821650
Short name T945
Test name
Test status
Simulation time 294222220 ps
CPU time 3.58 seconds
Started Mar 12 01:11:06 PM PDT 24
Finished Mar 12 01:11:10 PM PDT 24
Peak memory 222264 kb
Host smart-715d9bb8-668a-481a-b184-e1c9f3a2525c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3722821650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3722821650
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2642311363
Short name T157
Test name
Test status
Simulation time 170666784629 ps
CPU time 141.19 seconds
Started Mar 12 03:06:36 PM PDT 24
Finished Mar 12 03:08:58 PM PDT 24
Peak memory 250016 kb
Host smart-ccfaabbe-f9b0-42b9-8755-399a6854733d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642311363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2642311363
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3670916617
Short name T1502
Test name
Test status
Simulation time 14608139189 ps
CPU time 22.59 seconds
Started Mar 12 01:11:04 PM PDT 24
Finished Mar 12 01:11:27 PM PDT 24
Peak memory 216156 kb
Host smart-7cf07309-b82a-4687-95b4-3aafa9ca139e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670916617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3670916617
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3712474472
Short name T1713
Test name
Test status
Simulation time 9936578172 ps
CPU time 13.39 seconds
Started Mar 12 03:06:36 PM PDT 24
Finished Mar 12 03:06:49 PM PDT 24
Peak memory 216044 kb
Host smart-19b91839-1f09-4a41-8739-fc98e449047d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712474472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3712474472
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2005281558
Short name T342
Test name
Test status
Simulation time 2150633228 ps
CPU time 6.79 seconds
Started Mar 12 03:06:38 PM PDT 24
Finished Mar 12 03:06:45 PM PDT 24
Peak memory 207972 kb
Host smart-eab3800d-76f4-469b-b446-e566e5220f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005281558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2005281558
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2887308470
Short name T1515
Test name
Test status
Simulation time 65488281305 ps
CPU time 30.77 seconds
Started Mar 12 01:11:07 PM PDT 24
Finished Mar 12 01:11:38 PM PDT 24
Peak memory 216100 kb
Host smart-5294e99c-cbd9-4d95-a14a-2af529fb14a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887308470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2887308470
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1336293972
Short name T1318
Test name
Test status
Simulation time 300482384 ps
CPU time 1.25 seconds
Started Mar 12 01:11:05 PM PDT 24
Finished Mar 12 01:11:07 PM PDT 24
Peak memory 207752 kb
Host smart-0c065c9a-fe6d-4382-987b-e409899ab01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336293972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1336293972
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.4016109174
Short name T1070
Test name
Test status
Simulation time 44698347 ps
CPU time 1.04 seconds
Started Mar 12 03:06:38 PM PDT 24
Finished Mar 12 03:06:40 PM PDT 24
Peak memory 206312 kb
Host smart-fac8809c-3a52-416a-ad5a-909feadff509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016109174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.4016109174
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1993820882
Short name T354
Test name
Test status
Simulation time 28733208 ps
CPU time 0.83 seconds
Started Mar 12 03:06:39 PM PDT 24
Finished Mar 12 03:06:39 PM PDT 24
Peak memory 205272 kb
Host smart-4c4a76ea-5f83-4416-a5d6-5323554d4869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993820882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1993820882
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2684362092
Short name T1572
Test name
Test status
Simulation time 407023658 ps
CPU time 0.97 seconds
Started Mar 12 01:11:05 PM PDT 24
Finished Mar 12 01:11:07 PM PDT 24
Peak memory 205728 kb
Host smart-0ff7c411-3ede-4a28-b9d2-bc1e89703ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684362092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2684362092
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2154084885
Short name T1794
Test name
Test status
Simulation time 814999523 ps
CPU time 9.32 seconds
Started Mar 12 01:11:08 PM PDT 24
Finished Mar 12 01:11:18 PM PDT 24
Peak memory 233532 kb
Host smart-66a35d97-b4ca-46fb-84dc-ff8a5a8b8eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154084885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2154084885
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_upload.3917095623
Short name T1382
Test name
Test status
Simulation time 820251952 ps
CPU time 5.52 seconds
Started Mar 12 03:06:37 PM PDT 24
Finished Mar 12 03:06:43 PM PDT 24
Peak memory 224168 kb
Host smart-fce1574a-4dfa-4324-ac22-30b386787b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917095623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3917095623
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1861664534
Short name T475
Test name
Test status
Simulation time 23588726 ps
CPU time 0.71 seconds
Started Mar 12 01:11:12 PM PDT 24
Finished Mar 12 01:11:13 PM PDT 24
Peak memory 204788 kb
Host smart-52dfa80d-e8b9-452f-b233-e2952a3f707e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861664534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1861664534
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2596194551
Short name T408
Test name
Test status
Simulation time 13863023 ps
CPU time 0.72 seconds
Started Mar 12 03:06:47 PM PDT 24
Finished Mar 12 03:06:48 PM PDT 24
Peak memory 204224 kb
Host smart-6cbb7803-9b7f-4e6f-a1f1-19f8201f9590
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596194551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2596194551
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1045938923
Short name T238
Test name
Test status
Simulation time 11403514636 ps
CPU time 5.29 seconds
Started Mar 12 03:06:44 PM PDT 24
Finished Mar 12 03:06:50 PM PDT 24
Peak memory 232796 kb
Host smart-9b0b5ffe-bf69-47c6-a0cd-38645bfcdf84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045938923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1045938923
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.893791444
Short name T594
Test name
Test status
Simulation time 2048579474 ps
CPU time 7.54 seconds
Started Mar 12 01:11:07 PM PDT 24
Finished Mar 12 01:11:15 PM PDT 24
Peak memory 233740 kb
Host smart-3f41172c-33ef-4fcc-91e3-1748fb4761dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893791444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.893791444
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2574392098
Short name T1582
Test name
Test status
Simulation time 60808515 ps
CPU time 0.76 seconds
Started Mar 12 01:11:09 PM PDT 24
Finished Mar 12 01:11:10 PM PDT 24
Peak memory 204852 kb
Host smart-19576106-59f6-4f05-a1e1-1c3bdf1517e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574392098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2574392098
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.4124001873
Short name T725
Test name
Test status
Simulation time 50928746 ps
CPU time 0.77 seconds
Started Mar 12 03:06:47 PM PDT 24
Finished Mar 12 03:06:48 PM PDT 24
Peak memory 206256 kb
Host smart-16fb6946-4149-463f-b428-95bf21c1c580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124001873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.4124001873
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1747261750
Short name T1273
Test name
Test status
Simulation time 18314964109 ps
CPU time 53.87 seconds
Started Mar 12 03:06:47 PM PDT 24
Finished Mar 12 03:07:41 PM PDT 24
Peak memory 240556 kb
Host smart-c5bbb0e6-bea4-464a-9279-5194683f18cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747261750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1747261750
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2753715732
Short name T1470
Test name
Test status
Simulation time 25104776036 ps
CPU time 111.34 seconds
Started Mar 12 01:11:04 PM PDT 24
Finished Mar 12 01:12:56 PM PDT 24
Peak memory 251420 kb
Host smart-ffc73cef-29c5-44dc-b492-dc50425c974c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753715732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2753715732
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3259112927
Short name T1628
Test name
Test status
Simulation time 3691587343 ps
CPU time 61.08 seconds
Started Mar 12 01:11:06 PM PDT 24
Finished Mar 12 01:12:07 PM PDT 24
Peak memory 232636 kb
Host smart-501b78c8-461a-4cc0-9a58-c1d5ef1e9f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259112927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3259112927
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2411430142
Short name T1906
Test name
Test status
Simulation time 49920612890 ps
CPU time 124.61 seconds
Started Mar 12 03:06:46 PM PDT 24
Finished Mar 12 03:08:51 PM PDT 24
Peak memory 272868 kb
Host smart-85c65082-6326-4c5d-96b5-3a54ddad8969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411430142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2411430142
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.268181712
Short name T1931
Test name
Test status
Simulation time 22068906458 ps
CPU time 132.89 seconds
Started Mar 12 01:11:06 PM PDT 24
Finished Mar 12 01:13:19 PM PDT 24
Peak memory 265636 kb
Host smart-c5e2c279-0919-476c-a04c-4b6f7bbe89e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268181712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle
.268181712
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1308579703
Short name T1631
Test name
Test status
Simulation time 2756658064 ps
CPU time 17.33 seconds
Started Mar 12 01:11:22 PM PDT 24
Finished Mar 12 01:11:39 PM PDT 24
Peak memory 238404 kb
Host smart-dab52ee6-4b2e-45e2-b0e4-b8bc7fc9ee6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308579703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1308579703
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.885955283
Short name T1863
Test name
Test status
Simulation time 3307553212 ps
CPU time 12.66 seconds
Started Mar 12 03:06:49 PM PDT 24
Finished Mar 12 03:07:01 PM PDT 24
Peak memory 248620 kb
Host smart-1a26785a-f554-4749-81a5-4e8a25fef9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885955283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.885955283
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.267294619
Short name T761
Test name
Test status
Simulation time 1407031291 ps
CPU time 5.14 seconds
Started Mar 12 01:11:03 PM PDT 24
Finished Mar 12 01:11:08 PM PDT 24
Peak memory 224188 kb
Host smart-cdad414d-38ea-4cb4-97e2-e20632858019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267294619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.267294619
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_intercept.4189545489
Short name T1276
Test name
Test status
Simulation time 286059977 ps
CPU time 2.7 seconds
Started Mar 12 03:06:46 PM PDT 24
Finished Mar 12 03:06:48 PM PDT 24
Peak memory 233176 kb
Host smart-ffde3d75-50b8-44e0-8597-1ec91c3cb43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189545489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.4189545489
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2204568831
Short name T1003
Test name
Test status
Simulation time 36538869778 ps
CPU time 20.49 seconds
Started Mar 12 01:11:12 PM PDT 24
Finished Mar 12 01:11:33 PM PDT 24
Peak memory 224200 kb
Host smart-40ea9785-8e63-4129-80f1-fb07bb13589f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204568831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2204568831
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3197198527
Short name T1860
Test name
Test status
Simulation time 172298454 ps
CPU time 3.14 seconds
Started Mar 12 03:06:51 PM PDT 24
Finished Mar 12 03:06:54 PM PDT 24
Peak memory 234300 kb
Host smart-81105af6-2d19-4057-b0db-384c1072497f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197198527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3197198527
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.2176067530
Short name T463
Test name
Test status
Simulation time 31666217 ps
CPU time 1.03 seconds
Started Mar 12 01:11:04 PM PDT 24
Finished Mar 12 01:11:05 PM PDT 24
Peak memory 216352 kb
Host smart-205939cd-a2aa-45bf-a0fd-f69beab1829a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176067530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.2176067530
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.851473497
Short name T1464
Test name
Test status
Simulation time 30556657 ps
CPU time 0.96 seconds
Started Mar 12 03:06:46 PM PDT 24
Finished Mar 12 03:06:47 PM PDT 24
Peak memory 216136 kb
Host smart-08a250fa-967f-48a2-896e-6b40eacf974a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851473497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.spi_device_mem_parity.851473497
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1236973660
Short name T256
Test name
Test status
Simulation time 11543399061 ps
CPU time 31.49 seconds
Started Mar 12 03:06:51 PM PDT 24
Finished Mar 12 03:07:23 PM PDT 24
Peak memory 235320 kb
Host smart-a5c89043-4a3b-4d9f-a98d-d865cb3f8ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236973660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1236973660
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.832227321
Short name T1791
Test name
Test status
Simulation time 4020197392 ps
CPU time 11.38 seconds
Started Mar 12 01:11:05 PM PDT 24
Finished Mar 12 01:11:16 PM PDT 24
Peak memory 233328 kb
Host smart-7fbdcae2-cd3d-43d3-882b-b8cb86ade25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832227321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.832227321
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1197876459
Short name T1090
Test name
Test status
Simulation time 4649068383 ps
CPU time 18.16 seconds
Started Mar 12 01:11:03 PM PDT 24
Finished Mar 12 01:11:22 PM PDT 24
Peak memory 217356 kb
Host smart-f99bf2d0-d3ce-4774-bf82-33669d43ff03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197876459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1197876459
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.376673573
Short name T781
Test name
Test status
Simulation time 1310955816 ps
CPU time 5.62 seconds
Started Mar 12 03:06:47 PM PDT 24
Finished Mar 12 03:06:52 PM PDT 24
Peak memory 216620 kb
Host smart-44077332-21e8-4203-9544-dec5576f287b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376673573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.376673573
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.1096593560
Short name T631
Test name
Test status
Simulation time 15431902 ps
CPU time 0.76 seconds
Started Mar 12 01:11:19 PM PDT 24
Finished Mar 12 01:11:20 PM PDT 24
Peak memory 215416 kb
Host smart-250c69bb-d666-4159-8eab-82b6b19f4667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096593560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.1096593560
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.3096871480
Short name T537
Test name
Test status
Simulation time 17360404 ps
CPU time 0.76 seconds
Started Mar 12 03:06:46 PM PDT 24
Finished Mar 12 03:06:47 PM PDT 24
Peak memory 215928 kb
Host smart-085d063c-1d4a-4f68-a290-4fddf98e5ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096871480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.3096871480
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.588548078
Short name T361
Test name
Test status
Simulation time 81782861 ps
CPU time 3.65 seconds
Started Mar 12 03:06:46 PM PDT 24
Finished Mar 12 03:06:50 PM PDT 24
Peak memory 222516 kb
Host smart-417a9671-16e7-440c-a90a-9bf4df9e79b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=588548078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.588548078
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.688905106
Short name T1541
Test name
Test status
Simulation time 1363101625 ps
CPU time 6.73 seconds
Started Mar 12 01:11:12 PM PDT 24
Finished Mar 12 01:11:19 PM PDT 24
Peak memory 222332 kb
Host smart-905068ca-cdce-4947-87d9-5da09e558f83
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=688905106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.688905106
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2932522866
Short name T158
Test name
Test status
Simulation time 191643052102 ps
CPU time 90.95 seconds
Started Mar 12 01:11:19 PM PDT 24
Finished Mar 12 01:12:50 PM PDT 24
Peak memory 251384 kb
Host smart-865eaca9-280c-4391-bd0d-a679a976e2f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932522866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2932522866
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.3797467193
Short name T847
Test name
Test status
Simulation time 30314509171 ps
CPU time 138.33 seconds
Started Mar 12 03:06:45 PM PDT 24
Finished Mar 12 03:09:04 PM PDT 24
Peak memory 256916 kb
Host smart-82635f9b-3330-4539-baee-86d624569b2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797467193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.3797467193
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.292759418
Short name T1429
Test name
Test status
Simulation time 9220205145 ps
CPU time 50.88 seconds
Started Mar 12 01:11:06 PM PDT 24
Finished Mar 12 01:11:57 PM PDT 24
Peak memory 216076 kb
Host smart-80c3638e-77fa-4366-9221-1acc89ca130b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292759418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.292759418
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1886756245
Short name T1813
Test name
Test status
Simulation time 20776177311 ps
CPU time 18.93 seconds
Started Mar 12 03:06:46 PM PDT 24
Finished Mar 12 03:07:06 PM PDT 24
Peak memory 216108 kb
Host smart-fd80c675-dcff-4679-95ee-7afa43e2a4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886756245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1886756245
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2833098855
Short name T825
Test name
Test status
Simulation time 5450918712 ps
CPU time 9.03 seconds
Started Mar 12 01:11:04 PM PDT 24
Finished Mar 12 01:11:13 PM PDT 24
Peak memory 215984 kb
Host smart-c926f935-0013-4e5a-9e68-dd641c2be8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833098855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2833098855
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3969528996
Short name T644
Test name
Test status
Simulation time 440132416 ps
CPU time 1.74 seconds
Started Mar 12 01:11:04 PM PDT 24
Finished Mar 12 01:11:06 PM PDT 24
Peak memory 216076 kb
Host smart-6e1fc98b-3e7a-4e9c-ad35-df74bd9bcfd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969528996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3969528996
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.790147140
Short name T1731
Test name
Test status
Simulation time 461584203 ps
CPU time 3.69 seconds
Started Mar 12 03:06:45 PM PDT 24
Finished Mar 12 03:06:49 PM PDT 24
Peak memory 217464 kb
Host smart-605d3c3f-d805-468d-ab1b-4e2494dbb671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790147140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.790147140
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.507914955
Short name T395
Test name
Test status
Simulation time 22917064 ps
CPU time 0.76 seconds
Started Mar 12 03:06:47 PM PDT 24
Finished Mar 12 03:06:48 PM PDT 24
Peak memory 205232 kb
Host smart-93675be6-17e0-4def-9fd8-da630ff2f031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507914955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.507914955
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.517218324
Short name T994
Test name
Test status
Simulation time 63420205 ps
CPU time 0.85 seconds
Started Mar 12 01:11:22 PM PDT 24
Finished Mar 12 01:11:23 PM PDT 24
Peak memory 206220 kb
Host smart-b6f1486e-24fb-4698-b535-d8ddcceb5ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517218324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.517218324
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1173889573
Short name T1089
Test name
Test status
Simulation time 36071702672 ps
CPU time 50.98 seconds
Started Mar 12 01:11:04 PM PDT 24
Finished Mar 12 01:11:55 PM PDT 24
Peak memory 234408 kb
Host smart-ea2c3e84-8efd-4103-ae22-b0fb79881744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173889573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1173889573
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_upload.187420643
Short name T1497
Test name
Test status
Simulation time 13875650283 ps
CPU time 24.58 seconds
Started Mar 12 03:06:45 PM PDT 24
Finished Mar 12 03:07:10 PM PDT 24
Peak memory 240528 kb
Host smart-1f3f85d0-9af4-4c58-a632-483f30615493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187420643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.187420643
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1181617656
Short name T986
Test name
Test status
Simulation time 29965224 ps
CPU time 0.73 seconds
Started Mar 12 03:07:01 PM PDT 24
Finished Mar 12 03:07:02 PM PDT 24
Peak memory 204812 kb
Host smart-dc5f29bc-6039-4061-a3ae-3dd4458bb900
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181617656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1181617656
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1940661771
Short name T941
Test name
Test status
Simulation time 14058938 ps
CPU time 0.68 seconds
Started Mar 12 01:11:08 PM PDT 24
Finished Mar 12 01:11:09 PM PDT 24
Peak memory 204808 kb
Host smart-2dc2151e-e9fb-43e6-988c-b8b995275733
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940661771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1940661771
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2753599780
Short name T1462
Test name
Test status
Simulation time 302708679 ps
CPU time 4.05 seconds
Started Mar 12 03:06:57 PM PDT 24
Finished Mar 12 03:07:02 PM PDT 24
Peak memory 233316 kb
Host smart-eacc8826-6698-4859-9600-65cf1cb72430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753599780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2753599780
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.412956377
Short name T1346
Test name
Test status
Simulation time 1505110100 ps
CPU time 6.3 seconds
Started Mar 12 01:11:19 PM PDT 24
Finished Mar 12 01:11:25 PM PDT 24
Peak memory 237416 kb
Host smart-c3727763-0181-4ffb-afa3-08c5a83f61a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412956377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.412956377
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1895615902
Short name T1310
Test name
Test status
Simulation time 71383699 ps
CPU time 0.75 seconds
Started Mar 12 01:11:07 PM PDT 24
Finished Mar 12 01:11:08 PM PDT 24
Peak memory 205260 kb
Host smart-de75bca3-8b51-4854-802b-de01c912cad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895615902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1895615902
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3439179069
Short name T719
Test name
Test status
Simulation time 15054367 ps
CPU time 0.74 seconds
Started Mar 12 03:06:47 PM PDT 24
Finished Mar 12 03:06:48 PM PDT 24
Peak memory 206264 kb
Host smart-806778cf-f344-4f61-8a8a-bb7956468f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439179069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3439179069
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.184544368
Short name T1683
Test name
Test status
Simulation time 687346191 ps
CPU time 8.67 seconds
Started Mar 12 01:11:19 PM PDT 24
Finished Mar 12 01:11:27 PM PDT 24
Peak memory 228320 kb
Host smart-c96981cd-e2a1-462a-b3af-062c9e19ccf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184544368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.184544368
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3916207341
Short name T1901
Test name
Test status
Simulation time 4227560955 ps
CPU time 38.06 seconds
Started Mar 12 03:06:56 PM PDT 24
Finished Mar 12 03:07:34 PM PDT 24
Peak memory 234612 kb
Host smart-b07c0b6e-47f1-40ec-9280-ad98dcc31854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916207341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3916207341
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.202620198
Short name T205
Test name
Test status
Simulation time 63621761221 ps
CPU time 95.25 seconds
Started Mar 12 03:07:02 PM PDT 24
Finished Mar 12 03:08:37 PM PDT 24
Peak memory 266972 kb
Host smart-093a23ab-1f78-4f36-afc1-70e0bea38ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202620198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.202620198
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3642485812
Short name T277
Test name
Test status
Simulation time 79265458722 ps
CPU time 267.01 seconds
Started Mar 12 01:11:16 PM PDT 24
Finished Mar 12 01:15:43 PM PDT 24
Peak memory 254648 kb
Host smart-cfbbdcdd-e3aa-4fa8-a90e-792343d4069f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642485812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3642485812
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1641595666
Short name T167
Test name
Test status
Simulation time 129903306445 ps
CPU time 104.68 seconds
Started Mar 12 01:11:15 PM PDT 24
Finished Mar 12 01:13:00 PM PDT 24
Peak memory 260564 kb
Host smart-ace9c056-ed05-44ac-a138-f11c1ae651c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641595666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1641595666
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3824054912
Short name T728
Test name
Test status
Simulation time 13937118411 ps
CPU time 59.46 seconds
Started Mar 12 03:06:56 PM PDT 24
Finished Mar 12 03:07:56 PM PDT 24
Peak memory 249024 kb
Host smart-3c905bbb-db19-4e4c-9e75-6c9b6f8a9726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824054912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.3824054912
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3099199197
Short name T446
Test name
Test status
Simulation time 12634584756 ps
CPU time 24.26 seconds
Started Mar 12 01:11:12 PM PDT 24
Finished Mar 12 01:11:36 PM PDT 24
Peak memory 244608 kb
Host smart-062dbf2e-01b8-4601-8c66-b411b8522dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099199197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3099199197
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.584321656
Short name T454
Test name
Test status
Simulation time 611794557 ps
CPU time 11.63 seconds
Started Mar 12 03:06:57 PM PDT 24
Finished Mar 12 03:07:08 PM PDT 24
Peak memory 240588 kb
Host smart-d3ea2a37-7cd4-4962-981e-28e8d5ec63b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584321656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.584321656
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3319727386
Short name T963
Test name
Test status
Simulation time 38201580148 ps
CPU time 9.09 seconds
Started Mar 12 03:06:57 PM PDT 24
Finished Mar 12 03:07:06 PM PDT 24
Peak memory 220184 kb
Host smart-747ee10e-c0d9-4a04-b89f-3dc4d88c912e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319727386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3319727386
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_intercept.662159827
Short name T633
Test name
Test status
Simulation time 777805059 ps
CPU time 5.17 seconds
Started Mar 12 01:11:08 PM PDT 24
Finished Mar 12 01:11:13 PM PDT 24
Peak memory 233380 kb
Host smart-17b2a98e-6594-456b-8f04-1edb4163cf1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662159827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.662159827
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2723089443
Short name T659
Test name
Test status
Simulation time 2011390736 ps
CPU time 5.32 seconds
Started Mar 12 01:11:05 PM PDT 24
Finished Mar 12 01:11:10 PM PDT 24
Peak memory 233484 kb
Host smart-e2577fd0-dd73-4587-8c85-1d1c1cdfcf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723089443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2723089443
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3782591850
Short name T1891
Test name
Test status
Simulation time 340324603 ps
CPU time 5.42 seconds
Started Mar 12 03:06:55 PM PDT 24
Finished Mar 12 03:07:01 PM PDT 24
Peak memory 232384 kb
Host smart-04487e35-bd23-427d-9059-e3efdeef65cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782591850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3782591850
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.3364838286
Short name T1372
Test name
Test status
Simulation time 28091510 ps
CPU time 1.04 seconds
Started Mar 12 01:11:06 PM PDT 24
Finished Mar 12 01:11:08 PM PDT 24
Peak memory 217540 kb
Host smart-ab16e26d-d2ec-425d-aae2-152e076d92df
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364838286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.3364838286
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.375777565
Short name T1452
Test name
Test status
Simulation time 17533161 ps
CPU time 1.02 seconds
Started Mar 12 03:06:45 PM PDT 24
Finished Mar 12 03:06:46 PM PDT 24
Peak memory 217576 kb
Host smart-f57551b4-810c-4ffe-b581-095818462513
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375777565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.spi_device_mem_parity.375777565
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.4175234451
Short name T1393
Test name
Test status
Simulation time 676124052 ps
CPU time 7.05 seconds
Started Mar 12 03:06:56 PM PDT 24
Finished Mar 12 03:07:04 PM PDT 24
Peak memory 233228 kb
Host smart-4111ad41-4cf7-4634-a42c-cdb7a52b3872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175234451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.4175234451
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.909026694
Short name T285
Test name
Test status
Simulation time 401754867 ps
CPU time 4.64 seconds
Started Mar 12 01:11:14 PM PDT 24
Finished Mar 12 01:11:19 PM PDT 24
Peak memory 240468 kb
Host smart-e452542f-dd1d-4fb2-b153-c3e94189cddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909026694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.909026694
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1957611927
Short name T33
Test name
Test status
Simulation time 5269732910 ps
CPU time 7.93 seconds
Started Mar 12 03:06:56 PM PDT 24
Finished Mar 12 03:07:04 PM PDT 24
Peak memory 221592 kb
Host smart-620c14de-3573-43bd-88ab-c354db0d9bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957611927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1957611927
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2718473680
Short name T1435
Test name
Test status
Simulation time 390110194 ps
CPU time 3.69 seconds
Started Mar 12 01:11:05 PM PDT 24
Finished Mar 12 01:11:09 PM PDT 24
Peak memory 233080 kb
Host smart-963e2836-509a-440a-9302-bfcf4fda12fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718473680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2718473680
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_ram_cfg.2722016046
Short name T1848
Test name
Test status
Simulation time 29820951 ps
CPU time 0.71 seconds
Started Mar 12 01:11:08 PM PDT 24
Finished Mar 12 01:11:09 PM PDT 24
Peak memory 215964 kb
Host smart-394e6205-938e-4b8f-a745-f497fe04caa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722016046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.2722016046
Directory /workspace/12.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/12.spi_device_ram_cfg.2882805306
Short name T486
Test name
Test status
Simulation time 28076631 ps
CPU time 0.72 seconds
Started Mar 12 03:06:56 PM PDT 24
Finished Mar 12 03:06:56 PM PDT 24
Peak memory 215936 kb
Host smart-b43820c7-77f5-4fdb-bff6-62276879ef93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882805306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.2882805306
Directory /workspace/12.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3522755654
Short name T1184
Test name
Test status
Simulation time 225557577 ps
CPU time 3.51 seconds
Started Mar 12 01:11:05 PM PDT 24
Finished Mar 12 01:11:09 PM PDT 24
Peak memory 222008 kb
Host smart-c985d8a7-1fe7-4711-ab14-6ebba81fe435
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3522755654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3522755654
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3588771511
Short name T340
Test name
Test status
Simulation time 389728007 ps
CPU time 3.49 seconds
Started Mar 12 03:06:56 PM PDT 24
Finished Mar 12 03:06:59 PM PDT 24
Peak memory 216336 kb
Host smart-3f24349d-d57d-4731-bd7e-09a9796a9a8e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3588771511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3588771511
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3407902663
Short name T1508
Test name
Test status
Simulation time 77215808 ps
CPU time 0.92 seconds
Started Mar 12 01:11:07 PM PDT 24
Finished Mar 12 01:11:08 PM PDT 24
Peak memory 206540 kb
Host smart-978c0616-782a-43ee-9b16-6ff2a34bac12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407902663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3407902663
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3684986757
Short name T1280
Test name
Test status
Simulation time 303470592219 ps
CPU time 480.87 seconds
Started Mar 12 03:06:55 PM PDT 24
Finished Mar 12 03:14:56 PM PDT 24
Peak memory 265364 kb
Host smart-f1b6285d-8bf8-4b1e-9d28-66004beee426
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684986757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3684986757
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2266563117
Short name T583
Test name
Test status
Simulation time 36995378588 ps
CPU time 53.97 seconds
Started Mar 12 01:11:05 PM PDT 24
Finished Mar 12 01:12:00 PM PDT 24
Peak memory 216156 kb
Host smart-0b82c37d-a3bf-4303-9deb-fa96af6da092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266563117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2266563117
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3228718616
Short name T1540
Test name
Test status
Simulation time 17738440060 ps
CPU time 44.89 seconds
Started Mar 12 03:06:55 PM PDT 24
Finished Mar 12 03:07:40 PM PDT 24
Peak memory 219776 kb
Host smart-17156e2e-5f54-4eb6-a67f-75d3ec020431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228718616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3228718616
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3513176287
Short name T452
Test name
Test status
Simulation time 1291246029 ps
CPU time 7.39 seconds
Started Mar 12 03:06:56 PM PDT 24
Finished Mar 12 03:07:04 PM PDT 24
Peak memory 216060 kb
Host smart-f7605442-5b57-4ec1-a16d-3a96cb7d4c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513176287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3513176287
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.661247500
Short name T1830
Test name
Test status
Simulation time 2707940626 ps
CPU time 7.14 seconds
Started Mar 12 01:11:19 PM PDT 24
Finished Mar 12 01:11:26 PM PDT 24
Peak memory 215380 kb
Host smart-e622f9c2-a3d2-40ff-8572-9215956e17a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661247500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.661247500
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1891481921
Short name T1321
Test name
Test status
Simulation time 123951748 ps
CPU time 1.36 seconds
Started Mar 12 01:11:08 PM PDT 24
Finished Mar 12 01:11:10 PM PDT 24
Peak memory 216028 kb
Host smart-28359089-e6d2-4ade-8f74-5e2eda4f568c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891481921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1891481921
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.4035540532
Short name T1249
Test name
Test status
Simulation time 28236928 ps
CPU time 0.98 seconds
Started Mar 12 03:06:55 PM PDT 24
Finished Mar 12 03:06:56 PM PDT 24
Peak memory 206296 kb
Host smart-68c98b79-d9dd-49cc-b784-6017cd2acc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035540532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.4035540532
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.494835376
Short name T464
Test name
Test status
Simulation time 63294314 ps
CPU time 0.74 seconds
Started Mar 12 01:11:19 PM PDT 24
Finished Mar 12 01:11:20 PM PDT 24
Peak memory 205228 kb
Host smart-c231f610-724a-4ea7-b7b5-805a40d67c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494835376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.494835376
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.786242801
Short name T42
Test name
Test status
Simulation time 81194021 ps
CPU time 0.84 seconds
Started Mar 12 03:06:55 PM PDT 24
Finished Mar 12 03:06:56 PM PDT 24
Peak memory 205228 kb
Host smart-44d2d718-e0e1-4f74-8c4e-1a5d08dbc374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786242801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.786242801
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2634874941
Short name T1110
Test name
Test status
Simulation time 14763078570 ps
CPU time 27 seconds
Started Mar 12 01:11:11 PM PDT 24
Finished Mar 12 01:11:38 PM PDT 24
Peak memory 234952 kb
Host smart-176fd048-7a98-48c5-a0d7-e6f9dce4b9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634874941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2634874941
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_upload.441986108
Short name T482
Test name
Test status
Simulation time 760037766 ps
CPU time 6.94 seconds
Started Mar 12 03:06:55 PM PDT 24
Finished Mar 12 03:07:02 PM PDT 24
Peak memory 224128 kb
Host smart-e3032210-2585-4004-b753-81345e5398b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441986108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.441986108
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3819315051
Short name T1268
Test name
Test status
Simulation time 16121038 ps
CPU time 0.75 seconds
Started Mar 12 01:11:29 PM PDT 24
Finished Mar 12 01:11:31 PM PDT 24
Peak memory 204820 kb
Host smart-4c8cfd3a-9651-433a-a565-c81b0bd39302
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819315051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3819315051
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.4070979130
Short name T1358
Test name
Test status
Simulation time 29849577 ps
CPU time 0.71 seconds
Started Mar 12 03:07:10 PM PDT 24
Finished Mar 12 03:07:11 PM PDT 24
Peak memory 204804 kb
Host smart-a614ffa9-8d04-4fa0-8e1b-63628fcec014
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070979130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
4070979130
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2249999273
Short name T1219
Test name
Test status
Simulation time 84843938 ps
CPU time 2.74 seconds
Started Mar 12 01:11:08 PM PDT 24
Finished Mar 12 01:11:11 PM PDT 24
Peak memory 233500 kb
Host smart-4271553d-3b00-492d-a378-cfd64f6c3b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249999273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2249999273
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3251798644
Short name T844
Test name
Test status
Simulation time 1118566112 ps
CPU time 4.31 seconds
Started Mar 12 03:07:07 PM PDT 24
Finished Mar 12 03:07:12 PM PDT 24
Peak memory 234396 kb
Host smart-084cc56b-9f60-4594-8732-11e3507f7719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251798644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3251798644
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3534962913
Short name T1902
Test name
Test status
Simulation time 26441017 ps
CPU time 0.81 seconds
Started Mar 12 03:06:55 PM PDT 24
Finished Mar 12 03:06:56 PM PDT 24
Peak memory 205956 kb
Host smart-f42872bd-80fd-48b6-8e95-49e994bf1f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534962913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3534962913
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.875237295
Short name T421
Test name
Test status
Simulation time 46170150 ps
CPU time 0.78 seconds
Started Mar 12 01:11:07 PM PDT 24
Finished Mar 12 01:11:08 PM PDT 24
Peak memory 205944 kb
Host smart-3dedcf60-8e46-4eac-92b7-ee2e47f22a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875237295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.875237295
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.3920656869
Short name T733
Test name
Test status
Simulation time 90140639655 ps
CPU time 47.16 seconds
Started Mar 12 01:11:16 PM PDT 24
Finished Mar 12 01:12:03 PM PDT 24
Peak memory 232428 kb
Host smart-d6e9b43e-3efc-46f5-9c45-510f065f765c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920656869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3920656869
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.656677416
Short name T271
Test name
Test status
Simulation time 13719918242 ps
CPU time 21.34 seconds
Started Mar 12 03:07:07 PM PDT 24
Finished Mar 12 03:07:29 PM PDT 24
Peak memory 232420 kb
Host smart-e4fc371e-bf64-4f82-ab11-a5c5affbb851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656677416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.656677416
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3578833026
Short name T1319
Test name
Test status
Simulation time 9761703310 ps
CPU time 69.16 seconds
Started Mar 12 03:07:13 PM PDT 24
Finished Mar 12 03:08:23 PM PDT 24
Peak memory 248992 kb
Host smart-19938c99-97a6-42a6-9483-db934faf1caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578833026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3578833026
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.863177284
Short name T273
Test name
Test status
Simulation time 93071664423 ps
CPU time 711.68 seconds
Started Mar 12 01:11:17 PM PDT 24
Finished Mar 12 01:23:09 PM PDT 24
Peak memory 268624 kb
Host smart-2ece4a3c-7caa-4706-905c-867acafde2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863177284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.863177284
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1288227183
Short name T281
Test name
Test status
Simulation time 56502796824 ps
CPU time 423.47 seconds
Started Mar 12 03:07:05 PM PDT 24
Finished Mar 12 03:14:09 PM PDT 24
Peak memory 265060 kb
Host smart-0648117a-9a7c-4079-855d-149e3be47139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288227183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1288227183
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1999440068
Short name T1234
Test name
Test status
Simulation time 382765267468 ps
CPU time 256.83 seconds
Started Mar 12 01:11:19 PM PDT 24
Finished Mar 12 01:15:36 PM PDT 24
Peak memory 260820 kb
Host smart-5244acef-a9d2-4f80-bf1a-0a882591f290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999440068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1999440068
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1455048385
Short name T1243
Test name
Test status
Simulation time 26688272308 ps
CPU time 33.56 seconds
Started Mar 12 01:11:12 PM PDT 24
Finished Mar 12 01:11:46 PM PDT 24
Peak memory 244400 kb
Host smart-81792335-341f-4321-b2d6-bc8f648ae0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455048385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1455048385
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.4125381511
Short name T449
Test name
Test status
Simulation time 4880244809 ps
CPU time 35.43 seconds
Started Mar 12 03:07:03 PM PDT 24
Finished Mar 12 03:07:40 PM PDT 24
Peak memory 231228 kb
Host smart-ee27d88e-0e9d-49fc-9c4f-6dd569cdd542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125381511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.4125381511
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1217722785
Short name T1229
Test name
Test status
Simulation time 72878606390 ps
CPU time 12.6 seconds
Started Mar 12 01:11:07 PM PDT 24
Finished Mar 12 01:11:20 PM PDT 24
Peak memory 234868 kb
Host smart-e1254bb5-10d6-42da-9296-e6bb053aeada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217722785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1217722785
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1517183425
Short name T1588
Test name
Test status
Simulation time 545442871 ps
CPU time 3.71 seconds
Started Mar 12 03:07:12 PM PDT 24
Finished Mar 12 03:07:18 PM PDT 24
Peak memory 224200 kb
Host smart-17f7033c-ed16-4e1c-a72e-38afed0bb008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517183425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1517183425
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.388225334
Short name T1494
Test name
Test status
Simulation time 833452960 ps
CPU time 6.02 seconds
Started Mar 12 03:07:12 PM PDT 24
Finished Mar 12 03:07:20 PM PDT 24
Peak memory 238260 kb
Host smart-1fac6543-626f-4ca5-a93f-5f2c99b307ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388225334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.388225334
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.685298631
Short name T1802
Test name
Test status
Simulation time 1755661879 ps
CPU time 10.64 seconds
Started Mar 12 01:11:07 PM PDT 24
Finished Mar 12 01:11:18 PM PDT 24
Peak memory 240488 kb
Host smart-c0625dd6-bdbf-4431-a7e6-abc5988bea00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685298631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.685298631
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.1297179483
Short name T429
Test name
Test status
Simulation time 16762946 ps
CPU time 1 seconds
Started Mar 12 01:11:09 PM PDT 24
Finished Mar 12 01:11:10 PM PDT 24
Peak memory 216316 kb
Host smart-be869ade-6d75-4e87-823b-186a5cdaee1b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297179483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.1297179483
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.2736825595
Short name T595
Test name
Test status
Simulation time 57321037 ps
CPU time 0.99 seconds
Started Mar 12 03:07:13 PM PDT 24
Finished Mar 12 03:07:15 PM PDT 24
Peak memory 217596 kb
Host smart-395c9955-d43f-45ee-95a6-86df79d13cbb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736825595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.2736825595
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.193517863
Short name T653
Test name
Test status
Simulation time 34182143413 ps
CPU time 29.16 seconds
Started Mar 12 01:11:15 PM PDT 24
Finished Mar 12 01:11:45 PM PDT 24
Peak memory 236648 kb
Host smart-e1d8d9c1-8e92-4f8e-9eca-c9f6295f8f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193517863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.193517863
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2348122660
Short name T618
Test name
Test status
Simulation time 2888227488 ps
CPU time 11.16 seconds
Started Mar 12 03:07:04 PM PDT 24
Finished Mar 12 03:07:15 PM PDT 24
Peak memory 233368 kb
Host smart-65bc27b6-4001-4b74-91fd-ea3411c674cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348122660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2348122660
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.129544832
Short name T1033
Test name
Test status
Simulation time 47515570096 ps
CPU time 30.99 seconds
Started Mar 12 01:11:07 PM PDT 24
Finished Mar 12 01:11:38 PM PDT 24
Peak memory 234024 kb
Host smart-aca84ef4-4408-456c-a89d-29bc75a5409f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129544832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.129544832
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.4063255564
Short name T211
Test name
Test status
Simulation time 1581875549 ps
CPU time 5.46 seconds
Started Mar 12 03:07:04 PM PDT 24
Finished Mar 12 03:07:10 PM PDT 24
Peak memory 217308 kb
Host smart-1e091cd3-1f0e-4e63-bf67-308c4ecf5253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063255564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.4063255564
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.2493616018
Short name T1023
Test name
Test status
Simulation time 37150109 ps
CPU time 0.7 seconds
Started Mar 12 01:11:08 PM PDT 24
Finished Mar 12 01:11:09 PM PDT 24
Peak memory 215976 kb
Host smart-542c8f79-3646-452d-a21d-cdd9100f3867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493616018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.2493616018
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.2517630346
Short name T1314
Test name
Test status
Simulation time 33936700 ps
CPU time 0.8 seconds
Started Mar 12 03:07:06 PM PDT 24
Finished Mar 12 03:07:07 PM PDT 24
Peak memory 215948 kb
Host smart-132a7686-9f9c-4563-bf06-9fecbdc1894c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517630346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.2517630346
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2985908802
Short name T553
Test name
Test status
Simulation time 769213749 ps
CPU time 5.12 seconds
Started Mar 12 01:11:11 PM PDT 24
Finished Mar 12 01:11:16 PM PDT 24
Peak memory 222408 kb
Host smart-3953d2c6-6e64-4d31-971c-5bd3b8268a35
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2985908802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2985908802
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3156552797
Short name T1355
Test name
Test status
Simulation time 296155280 ps
CPU time 3.53 seconds
Started Mar 12 03:07:07 PM PDT 24
Finished Mar 12 03:07:11 PM PDT 24
Peak memory 218304 kb
Host smart-ce0c617c-f672-4526-9a56-793ec2767379
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3156552797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3156552797
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.691924821
Short name T622
Test name
Test status
Simulation time 8354535176 ps
CPU time 78.01 seconds
Started Mar 12 03:07:04 PM PDT 24
Finished Mar 12 03:08:22 PM PDT 24
Peak memory 252064 kb
Host smart-5dc5feff-ab24-49fe-bdc2-9358e5f92abf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691924821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.691924821
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1446135223
Short name T1837
Test name
Test status
Simulation time 4844132644 ps
CPU time 17.48 seconds
Started Mar 12 01:11:07 PM PDT 24
Finished Mar 12 01:11:25 PM PDT 24
Peak memory 216168 kb
Host smart-2f39e9bf-d437-459e-8cf2-9d4fca3db4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446135223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1446135223
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.4173328016
Short name T736
Test name
Test status
Simulation time 541412329 ps
CPU time 9.92 seconds
Started Mar 12 03:07:05 PM PDT 24
Finished Mar 12 03:07:16 PM PDT 24
Peak memory 216008 kb
Host smart-2e9b239a-394f-435e-b6c8-0788f9029e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173328016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.4173328016
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.508105202
Short name T1646
Test name
Test status
Simulation time 6556654779 ps
CPU time 9.52 seconds
Started Mar 12 03:07:04 PM PDT 24
Finished Mar 12 03:07:14 PM PDT 24
Peak memory 216148 kb
Host smart-4b84d267-1367-43b6-95a4-f99bcda0405f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508105202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.508105202
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.558908619
Short name T627
Test name
Test status
Simulation time 2580846855 ps
CPU time 4.41 seconds
Started Mar 12 01:11:08 PM PDT 24
Finished Mar 12 01:11:13 PM PDT 24
Peak memory 216096 kb
Host smart-44dd1d43-b3ed-460e-bd9b-86436025ced2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558908619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.558908619
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3642403994
Short name T911
Test name
Test status
Simulation time 336668543 ps
CPU time 4.04 seconds
Started Mar 12 03:07:06 PM PDT 24
Finished Mar 12 03:07:10 PM PDT 24
Peak memory 216140 kb
Host smart-89e77693-142e-408c-b4d9-f7b620a3ae91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642403994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3642403994
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.909196247
Short name T1359
Test name
Test status
Simulation time 93361020 ps
CPU time 1.43 seconds
Started Mar 12 01:11:14 PM PDT 24
Finished Mar 12 01:11:16 PM PDT 24
Peak memory 216052 kb
Host smart-7e6f2313-c2e6-46e9-8ba4-f93985bfd43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909196247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.909196247
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.343161025
Short name T352
Test name
Test status
Simulation time 53408687 ps
CPU time 0.96 seconds
Started Mar 12 03:07:06 PM PDT 24
Finished Mar 12 03:07:07 PM PDT 24
Peak memory 205724 kb
Host smart-2d5cdf77-2029-449b-9e50-f3ab94f9016d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343161025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.343161025
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3468959639
Short name T1893
Test name
Test status
Simulation time 425205006 ps
CPU time 0.86 seconds
Started Mar 12 01:11:12 PM PDT 24
Finished Mar 12 01:11:13 PM PDT 24
Peak memory 205228 kb
Host smart-dba267df-7225-4a31-adfa-51016b4526a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468959639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3468959639
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3008610365
Short name T1781
Test name
Test status
Simulation time 13686242594 ps
CPU time 26.78 seconds
Started Mar 12 01:11:11 PM PDT 24
Finished Mar 12 01:11:38 PM PDT 24
Peak memory 230912 kb
Host smart-34b30269-da37-4cf1-a353-c1645b5cdc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008610365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3008610365
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.319251616
Short name T1657
Test name
Test status
Simulation time 24279648 ps
CPU time 0.74 seconds
Started Mar 12 01:11:17 PM PDT 24
Finished Mar 12 01:11:18 PM PDT 24
Peak memory 204788 kb
Host smart-3f084e06-ea7a-4c38-9367-06a52271f430
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319251616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.319251616
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.874854101
Short name T371
Test name
Test status
Simulation time 45836203 ps
CPU time 0.74 seconds
Started Mar 12 03:07:13 PM PDT 24
Finished Mar 12 03:07:15 PM PDT 24
Peak memory 205016 kb
Host smart-6e521851-2d53-49f1-8180-76ae19d115d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874854101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.874854101
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1194285566
Short name T227
Test name
Test status
Simulation time 4611164864 ps
CPU time 9.55 seconds
Started Mar 12 01:11:16 PM PDT 24
Finished Mar 12 01:11:26 PM PDT 24
Peak memory 233448 kb
Host smart-dd17a074-6327-438e-85be-30a0894dd1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194285566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1194285566
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3255004512
Short name T1087
Test name
Test status
Simulation time 7372638919 ps
CPU time 8.1 seconds
Started Mar 12 03:07:13 PM PDT 24
Finished Mar 12 03:07:23 PM PDT 24
Peak memory 233220 kb
Host smart-2d317136-0714-4d45-bcb2-0f175484cf85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255004512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3255004512
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1862666007
Short name T497
Test name
Test status
Simulation time 18992825 ps
CPU time 0.79 seconds
Started Mar 12 03:07:06 PM PDT 24
Finished Mar 12 03:07:07 PM PDT 24
Peak memory 204892 kb
Host smart-0c3b606b-4d5a-4bc4-9b01-dccba4ef5478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862666007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1862666007
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3714456513
Short name T1823
Test name
Test status
Simulation time 104303094 ps
CPU time 0.79 seconds
Started Mar 12 01:11:19 PM PDT 24
Finished Mar 12 01:11:20 PM PDT 24
Peak memory 205772 kb
Host smart-ba6b15cc-93df-4fb2-94ea-f334f493d22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714456513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3714456513
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1746120100
Short name T1874
Test name
Test status
Simulation time 68814182299 ps
CPU time 136.17 seconds
Started Mar 12 01:11:16 PM PDT 24
Finished Mar 12 01:13:32 PM PDT 24
Peak memory 264400 kb
Host smart-12d849f7-1edc-471d-8efc-e4620a8bf590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746120100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1746120100
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2068130802
Short name T1930
Test name
Test status
Simulation time 91117852074 ps
CPU time 703.8 seconds
Started Mar 12 01:11:14 PM PDT 24
Finished Mar 12 01:22:58 PM PDT 24
Peak memory 272788 kb
Host smart-70572b0d-416e-4e7c-bbff-bd067442bbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068130802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2068130802
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.4145759903
Short name T784
Test name
Test status
Simulation time 12909580555 ps
CPU time 85.2 seconds
Started Mar 12 03:07:13 PM PDT 24
Finished Mar 12 03:08:39 PM PDT 24
Peak memory 223972 kb
Host smart-61947afd-28e3-435e-b00c-82a87bf42beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145759903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.4145759903
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2358058035
Short name T776
Test name
Test status
Simulation time 42931526910 ps
CPU time 281.47 seconds
Started Mar 12 01:11:16 PM PDT 24
Finished Mar 12 01:15:57 PM PDT 24
Peak memory 251552 kb
Host smart-d16f63c7-9a26-457e-aee2-80b5388606ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358058035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2358058035
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.454038686
Short name T1376
Test name
Test status
Simulation time 58970700387 ps
CPU time 441.92 seconds
Started Mar 12 03:07:16 PM PDT 24
Finished Mar 12 03:14:39 PM PDT 24
Peak memory 272788 kb
Host smart-bd0060ca-a2da-48c0-ba42-6c828163a462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454038686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle
.454038686
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1362073048
Short name T900
Test name
Test status
Simulation time 5641835761 ps
CPU time 31.26 seconds
Started Mar 12 01:11:17 PM PDT 24
Finished Mar 12 01:11:49 PM PDT 24
Peak memory 240624 kb
Host smart-b1dd1aaf-0ef6-45b4-b13d-d9904104b0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362073048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1362073048
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.4025307546
Short name T402
Test name
Test status
Simulation time 393955593 ps
CPU time 9.89 seconds
Started Mar 12 03:07:15 PM PDT 24
Finished Mar 12 03:07:26 PM PDT 24
Peak memory 248632 kb
Host smart-0b0468ee-7e24-4d07-be0d-33cd4ba84afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025307546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.4025307546
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3323862111
Short name T90
Test name
Test status
Simulation time 460419911 ps
CPU time 3.63 seconds
Started Mar 12 03:07:05 PM PDT 24
Finished Mar 12 03:07:08 PM PDT 24
Peak memory 235376 kb
Host smart-c45b3493-0811-4976-9392-c4fda92e6d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323862111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3323862111
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3369334000
Short name T1925
Test name
Test status
Simulation time 2314330235 ps
CPU time 8.29 seconds
Started Mar 12 01:11:14 PM PDT 24
Finished Mar 12 01:11:23 PM PDT 24
Peak memory 217608 kb
Host smart-2f2789de-af99-4564-862c-21cf279f3023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369334000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3369334000
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3366176824
Short name T1396
Test name
Test status
Simulation time 13577269806 ps
CPU time 12.16 seconds
Started Mar 12 03:07:12 PM PDT 24
Finished Mar 12 03:07:26 PM PDT 24
Peak memory 234960 kb
Host smart-f83c0da3-93b6-4cea-a4e6-d114ca1ec77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366176824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3366176824
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3964175686
Short name T1701
Test name
Test status
Simulation time 4482114889 ps
CPU time 19.26 seconds
Started Mar 12 01:11:17 PM PDT 24
Finished Mar 12 01:11:36 PM PDT 24
Peak memory 244600 kb
Host smart-9dbfda84-18d5-409b-b5b2-310b06899bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964175686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3964175686
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.3745105811
Short name T758
Test name
Test status
Simulation time 53263519 ps
CPU time 1.12 seconds
Started Mar 12 03:07:07 PM PDT 24
Finished Mar 12 03:07:09 PM PDT 24
Peak memory 216376 kb
Host smart-45142f85-e1e8-47b6-bc49-85958ad4c8b2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745105811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.3745105811
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.658825178
Short name T1505
Test name
Test status
Simulation time 99649965 ps
CPU time 1.06 seconds
Started Mar 12 01:11:18 PM PDT 24
Finished Mar 12 01:11:19 PM PDT 24
Peak memory 217568 kb
Host smart-01fb7f4a-fd32-49e4-86c3-56339dc7431b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658825178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.spi_device_mem_parity.658825178
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1994580151
Short name T713
Test name
Test status
Simulation time 1529115048 ps
CPU time 3.8 seconds
Started Mar 12 03:07:04 PM PDT 24
Finished Mar 12 03:07:08 PM PDT 24
Peak memory 224196 kb
Host smart-74ab6fbe-e5be-4a62-a7da-53fafe87e453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994580151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1994580151
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.548073055
Short name T1530
Test name
Test status
Simulation time 632434376 ps
CPU time 4.47 seconds
Started Mar 12 01:11:17 PM PDT 24
Finished Mar 12 01:11:21 PM PDT 24
Peak memory 225320 kb
Host smart-7bd722c7-79a3-4e30-b1dd-17c4b9c29933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548073055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.548073055
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.210070490
Short name T1046
Test name
Test status
Simulation time 3790748709 ps
CPU time 7.6 seconds
Started Mar 12 03:07:05 PM PDT 24
Finished Mar 12 03:07:13 PM PDT 24
Peak memory 219520 kb
Host smart-cd4213f8-7731-4b6e-a1d7-50206fcfa0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210070490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.210070490
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.718466798
Short name T1535
Test name
Test status
Simulation time 17474570386 ps
CPU time 12.71 seconds
Started Mar 12 01:11:28 PM PDT 24
Finished Mar 12 01:11:41 PM PDT 24
Peak memory 217256 kb
Host smart-594f61ff-e0a7-44ee-8cd4-9a009a6c2778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718466798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.718466798
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.2293291768
Short name T1381
Test name
Test status
Simulation time 18590064 ps
CPU time 0.77 seconds
Started Mar 12 03:07:07 PM PDT 24
Finished Mar 12 03:07:08 PM PDT 24
Peak memory 215948 kb
Host smart-00fbe783-c983-4dd5-98df-66147a9ad24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293291768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.2293291768
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.3527200327
Short name T422
Test name
Test status
Simulation time 30475110 ps
CPU time 0.76 seconds
Started Mar 12 01:11:16 PM PDT 24
Finished Mar 12 01:11:17 PM PDT 24
Peak memory 215844 kb
Host smart-e26ede05-e2e1-46ee-b97f-8fb9f7905864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527200327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.3527200327
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1535141632
Short name T1150
Test name
Test status
Simulation time 1700458243 ps
CPU time 5.69 seconds
Started Mar 12 01:11:18 PM PDT 24
Finished Mar 12 01:11:24 PM PDT 24
Peak memory 218184 kb
Host smart-9fd49f07-e20f-4869-8cce-bca857a1b1b0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1535141632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1535141632
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.4252987524
Short name T1035
Test name
Test status
Simulation time 913657969 ps
CPU time 4.04 seconds
Started Mar 12 03:07:12 PM PDT 24
Finished Mar 12 03:07:18 PM PDT 24
Peak memory 218264 kb
Host smart-b62f7346-86df-4129-8012-5766f0872bcd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4252987524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.4252987524
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2449675682
Short name T778
Test name
Test status
Simulation time 85577309803 ps
CPU time 516.95 seconds
Started Mar 12 01:11:14 PM PDT 24
Finished Mar 12 01:19:51 PM PDT 24
Peak memory 265384 kb
Host smart-d4728f89-a3ad-4361-a9d3-8a9d1dc2115b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449675682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2449675682
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.60288425
Short name T1797
Test name
Test status
Simulation time 739242085 ps
CPU time 0.96 seconds
Started Mar 12 03:07:13 PM PDT 24
Finished Mar 12 03:07:15 PM PDT 24
Peak memory 206264 kb
Host smart-5d6afeb6-04d7-41cf-8d9e-d8ae1b4bae13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60288425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stress
_all.60288425
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1583177380
Short name T1589
Test name
Test status
Simulation time 2995615841 ps
CPU time 22.33 seconds
Started Mar 12 01:11:16 PM PDT 24
Finished Mar 12 01:11:39 PM PDT 24
Peak memory 216136 kb
Host smart-719fa3d4-57ba-4651-8b33-6c92f2f3a0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583177380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1583177380
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.821074870
Short name T1132
Test name
Test status
Simulation time 11738329665 ps
CPU time 26.01 seconds
Started Mar 12 03:07:06 PM PDT 24
Finished Mar 12 03:07:32 PM PDT 24
Peak memory 216148 kb
Host smart-cf0273ef-ab0b-4f27-ac1d-8892417c107f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821074870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.821074870
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1684150614
Short name T1086
Test name
Test status
Simulation time 4894359001 ps
CPU time 14.96 seconds
Started Mar 12 01:11:17 PM PDT 24
Finished Mar 12 01:11:32 PM PDT 24
Peak memory 216448 kb
Host smart-e7c78613-de24-46a8-b3be-8066a6c9a5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684150614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1684150614
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3590196104
Short name T423
Test name
Test status
Simulation time 650395066 ps
CPU time 1.97 seconds
Started Mar 12 03:07:07 PM PDT 24
Finished Mar 12 03:07:10 PM PDT 24
Peak memory 207696 kb
Host smart-ff5ee20d-dc53-4f37-89dd-e3b27fa29dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590196104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3590196104
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2121791496
Short name T1608
Test name
Test status
Simulation time 101714517 ps
CPU time 1.26 seconds
Started Mar 12 01:11:15 PM PDT 24
Finished Mar 12 01:11:17 PM PDT 24
Peak memory 206632 kb
Host smart-8479a43e-fd2f-47f8-b001-b645a51e9b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121791496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2121791496
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3023192100
Short name T1711
Test name
Test status
Simulation time 145006428 ps
CPU time 6.19 seconds
Started Mar 12 03:07:01 PM PDT 24
Finished Mar 12 03:07:08 PM PDT 24
Peak memory 216112 kb
Host smart-a244638f-427b-411f-af94-d5024f2c1c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023192100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3023192100
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.4168619911
Short name T1675
Test name
Test status
Simulation time 364728930 ps
CPU time 1.08 seconds
Started Mar 12 01:11:14 PM PDT 24
Finished Mar 12 01:11:15 PM PDT 24
Peak memory 206240 kb
Host smart-7ab7adc4-3101-4df0-ab93-f4f86218f995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168619911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.4168619911
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.760402715
Short name T1240
Test name
Test status
Simulation time 427736515 ps
CPU time 0.99 seconds
Started Mar 12 03:07:06 PM PDT 24
Finished Mar 12 03:07:07 PM PDT 24
Peak memory 206252 kb
Host smart-bb21002d-b659-47d8-991c-1532493d7c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760402715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.760402715
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2575718414
Short name T1832
Test name
Test status
Simulation time 607290159 ps
CPU time 3.31 seconds
Started Mar 12 01:11:16 PM PDT 24
Finished Mar 12 01:11:19 PM PDT 24
Peak memory 232240 kb
Host smart-cd2ab27c-397a-4973-8f95-c0b9390b1e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575718414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2575718414
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_upload.917718852
Short name T800
Test name
Test status
Simulation time 1747715726 ps
CPU time 19.13 seconds
Started Mar 12 03:07:13 PM PDT 24
Finished Mar 12 03:07:34 PM PDT 24
Peak memory 232664 kb
Host smart-f5c7021c-f0d2-47ff-894f-e37537223f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917718852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.917718852
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3823089581
Short name T1137
Test name
Test status
Simulation time 13636973 ps
CPU time 0.73 seconds
Started Mar 12 01:11:29 PM PDT 24
Finished Mar 12 01:11:31 PM PDT 24
Peak memory 204716 kb
Host smart-561529b2-11b3-486b-a1c4-fed82be47bac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823089581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3823089581
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.4029188214
Short name T1684
Test name
Test status
Simulation time 14500897 ps
CPU time 0.69 seconds
Started Mar 12 03:07:18 PM PDT 24
Finished Mar 12 03:07:19 PM PDT 24
Peak memory 204784 kb
Host smart-23b7d365-9876-4d19-a253-3c0a1f5f2e46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029188214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
4029188214
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.2192167121
Short name T500
Test name
Test status
Simulation time 7950489116 ps
CPU time 6.87 seconds
Started Mar 12 03:07:13 PM PDT 24
Finished Mar 12 03:07:21 PM PDT 24
Peak memory 218832 kb
Host smart-8a4929d8-eba3-4f9b-bfb9-dc7a9bf1ea4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192167121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2192167121
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.50129309
Short name T424
Test name
Test status
Simulation time 4320502182 ps
CPU time 7.85 seconds
Started Mar 12 01:11:17 PM PDT 24
Finished Mar 12 01:11:25 PM PDT 24
Peak memory 234612 kb
Host smart-44e9151d-58dd-4627-abec-2122448e6145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50129309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.50129309
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.235705836
Short name T1438
Test name
Test status
Simulation time 19439576 ps
CPU time 0.78 seconds
Started Mar 12 03:07:13 PM PDT 24
Finished Mar 12 03:07:15 PM PDT 24
Peak memory 204880 kb
Host smart-db10a0d5-3973-4563-9deb-c17fe794fa94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235705836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.235705836
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3874323849
Short name T450
Test name
Test status
Simulation time 55900483 ps
CPU time 0.75 seconds
Started Mar 12 01:11:15 PM PDT 24
Finished Mar 12 01:11:16 PM PDT 24
Peak memory 206276 kb
Host smart-db552395-9257-4943-ac98-e75c3dcccb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874323849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3874323849
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.1903154576
Short name T298
Test name
Test status
Simulation time 543759199076 ps
CPU time 473 seconds
Started Mar 12 01:11:22 PM PDT 24
Finished Mar 12 01:19:15 PM PDT 24
Peak memory 264948 kb
Host smart-9f2861d2-5144-4429-88e7-f5e1322949b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903154576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1903154576
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3433160566
Short name T286
Test name
Test status
Simulation time 1429507611355 ps
CPU time 361.49 seconds
Started Mar 12 03:07:14 PM PDT 24
Finished Mar 12 03:13:16 PM PDT 24
Peak memory 265748 kb
Host smart-19154e89-9673-4a72-97f1-0c081d70f7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433160566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3433160566
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.1276074498
Short name T1284
Test name
Test status
Simulation time 20609976594 ps
CPU time 76.39 seconds
Started Mar 12 03:07:17 PM PDT 24
Finished Mar 12 03:08:34 PM PDT 24
Peak memory 254508 kb
Host smart-bc66b586-919c-4655-a2e9-2c239c5a97bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276074498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1276074498
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1546564224
Short name T1401
Test name
Test status
Simulation time 10240306378 ps
CPU time 62.97 seconds
Started Mar 12 03:07:14 PM PDT 24
Finished Mar 12 03:08:18 PM PDT 24
Peak memory 248932 kb
Host smart-d67e8a51-e84e-44ae-a7e2-053e1ca00b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546564224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1546564224
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.126425426
Short name T777
Test name
Test status
Simulation time 752145990 ps
CPU time 12.13 seconds
Started Mar 12 01:11:17 PM PDT 24
Finished Mar 12 01:11:30 PM PDT 24
Peak memory 253660 kb
Host smart-a00d4194-5285-411a-8856-1d62b16c4a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126425426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.126425426
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1772809899
Short name T854
Test name
Test status
Simulation time 1903187679 ps
CPU time 11.97 seconds
Started Mar 12 03:07:14 PM PDT 24
Finished Mar 12 03:07:26 PM PDT 24
Peak memory 232400 kb
Host smart-45c6c8d5-02e2-448b-8ade-8e70bd75a3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772809899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1772809899
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1013578205
Short name T1747
Test name
Test status
Simulation time 141354274 ps
CPU time 3.8 seconds
Started Mar 12 01:11:18 PM PDT 24
Finished Mar 12 01:11:22 PM PDT 24
Peak memory 224144 kb
Host smart-90c26066-9be8-4be9-a638-c1571255380d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013578205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1013578205
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1805466365
Short name T712
Test name
Test status
Simulation time 3802332181 ps
CPU time 12.52 seconds
Started Mar 12 03:07:12 PM PDT 24
Finished Mar 12 03:07:27 PM PDT 24
Peak memory 220372 kb
Host smart-95390cf0-cb03-4f6a-af73-a6fd6abdb577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805466365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1805466365
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1155303783
Short name T1298
Test name
Test status
Simulation time 2613445513 ps
CPU time 16.68 seconds
Started Mar 12 01:11:15 PM PDT 24
Finished Mar 12 01:11:32 PM PDT 24
Peak memory 224232 kb
Host smart-58de8d80-da9e-4f37-83c2-70902ebe4714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155303783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1155303783
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3766887934
Short name T263
Test name
Test status
Simulation time 25280014439 ps
CPU time 13.31 seconds
Started Mar 12 03:07:13 PM PDT 24
Finished Mar 12 03:07:28 PM PDT 24
Peak memory 235520 kb
Host smart-de779f40-b60e-4365-9939-704c0b2d8834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766887934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3766887934
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.735017438
Short name T28
Test name
Test status
Simulation time 96383352 ps
CPU time 1.1 seconds
Started Mar 12 03:07:16 PM PDT 24
Finished Mar 12 03:07:18 PM PDT 24
Peak memory 216300 kb
Host smart-a0c04027-b1fd-4f82-8e19-0f9808e8e31b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735017438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.spi_device_mem_parity.735017438
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.991319482
Short name T1609
Test name
Test status
Simulation time 115437448 ps
CPU time 1.12 seconds
Started Mar 12 01:11:15 PM PDT 24
Finished Mar 12 01:11:16 PM PDT 24
Peak memory 216336 kb
Host smart-c954b798-a5c5-4fcf-893e-aa690b7cee24
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991319482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.spi_device_mem_parity.991319482
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1343844173
Short name T1340
Test name
Test status
Simulation time 16921138654 ps
CPU time 10.58 seconds
Started Mar 12 03:07:14 PM PDT 24
Finished Mar 12 03:07:26 PM PDT 24
Peak memory 216428 kb
Host smart-f5162e1c-1d82-4151-beec-91f4c51e051b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343844173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1343844173
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1546510250
Short name T1071
Test name
Test status
Simulation time 1415898811 ps
CPU time 9.34 seconds
Started Mar 12 01:11:17 PM PDT 24
Finished Mar 12 01:11:27 PM PDT 24
Peak memory 232448 kb
Host smart-aa56f498-fc72-41e6-a3dc-ce1e681ef630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546510250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1546510250
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1598093182
Short name T855
Test name
Test status
Simulation time 1239068234 ps
CPU time 4.94 seconds
Started Mar 12 01:11:17 PM PDT 24
Finished Mar 12 01:11:22 PM PDT 24
Peak memory 234324 kb
Host smart-2a30a816-9a96-4b0f-ac2d-b1a3a2db3e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598093182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1598093182
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.826713046
Short name T31
Test name
Test status
Simulation time 8932936766 ps
CPU time 9.12 seconds
Started Mar 12 03:07:13 PM PDT 24
Finished Mar 12 03:07:24 PM PDT 24
Peak memory 224244 kb
Host smart-c60c7d83-ec7a-4699-9ad4-2ed0742ad280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826713046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.826713046
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.2686903488
Short name T1561
Test name
Test status
Simulation time 26356363 ps
CPU time 0.76 seconds
Started Mar 12 03:07:13 PM PDT 24
Finished Mar 12 03:07:15 PM PDT 24
Peak memory 215924 kb
Host smart-20d07deb-4d2d-4da3-8269-05c51a79bf31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686903488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.2686903488
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.3008158311
Short name T1428
Test name
Test status
Simulation time 109085268 ps
CPU time 0.74 seconds
Started Mar 12 01:11:21 PM PDT 24
Finished Mar 12 01:11:22 PM PDT 24
Peak memory 215896 kb
Host smart-a51da998-1a75-4152-ad34-c3e5089fe660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008158311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.3008158311
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1979725853
Short name T1291
Test name
Test status
Simulation time 1943337605 ps
CPU time 5.73 seconds
Started Mar 12 03:07:16 PM PDT 24
Finished Mar 12 03:07:23 PM PDT 24
Peak memory 221808 kb
Host smart-d786fe0f-e199-4b10-bf7d-78e6e00fa977
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1979725853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1979725853
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3265300502
Short name T717
Test name
Test status
Simulation time 2845290373 ps
CPU time 5.93 seconds
Started Mar 12 01:11:17 PM PDT 24
Finished Mar 12 01:11:23 PM PDT 24
Peak memory 218408 kb
Host smart-5a4d55ed-8022-482c-9cd8-e446fcda57e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3265300502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3265300502
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.4064025824
Short name T1938
Test name
Test status
Simulation time 278321587418 ps
CPU time 272.31 seconds
Started Mar 12 01:11:19 PM PDT 24
Finished Mar 12 01:15:51 PM PDT 24
Peak memory 261464 kb
Host smart-937227f3-9167-4635-8ae7-0da22333e724
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064025824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.4064025824
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.185646774
Short name T1581
Test name
Test status
Simulation time 18019081272 ps
CPU time 43.92 seconds
Started Mar 12 03:07:17 PM PDT 24
Finished Mar 12 03:08:02 PM PDT 24
Peak memory 215904 kb
Host smart-0a441e93-3f18-4e2a-9afa-ed55801059b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185646774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.185646774
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3568095591
Short name T1274
Test name
Test status
Simulation time 46539241386 ps
CPU time 22.32 seconds
Started Mar 12 01:11:17 PM PDT 24
Finished Mar 12 01:11:39 PM PDT 24
Peak memory 216128 kb
Host smart-8e60bd7e-9f64-4a7c-82a5-e34b0fac40d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568095591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3568095591
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2563133980
Short name T815
Test name
Test status
Simulation time 941157732 ps
CPU time 3.46 seconds
Started Mar 12 01:11:19 PM PDT 24
Finished Mar 12 01:11:22 PM PDT 24
Peak memory 215800 kb
Host smart-709b4be7-ab6b-436f-befb-d51329358eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563133980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2563133980
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3011994957
Short name T1656
Test name
Test status
Simulation time 3751090443 ps
CPU time 10.63 seconds
Started Mar 12 03:07:14 PM PDT 24
Finished Mar 12 03:07:25 PM PDT 24
Peak memory 216176 kb
Host smart-7d56f769-3ff8-4851-a267-bb095ad89c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011994957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3011994957
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3371403672
Short name T1356
Test name
Test status
Simulation time 116776338 ps
CPU time 3.03 seconds
Started Mar 12 03:07:14 PM PDT 24
Finished Mar 12 03:07:18 PM PDT 24
Peak memory 216148 kb
Host smart-f307d58e-5e76-43e3-bb14-aaa4b9c07e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371403672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3371403672
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3922386613
Short name T1936
Test name
Test status
Simulation time 123907918 ps
CPU time 2.22 seconds
Started Mar 12 01:11:17 PM PDT 24
Finished Mar 12 01:11:20 PM PDT 24
Peak memory 216068 kb
Host smart-d05b1a93-1671-4351-b0bb-d945dd45ea14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922386613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3922386613
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1338713886
Short name T1740
Test name
Test status
Simulation time 320894986 ps
CPU time 0.94 seconds
Started Mar 12 03:07:14 PM PDT 24
Finished Mar 12 03:07:16 PM PDT 24
Peak memory 206292 kb
Host smart-23d32ed3-14f5-48ff-885f-081eb0f0e4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338713886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1338713886
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1806663981
Short name T1557
Test name
Test status
Simulation time 136333018 ps
CPU time 1.32 seconds
Started Mar 12 01:11:19 PM PDT 24
Finished Mar 12 01:11:20 PM PDT 24
Peak memory 206272 kb
Host smart-59eb6f7d-1474-423d-b020-56f99ee3663e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806663981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1806663981
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1854125665
Short name T1887
Test name
Test status
Simulation time 6188235972 ps
CPU time 5.29 seconds
Started Mar 12 03:07:14 PM PDT 24
Finished Mar 12 03:07:20 PM PDT 24
Peak memory 234140 kb
Host smart-e21ef932-dcdb-4da7-8726-4c532973605b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854125665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1854125665
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2896180766
Short name T574
Test name
Test status
Simulation time 13247152 ps
CPU time 0.72 seconds
Started Mar 12 03:07:30 PM PDT 24
Finished Mar 12 03:07:31 PM PDT 24
Peak memory 204764 kb
Host smart-7016f6a0-1242-447a-b1db-931fdee3ceb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896180766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2896180766
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.4212075103
Short name T1019
Test name
Test status
Simulation time 51414556 ps
CPU time 0.69 seconds
Started Mar 12 01:11:28 PM PDT 24
Finished Mar 12 01:11:29 PM PDT 24
Peak memory 205120 kb
Host smart-f628e7df-5b47-46b0-a7ac-96860a8f52d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212075103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
4212075103
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3768062873
Short name T1546
Test name
Test status
Simulation time 816459422 ps
CPU time 5.16 seconds
Started Mar 12 03:07:24 PM PDT 24
Finished Mar 12 03:07:30 PM PDT 24
Peak memory 224148 kb
Host smart-bba99922-8407-4197-96bf-3b237f5db53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768062873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3768062873
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.479506072
Short name T563
Test name
Test status
Simulation time 66195755 ps
CPU time 2.18 seconds
Started Mar 12 01:11:17 PM PDT 24
Finished Mar 12 01:11:19 PM PDT 24
Peak memory 233020 kb
Host smart-00c63328-0e67-4fc2-974f-34a75c9073c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479506072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.479506072
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1244917552
Short name T1199
Test name
Test status
Simulation time 69910488 ps
CPU time 0.83 seconds
Started Mar 12 01:11:29 PM PDT 24
Finished Mar 12 01:11:30 PM PDT 24
Peak memory 205932 kb
Host smart-7f9db41d-5696-4956-a7a3-9de95909a16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244917552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1244917552
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2056062594
Short name T1611
Test name
Test status
Simulation time 37902465 ps
CPU time 0.77 seconds
Started Mar 12 03:07:20 PM PDT 24
Finished Mar 12 03:07:22 PM PDT 24
Peak memory 205912 kb
Host smart-d8724e69-213c-4d32-8e23-ec45917119ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056062594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2056062594
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1277063765
Short name T1767
Test name
Test status
Simulation time 1116322786974 ps
CPU time 314.99 seconds
Started Mar 12 03:07:30 PM PDT 24
Finished Mar 12 03:12:45 PM PDT 24
Peak memory 248836 kb
Host smart-f64adb0d-bf8b-4f11-ab7b-415e8bf3d5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277063765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1277063765
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.108389769
Short name T699
Test name
Test status
Simulation time 79902227651 ps
CPU time 337.93 seconds
Started Mar 12 03:07:29 PM PDT 24
Finished Mar 12 03:13:07 PM PDT 24
Peak memory 272880 kb
Host smart-8f468599-8c2f-4733-855d-3b9654f7edbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108389769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.108389769
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3921385340
Short name T1047
Test name
Test status
Simulation time 107249931589 ps
CPU time 340.03 seconds
Started Mar 12 01:11:30 PM PDT 24
Finished Mar 12 01:17:11 PM PDT 24
Peak memory 252256 kb
Host smart-6a278efa-e1b9-4dab-9714-71b25eb6b929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921385340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3921385340
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.1915116322
Short name T982
Test name
Test status
Simulation time 92493585627 ps
CPU time 150.75 seconds
Started Mar 12 01:11:32 PM PDT 24
Finished Mar 12 01:14:04 PM PDT 24
Peak memory 265348 kb
Host smart-08f192af-1bf4-4847-9044-96ed97cc07ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915116322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.1915116322
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2852563149
Short name T1896
Test name
Test status
Simulation time 3636642889 ps
CPU time 38.05 seconds
Started Mar 12 03:07:37 PM PDT 24
Finished Mar 12 03:08:15 PM PDT 24
Peak memory 253400 kb
Host smart-b28d1ab3-9b0c-4946-bb4c-525369ef8711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852563149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2852563149
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3250621191
Short name T312
Test name
Test status
Simulation time 502518839 ps
CPU time 13.01 seconds
Started Mar 12 03:07:20 PM PDT 24
Finished Mar 12 03:07:34 PM PDT 24
Peak memory 238492 kb
Host smart-106536b7-ec3f-4a39-b54d-631b3f17073a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250621191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3250621191
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1401565075
Short name T580
Test name
Test status
Simulation time 6965673439 ps
CPU time 7.08 seconds
Started Mar 12 03:07:24 PM PDT 24
Finished Mar 12 03:07:32 PM PDT 24
Peak memory 218928 kb
Host smart-ef01ffb8-ac9a-400f-96ca-04069bc3b28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401565075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1401565075
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_intercept.959760446
Short name T1427
Test name
Test status
Simulation time 34245441300 ps
CPU time 11.25 seconds
Started Mar 12 01:11:28 PM PDT 24
Finished Mar 12 01:11:40 PM PDT 24
Peak memory 217688 kb
Host smart-8ad48c5f-422c-4f4a-8ad0-bebdca0f3b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959760446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.959760446
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1307842039
Short name T559
Test name
Test status
Simulation time 1238260226 ps
CPU time 6.08 seconds
Started Mar 12 03:07:20 PM PDT 24
Finished Mar 12 03:07:26 PM PDT 24
Peak memory 232416 kb
Host smart-b5095fb7-5d99-4412-929c-4f534a56912b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307842039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1307842039
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.244409042
Short name T1353
Test name
Test status
Simulation time 12099090021 ps
CPU time 36.25 seconds
Started Mar 12 01:11:17 PM PDT 24
Finished Mar 12 01:11:54 PM PDT 24
Peak memory 246448 kb
Host smart-33224125-d2fa-4efd-aac3-09bbf76c6b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244409042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.244409042
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.1771781748
Short name T1351
Test name
Test status
Simulation time 24937123 ps
CPU time 1.04 seconds
Started Mar 12 03:07:17 PM PDT 24
Finished Mar 12 03:07:19 PM PDT 24
Peak memory 217568 kb
Host smart-6249d9d6-d40a-4efb-8eeb-52cce8dd1aeb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771781748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.1771781748
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.2457952134
Short name T440
Test name
Test status
Simulation time 156502634 ps
CPU time 1.07 seconds
Started Mar 12 01:11:28 PM PDT 24
Finished Mar 12 01:11:30 PM PDT 24
Peak memory 216336 kb
Host smart-d4f38034-ad3a-4c9b-856c-87e991d1a222
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457952134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.2457952134
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1130475063
Short name T1173
Test name
Test status
Simulation time 683449120 ps
CPU time 5.32 seconds
Started Mar 12 03:07:19 PM PDT 24
Finished Mar 12 03:07:25 PM PDT 24
Peak memory 227672 kb
Host smart-c34e7abb-9fec-4d2d-a4d0-f043763c88c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130475063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1130475063
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.946177995
Short name T459
Test name
Test status
Simulation time 4055552537 ps
CPU time 7.07 seconds
Started Mar 12 01:11:16 PM PDT 24
Finished Mar 12 01:11:23 PM PDT 24
Peak memory 217352 kb
Host smart-5716367c-0e05-4b26-8c41-44779f413178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946177995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap
.946177995
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.476375993
Short name T1313
Test name
Test status
Simulation time 107916473650 ps
CPU time 34.04 seconds
Started Mar 12 01:11:21 PM PDT 24
Finished Mar 12 01:11:55 PM PDT 24
Peak memory 240656 kb
Host smart-30226764-970e-4c90-a0c7-b5991529ff6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476375993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.476375993
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.974201443
Short name T1266
Test name
Test status
Simulation time 999901615 ps
CPU time 5.13 seconds
Started Mar 12 03:07:19 PM PDT 24
Finished Mar 12 03:07:25 PM PDT 24
Peak memory 217316 kb
Host smart-d82f3e0a-0458-40b5-9f26-95efa9cf3539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974201443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.974201443
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.1283533341
Short name T1063
Test name
Test status
Simulation time 19088322 ps
CPU time 0.73 seconds
Started Mar 12 01:11:28 PM PDT 24
Finished Mar 12 01:11:29 PM PDT 24
Peak memory 215944 kb
Host smart-65b288df-b5fd-41be-b8be-7806bb3a1109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283533341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.1283533341
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.2177367594
Short name T678
Test name
Test status
Simulation time 17086880 ps
CPU time 0.72 seconds
Started Mar 12 03:07:25 PM PDT 24
Finished Mar 12 03:07:26 PM PDT 24
Peak memory 215940 kb
Host smart-8e2470ef-f68a-4588-a08e-d13d0718a4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177367594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.2177367594
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3293199881
Short name T493
Test name
Test status
Simulation time 871567536 ps
CPU time 5.24 seconds
Started Mar 12 03:07:29 PM PDT 24
Finished Mar 12 03:07:35 PM PDT 24
Peak memory 219788 kb
Host smart-e517889d-52dd-421c-83ae-2ead3fe9d17f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3293199881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3293199881
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.4110087323
Short name T590
Test name
Test status
Simulation time 4384515408 ps
CPU time 3.57 seconds
Started Mar 12 01:11:16 PM PDT 24
Finished Mar 12 01:11:20 PM PDT 24
Peak memory 217252 kb
Host smart-95c8b8f5-b345-42d0-a0eb-fa949510b23e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4110087323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.4110087323
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.1427679449
Short name T1341
Test name
Test status
Simulation time 27605779849 ps
CPU time 245.18 seconds
Started Mar 12 03:07:30 PM PDT 24
Finished Mar 12 03:11:35 PM PDT 24
Peak memory 265368 kb
Host smart-c4b30ef6-4819-436f-97f2-426747cda624
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427679449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.1427679449
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.1476861403
Short name T159
Test name
Test status
Simulation time 14658259874 ps
CPU time 60.67 seconds
Started Mar 12 01:11:31 PM PDT 24
Finished Mar 12 01:12:33 PM PDT 24
Peak memory 239428 kb
Host smart-756f21ed-fa37-4537-83a6-ab3c65bde314
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476861403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.1476861403
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.161938057
Short name T417
Test name
Test status
Simulation time 8733011396 ps
CPU time 35.12 seconds
Started Mar 12 01:11:16 PM PDT 24
Finished Mar 12 01:11:51 PM PDT 24
Peak memory 216084 kb
Host smart-ce3bcb7b-eafb-4c69-8edd-91f7045ee3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161938057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.161938057
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.248041553
Short name T1613
Test name
Test status
Simulation time 2169707837 ps
CPU time 5.43 seconds
Started Mar 12 03:07:21 PM PDT 24
Finished Mar 12 03:07:26 PM PDT 24
Peak memory 216104 kb
Host smart-14c7d35c-6491-4197-ab8a-01d48e359eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248041553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.248041553
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3863220615
Short name T1177
Test name
Test status
Simulation time 1671271745 ps
CPU time 4.03 seconds
Started Mar 12 03:07:19 PM PDT 24
Finished Mar 12 03:07:23 PM PDT 24
Peak memory 207924 kb
Host smart-228ba572-566b-42e0-90c5-9efdf700b277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863220615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3863220615
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3903940224
Short name T1076
Test name
Test status
Simulation time 2000939012 ps
CPU time 3.76 seconds
Started Mar 12 01:11:21 PM PDT 24
Finished Mar 12 01:11:25 PM PDT 24
Peak memory 207928 kb
Host smart-3992e542-6949-43a3-87e6-940f9813c1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903940224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3903940224
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.473933958
Short name T1495
Test name
Test status
Simulation time 731376215 ps
CPU time 3.52 seconds
Started Mar 12 01:11:15 PM PDT 24
Finished Mar 12 01:11:19 PM PDT 24
Peak memory 216184 kb
Host smart-3d21f7f3-3ee2-4c1c-944d-823d2fa37699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473933958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.473933958
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.592592492
Short name T1311
Test name
Test status
Simulation time 78811810 ps
CPU time 4.39 seconds
Started Mar 12 03:07:24 PM PDT 24
Finished Mar 12 03:07:28 PM PDT 24
Peak memory 216076 kb
Host smart-49568388-2e1f-4079-ae7a-b7e53ddba291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592592492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.592592492
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1311658021
Short name T1323
Test name
Test status
Simulation time 95760583 ps
CPU time 0.91 seconds
Started Mar 12 03:07:19 PM PDT 24
Finished Mar 12 03:07:20 PM PDT 24
Peak memory 205192 kb
Host smart-1ee10396-be80-47ff-8f79-071c33fa3314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311658021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1311658021
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3807392169
Short name T1496
Test name
Test status
Simulation time 286522357 ps
CPU time 0.94 seconds
Started Mar 12 01:11:21 PM PDT 24
Finished Mar 12 01:11:22 PM PDT 24
Peak memory 205268 kb
Host smart-614e254b-339d-445e-984b-9e8cf83a62fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807392169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3807392169
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1150559595
Short name T752
Test name
Test status
Simulation time 2193940491 ps
CPU time 9.3 seconds
Started Mar 12 03:07:24 PM PDT 24
Finished Mar 12 03:07:33 PM PDT 24
Peak memory 237112 kb
Host smart-0267c090-ef0f-473b-b3e0-00206ad0da98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150559595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1150559595
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_upload.530952886
Short name T1532
Test name
Test status
Simulation time 1051914874 ps
CPU time 5.09 seconds
Started Mar 12 01:11:29 PM PDT 24
Finished Mar 12 01:11:34 PM PDT 24
Peak memory 219372 kb
Host smart-e22b2328-2e3a-4f57-8cd7-9533082c63f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530952886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.530952886
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1329607108
Short name T1606
Test name
Test status
Simulation time 14943048 ps
CPU time 0.69 seconds
Started Mar 12 03:07:38 PM PDT 24
Finished Mar 12 03:07:40 PM PDT 24
Peak memory 204796 kb
Host smart-5a624319-e5ed-43ac-9bd4-3c000fc1aefa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329607108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1329607108
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2052204898
Short name T634
Test name
Test status
Simulation time 26794014 ps
CPU time 0.72 seconds
Started Mar 12 01:11:33 PM PDT 24
Finished Mar 12 01:11:34 PM PDT 24
Peak memory 205104 kb
Host smart-a7d74ea5-683f-4419-91cd-db2cf55f2a88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052204898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2052204898
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1226946283
Short name T1354
Test name
Test status
Simulation time 198702588 ps
CPU time 3.26 seconds
Started Mar 12 01:11:34 PM PDT 24
Finished Mar 12 01:11:37 PM PDT 24
Peak memory 224164 kb
Host smart-71081f9b-b979-4a92-95a3-b84d943db786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226946283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1226946283
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2375391820
Short name T1328
Test name
Test status
Simulation time 59227486 ps
CPU time 2.14 seconds
Started Mar 12 03:07:40 PM PDT 24
Finished Mar 12 03:07:42 PM PDT 24
Peak memory 218416 kb
Host smart-ce337e46-000e-4f88-a4e5-9b71d797a016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375391820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2375391820
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.75485806
Short name T882
Test name
Test status
Simulation time 20429203 ps
CPU time 0.79 seconds
Started Mar 12 03:07:28 PM PDT 24
Finished Mar 12 03:07:28 PM PDT 24
Peak memory 204932 kb
Host smart-c7b0cf11-3f33-4e2e-82fb-8f3c22be5465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75485806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.75485806
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.943517950
Short name T703
Test name
Test status
Simulation time 19354681 ps
CPU time 0.79 seconds
Started Mar 12 01:11:30 PM PDT 24
Finished Mar 12 01:11:31 PM PDT 24
Peak memory 204916 kb
Host smart-bed497d7-4f46-4544-9e5d-ceb054566d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943517950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.943517950
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1067976637
Short name T1103
Test name
Test status
Simulation time 4510959033 ps
CPU time 13.52 seconds
Started Mar 12 01:11:31 PM PDT 24
Finished Mar 12 01:11:45 PM PDT 24
Peak memory 240628 kb
Host smart-0978700c-c8c8-4f1b-8b4b-a7a9c16774dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067976637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1067976637
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1395379933
Short name T1026
Test name
Test status
Simulation time 227266657178 ps
CPU time 173.74 seconds
Started Mar 12 03:07:29 PM PDT 24
Finished Mar 12 03:10:23 PM PDT 24
Peak memory 257188 kb
Host smart-d4902d34-482e-4d8c-ac84-7d9cff386ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395379933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1395379933
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1422599104
Short name T974
Test name
Test status
Simulation time 29275504474 ps
CPU time 50.06 seconds
Started Mar 12 01:11:36 PM PDT 24
Finished Mar 12 01:12:26 PM PDT 24
Peak memory 248968 kb
Host smart-e80d4fce-7220-4900-8993-dec08676ab2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422599104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1422599104
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2425866650
Short name T748
Test name
Test status
Simulation time 6762340521 ps
CPU time 51.34 seconds
Started Mar 12 03:07:29 PM PDT 24
Finished Mar 12 03:08:21 PM PDT 24
Peak memory 248948 kb
Host smart-a0a7296b-5304-413e-aa00-62cc7b75ec83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425866650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2425866650
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.3237467082
Short name T1335
Test name
Test status
Simulation time 9497906157 ps
CPU time 112.8 seconds
Started Mar 12 03:07:30 PM PDT 24
Finished Mar 12 03:09:23 PM PDT 24
Peak memory 265640 kb
Host smart-8f7ca8e6-4bb1-4721-acc4-e825efdce5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237467082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.3237467082
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.3826798537
Short name T549
Test name
Test status
Simulation time 35379042962 ps
CPU time 78.44 seconds
Started Mar 12 01:11:31 PM PDT 24
Finished Mar 12 01:12:51 PM PDT 24
Peak memory 249996 kb
Host smart-be18a1b6-5d84-462c-bed1-31d63c19ddcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826798537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.3826798537
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1559360117
Short name T1472
Test name
Test status
Simulation time 7426301129 ps
CPU time 26.83 seconds
Started Mar 12 01:11:29 PM PDT 24
Finished Mar 12 01:11:57 PM PDT 24
Peak memory 234392 kb
Host smart-ba1fe767-e34a-4e80-8a55-08acdb5a6f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559360117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1559360117
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.293780230
Short name T1404
Test name
Test status
Simulation time 17726349676 ps
CPU time 54.32 seconds
Started Mar 12 03:07:29 PM PDT 24
Finished Mar 12 03:08:23 PM PDT 24
Peak memory 239636 kb
Host smart-c959e0d5-fa0e-43c2-ae95-a552b3fc097c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293780230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.293780230
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2577096725
Short name T998
Test name
Test status
Simulation time 2892680170 ps
CPU time 6.03 seconds
Started Mar 12 03:07:29 PM PDT 24
Finished Mar 12 03:07:35 PM PDT 24
Peak memory 233264 kb
Host smart-07ff7696-7db3-4f3a-9fb8-7d952d3ef2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577096725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2577096725
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3398373410
Short name T558
Test name
Test status
Simulation time 99825771 ps
CPU time 2.76 seconds
Started Mar 12 01:11:30 PM PDT 24
Finished Mar 12 01:11:33 PM PDT 24
Peak memory 224184 kb
Host smart-85889541-34d5-4ac7-ad52-d7c99f5c3346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398373410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3398373410
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1245960780
Short name T953
Test name
Test status
Simulation time 7831971173 ps
CPU time 25.19 seconds
Started Mar 12 03:07:28 PM PDT 24
Finished Mar 12 03:07:53 PM PDT 24
Peak memory 236976 kb
Host smart-edda57cd-3331-479f-aa2d-694b2e58a962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245960780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1245960780
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1461202216
Short name T455
Test name
Test status
Simulation time 8044479603 ps
CPU time 25.87 seconds
Started Mar 12 01:11:33 PM PDT 24
Finished Mar 12 01:11:59 PM PDT 24
Peak memory 249264 kb
Host smart-688f5d4f-ea03-4448-86e8-b53477701665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461202216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1461202216
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.1793860744
Short name T591
Test name
Test status
Simulation time 93476711 ps
CPU time 1.01 seconds
Started Mar 12 01:11:33 PM PDT 24
Finished Mar 12 01:11:34 PM PDT 24
Peak memory 217576 kb
Host smart-6e402a8c-41d8-4709-bc24-be1d5a1ab66d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793860744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.1793860744
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.570208270
Short name T1467
Test name
Test status
Simulation time 23619927 ps
CPU time 1.08 seconds
Started Mar 12 03:07:39 PM PDT 24
Finished Mar 12 03:07:40 PM PDT 24
Peak memory 216244 kb
Host smart-7583d8ca-d13c-4b40-b79a-311166ac6b0a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570208270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.spi_device_mem_parity.570208270
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1017605836
Short name T1218
Test name
Test status
Simulation time 1727008301 ps
CPU time 6.3 seconds
Started Mar 12 01:11:32 PM PDT 24
Finished Mar 12 01:11:39 PM PDT 24
Peak memory 217556 kb
Host smart-b9bb2ee6-557b-437f-ab13-2c3d51575f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017605836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1017605836
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1798699438
Short name T640
Test name
Test status
Simulation time 15935779656 ps
CPU time 11.55 seconds
Started Mar 12 03:07:30 PM PDT 24
Finished Mar 12 03:07:42 PM PDT 24
Peak memory 224176 kb
Host smart-65a8d8c9-86eb-4acf-9295-0ed244c4479c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798699438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1798699438
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.191404701
Short name T1928
Test name
Test status
Simulation time 41514657983 ps
CPU time 13.71 seconds
Started Mar 12 01:11:32 PM PDT 24
Finished Mar 12 01:11:47 PM PDT 24
Peak memory 226800 kb
Host smart-ac48fa09-8f42-4d6d-8cff-679198371175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191404701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.191404701
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3897940011
Short name T705
Test name
Test status
Simulation time 37837933145 ps
CPU time 23.36 seconds
Started Mar 12 03:07:30 PM PDT 24
Finished Mar 12 03:07:54 PM PDT 24
Peak memory 233464 kb
Host smart-03f51564-0f00-4089-9c1e-f8a119978074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897940011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3897940011
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.3236864893
Short name T364
Test name
Test status
Simulation time 84107130 ps
CPU time 0.72 seconds
Started Mar 12 03:07:39 PM PDT 24
Finished Mar 12 03:07:40 PM PDT 24
Peak memory 215940 kb
Host smart-b5a6f166-d1d3-4ccb-814d-73150d188c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236864893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.3236864893
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.3595537
Short name T1407
Test name
Test status
Simulation time 29923811 ps
CPU time 0.73 seconds
Started Mar 12 01:11:32 PM PDT 24
Finished Mar 12 01:11:34 PM PDT 24
Peak memory 215948 kb
Host smart-ceb0a50e-2803-445f-9af9-4d4e23aefa2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.3595537
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2761671349
Short name T467
Test name
Test status
Simulation time 897753400 ps
CPU time 6.19 seconds
Started Mar 12 03:07:30 PM PDT 24
Finished Mar 12 03:07:36 PM PDT 24
Peak memory 221648 kb
Host smart-22e2bf7f-d5b0-41dc-9a89-f5ef102bc38e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2761671349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2761671349
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3417830658
Short name T737
Test name
Test status
Simulation time 791030421 ps
CPU time 4.9 seconds
Started Mar 12 01:11:33 PM PDT 24
Finished Mar 12 01:11:38 PM PDT 24
Peak memory 218772 kb
Host smart-bf481b98-b101-4c19-96a6-5e975084862c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3417830658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3417830658
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1977246948
Short name T207
Test name
Test status
Simulation time 204671398322 ps
CPU time 283.8 seconds
Started Mar 12 01:11:30 PM PDT 24
Finished Mar 12 01:16:14 PM PDT 24
Peak memory 262052 kb
Host smart-13e5bc92-102a-4608-87a1-5179a5114d40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977246948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1977246948
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.866020346
Short name T294
Test name
Test status
Simulation time 97468379364 ps
CPU time 319.42 seconds
Started Mar 12 03:07:30 PM PDT 24
Finished Mar 12 03:12:50 PM PDT 24
Peak memory 248980 kb
Host smart-5b8f1e3d-43d8-4873-ae8c-f6f13c520078
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866020346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.866020346
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2096288076
Short name T1658
Test name
Test status
Simulation time 22566314993 ps
CPU time 35.29 seconds
Started Mar 12 03:07:31 PM PDT 24
Finished Mar 12 03:08:07 PM PDT 24
Peak memory 216116 kb
Host smart-62d06ec3-1c56-49b3-b669-4eb2fea1feef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096288076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2096288076
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2561082613
Short name T924
Test name
Test status
Simulation time 12025458736 ps
CPU time 26.58 seconds
Started Mar 12 01:11:31 PM PDT 24
Finished Mar 12 01:11:58 PM PDT 24
Peak memory 216128 kb
Host smart-913a49f5-7f70-47d6-9cb8-d1e17cbf6743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561082613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2561082613
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1268585477
Short name T1632
Test name
Test status
Simulation time 8069642071 ps
CPU time 28.1 seconds
Started Mar 12 03:07:28 PM PDT 24
Finished Mar 12 03:07:56 PM PDT 24
Peak memory 216140 kb
Host smart-24bbf5a9-4f98-4edf-98ff-f4c1967c8805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268585477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1268585477
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2449186308
Short name T1209
Test name
Test status
Simulation time 2388944790 ps
CPU time 8.03 seconds
Started Mar 12 01:11:35 PM PDT 24
Finished Mar 12 01:11:43 PM PDT 24
Peak memory 216116 kb
Host smart-7cb5abe6-9f8b-4170-b1d9-6214ba342663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449186308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2449186308
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1597058922
Short name T658
Test name
Test status
Simulation time 87571474 ps
CPU time 3.85 seconds
Started Mar 12 03:07:30 PM PDT 24
Finished Mar 12 03:07:34 PM PDT 24
Peak memory 215896 kb
Host smart-8a5fe6eb-378d-4e77-bac9-e6f35f22753e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597058922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1597058922
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.829718142
Short name T1480
Test name
Test status
Simulation time 75081329 ps
CPU time 3.87 seconds
Started Mar 12 01:11:33 PM PDT 24
Finished Mar 12 01:11:37 PM PDT 24
Peak memory 216152 kb
Host smart-e9f7bddb-ed51-488c-ab26-1f04cc7cd056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829718142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.829718142
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1744429462
Short name T543
Test name
Test status
Simulation time 203094740 ps
CPU time 0.8 seconds
Started Mar 12 01:11:32 PM PDT 24
Finished Mar 12 01:11:34 PM PDT 24
Peak memory 205264 kb
Host smart-5bec7e75-c295-4a98-abfb-20174dbd0d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744429462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1744429462
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3201211295
Short name T456
Test name
Test status
Simulation time 127100005 ps
CPU time 1.09 seconds
Started Mar 12 03:07:30 PM PDT 24
Finished Mar 12 03:07:31 PM PDT 24
Peak memory 206300 kb
Host smart-bccac3c1-c29b-4640-93a9-10ffb3dd68e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201211295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3201211295
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.1469802742
Short name T935
Test name
Test status
Simulation time 5271972405 ps
CPU time 19.82 seconds
Started Mar 12 01:11:31 PM PDT 24
Finished Mar 12 01:11:53 PM PDT 24
Peak memory 229572 kb
Host smart-e59f85a1-ff80-4517-916b-b8379b16e1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469802742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1469802742
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_upload.2800011416
Short name T1924
Test name
Test status
Simulation time 616786159 ps
CPU time 5.83 seconds
Started Mar 12 03:07:37 PM PDT 24
Finished Mar 12 03:07:43 PM PDT 24
Peak memory 235380 kb
Host smart-cf29509e-123d-40b9-893d-b8b91867da56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800011416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2800011416
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3513832556
Short name T1679
Test name
Test status
Simulation time 51969541 ps
CPU time 0.72 seconds
Started Mar 12 03:07:56 PM PDT 24
Finished Mar 12 03:07:57 PM PDT 24
Peak memory 204256 kb
Host smart-c07a23fd-758f-4ba6-ba0d-3db716e592a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513832556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3513832556
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.719333951
Short name T1057
Test name
Test status
Simulation time 12479138 ps
CPU time 0.69 seconds
Started Mar 12 01:11:33 PM PDT 24
Finished Mar 12 01:11:34 PM PDT 24
Peak memory 205052 kb
Host smart-7f14b83d-ccc8-48a1-ae53-cdc0b23f8508
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719333951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.719333951
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3750097663
Short name T925
Test name
Test status
Simulation time 84348678 ps
CPU time 2.7 seconds
Started Mar 12 01:11:32 PM PDT 24
Finished Mar 12 01:11:36 PM PDT 24
Peak memory 233152 kb
Host smart-a5a4ecc7-29f0-481c-a938-783c0113d9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750097663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3750097663
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.4077923055
Short name T846
Test name
Test status
Simulation time 518086193 ps
CPU time 3.97 seconds
Started Mar 12 03:07:42 PM PDT 24
Finished Mar 12 03:07:46 PM PDT 24
Peak memory 232672 kb
Host smart-c1110c0f-c5bf-4ba4-8cf0-45df9548d787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077923055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.4077923055
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1031693437
Short name T1050
Test name
Test status
Simulation time 16960848 ps
CPU time 0.73 seconds
Started Mar 12 03:07:37 PM PDT 24
Finished Mar 12 03:07:38 PM PDT 24
Peak memory 206244 kb
Host smart-85732aa7-dad4-43c9-b62b-568fb5b261f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031693437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1031693437
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1150456207
Short name T770
Test name
Test status
Simulation time 18674086 ps
CPU time 0.75 seconds
Started Mar 12 01:11:34 PM PDT 24
Finished Mar 12 01:11:35 PM PDT 24
Peak memory 205248 kb
Host smart-65a9cba8-d4d5-4a72-8bb1-6f4a424a0910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150456207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1150456207
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1535497191
Short name T1637
Test name
Test status
Simulation time 8794368944 ps
CPU time 89 seconds
Started Mar 12 01:11:30 PM PDT 24
Finished Mar 12 01:13:00 PM PDT 24
Peak memory 268104 kb
Host smart-3b4ae66c-640a-4863-943f-794b81967b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535497191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1535497191
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.776230096
Short name T1601
Test name
Test status
Simulation time 6122164864 ps
CPU time 23.74 seconds
Started Mar 12 03:07:37 PM PDT 24
Finished Mar 12 03:08:01 PM PDT 24
Peak memory 240676 kb
Host smart-dbd27fbc-ca25-4d5d-8f27-48efdd55138a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776230096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.776230096
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2705151740
Short name T1205
Test name
Test status
Simulation time 1071877591879 ps
CPU time 692.05 seconds
Started Mar 12 03:07:45 PM PDT 24
Finished Mar 12 03:19:17 PM PDT 24
Peak memory 262776 kb
Host smart-19c592db-1ef6-4fec-8637-1eb053d438dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705151740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2705151740
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3094819962
Short name T1665
Test name
Test status
Simulation time 10835679777 ps
CPU time 12.28 seconds
Started Mar 12 01:11:33 PM PDT 24
Finished Mar 12 01:11:46 PM PDT 24
Peak memory 233688 kb
Host smart-28447089-987c-41f9-b6d9-b8d497d84644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094819962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3094819962
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1411998675
Short name T400
Test name
Test status
Simulation time 54447406505 ps
CPU time 106.34 seconds
Started Mar 12 01:11:31 PM PDT 24
Finished Mar 12 01:13:19 PM PDT 24
Peak memory 251224 kb
Host smart-bb4bab91-97a7-41a3-b199-b557a4c40a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411998675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1411998675
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3303589870
Short name T1437
Test name
Test status
Simulation time 18690187976 ps
CPU time 124.63 seconds
Started Mar 12 03:07:37 PM PDT 24
Finished Mar 12 03:09:42 PM PDT 24
Peak memory 237896 kb
Host smart-bd83f22f-24a1-4ba6-b70b-2d611de21f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303589870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3303589870
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2425981237
Short name T572
Test name
Test status
Simulation time 2547246950 ps
CPU time 15.85 seconds
Started Mar 12 01:11:31 PM PDT 24
Finished Mar 12 01:11:47 PM PDT 24
Peak memory 234788 kb
Host smart-7e9ddac2-4d2b-4b2d-9bd3-cf1105d02aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425981237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2425981237
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2901458911
Short name T1389
Test name
Test status
Simulation time 640080499 ps
CPU time 20.69 seconds
Started Mar 12 03:07:39 PM PDT 24
Finished Mar 12 03:08:00 PM PDT 24
Peak memory 234196 kb
Host smart-7a517038-3ce3-4697-b6a4-7a52ab57c08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901458911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2901458911
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3664747984
Short name T1099
Test name
Test status
Simulation time 600132522 ps
CPU time 2.62 seconds
Started Mar 12 03:07:45 PM PDT 24
Finished Mar 12 03:07:47 PM PDT 24
Peak memory 216668 kb
Host smart-75e50cc3-b529-43a9-9499-13e32f1a7d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664747984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3664747984
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_intercept.4179982945
Short name T1805
Test name
Test status
Simulation time 726083430 ps
CPU time 4.47 seconds
Started Mar 12 01:11:32 PM PDT 24
Finished Mar 12 01:11:38 PM PDT 24
Peak memory 218420 kb
Host smart-539d5ba3-3860-4354-9c7a-ed71b80b4b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179982945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.4179982945
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3625480541
Short name T788
Test name
Test status
Simulation time 6634600463 ps
CPU time 7.08 seconds
Started Mar 12 01:11:31 PM PDT 24
Finished Mar 12 01:11:39 PM PDT 24
Peak memory 233888 kb
Host smart-907655e0-c8f4-4500-83c2-876ee816eb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625480541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3625480541
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.587058438
Short name T1664
Test name
Test status
Simulation time 226262917 ps
CPU time 2.73 seconds
Started Mar 12 03:07:37 PM PDT 24
Finished Mar 12 03:07:40 PM PDT 24
Peak memory 234004 kb
Host smart-eb71a1f6-8cc8-4818-ae19-d93d0046c9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587058438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.587058438
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.3392337928
Short name T709
Test name
Test status
Simulation time 15828854 ps
CPU time 1.09 seconds
Started Mar 12 03:07:37 PM PDT 24
Finished Mar 12 03:07:39 PM PDT 24
Peak memory 216372 kb
Host smart-2b994905-8629-4545-b26e-59867ce4add8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392337928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.3392337928
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.7532012
Short name T27
Test name
Test status
Simulation time 299554713 ps
CPU time 1.03 seconds
Started Mar 12 01:11:29 PM PDT 24
Finished Mar 12 01:11:31 PM PDT 24
Peak memory 216352 kb
Host smart-1e9debb9-dcc8-43ab-9f7e-288a29034a54
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7532012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST
_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.spi_device_mem_parity.7532012
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3305280908
Short name T1420
Test name
Test status
Simulation time 61879793980 ps
CPU time 39.91 seconds
Started Mar 12 03:07:41 PM PDT 24
Finished Mar 12 03:08:21 PM PDT 24
Peak memory 234524 kb
Host smart-eb0ad616-c98d-47e0-8ebf-a88af9ca0cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305280908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3305280908
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.903077493
Short name T1898
Test name
Test status
Simulation time 2999655578 ps
CPU time 9.45 seconds
Started Mar 12 01:11:33 PM PDT 24
Finished Mar 12 01:11:43 PM PDT 24
Peak memory 223452 kb
Host smart-c63da1ae-eca1-47de-b246-70f2e7b6f470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903077493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.903077493
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1524775206
Short name T1623
Test name
Test status
Simulation time 8453662358 ps
CPU time 7.38 seconds
Started Mar 12 01:11:32 PM PDT 24
Finished Mar 12 01:11:41 PM PDT 24
Peak memory 224272 kb
Host smart-8b056d8f-0969-40c2-bbc1-cbb70c7d3973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524775206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1524775206
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2823925570
Short name T1348
Test name
Test status
Simulation time 12538001612 ps
CPU time 21.08 seconds
Started Mar 12 03:07:43 PM PDT 24
Finished Mar 12 03:08:04 PM PDT 24
Peak memory 228868 kb
Host smart-8b0ad11d-249f-4bfd-87de-ebe03ed9b428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823925570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2823925570
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.2163505536
Short name T1460
Test name
Test status
Simulation time 31714003 ps
CPU time 0.72 seconds
Started Mar 12 03:07:39 PM PDT 24
Finished Mar 12 03:07:40 PM PDT 24
Peak memory 215912 kb
Host smart-61c16441-3a04-44c6-90d9-13c39b7e644f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163505536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.2163505536
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.4093721805
Short name T586
Test name
Test status
Simulation time 17188936 ps
CPU time 0.74 seconds
Started Mar 12 01:11:31 PM PDT 24
Finished Mar 12 01:11:32 PM PDT 24
Peak memory 215996 kb
Host smart-3a61982a-79d0-4431-b32f-e99146cf5a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093721805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.4093721805
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1490760296
Short name T701
Test name
Test status
Simulation time 414183124 ps
CPU time 4.03 seconds
Started Mar 12 01:11:32 PM PDT 24
Finished Mar 12 01:11:37 PM PDT 24
Peak memory 219660 kb
Host smart-16e18aae-a631-44db-aaf7-d98db0e8b579
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1490760296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1490760296
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.4224868590
Short name T780
Test name
Test status
Simulation time 348644536 ps
CPU time 3.97 seconds
Started Mar 12 03:07:43 PM PDT 24
Finished Mar 12 03:07:47 PM PDT 24
Peak memory 219844 kb
Host smart-ccbba058-7f00-4afc-ab36-1d78cba32bef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4224868590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.4224868590
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3487138905
Short name T999
Test name
Test status
Simulation time 230195877 ps
CPU time 1.08 seconds
Started Mar 12 01:11:31 PM PDT 24
Finished Mar 12 01:11:34 PM PDT 24
Peak memory 206252 kb
Host smart-09a1181f-ac58-4e79-9628-32964ace0dad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487138905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3487138905
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.460417508
Short name T571
Test name
Test status
Simulation time 149168543335 ps
CPU time 546.52 seconds
Started Mar 12 03:07:41 PM PDT 24
Finished Mar 12 03:16:47 PM PDT 24
Peak memory 264612 kb
Host smart-05d79152-35d1-413b-a46d-eeb284493257
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460417508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stres
s_all.460417508
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1182540689
Short name T1315
Test name
Test status
Simulation time 16299283302 ps
CPU time 24.48 seconds
Started Mar 12 01:11:30 PM PDT 24
Finished Mar 12 01:11:55 PM PDT 24
Peak memory 216092 kb
Host smart-9b5c5bee-62a5-45ec-a0f0-d50ef721cd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182540689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1182540689
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2492021358
Short name T334
Test name
Test status
Simulation time 222557356 ps
CPU time 2.39 seconds
Started Mar 12 03:07:38 PM PDT 24
Finished Mar 12 03:07:42 PM PDT 24
Peak memory 216044 kb
Host smart-aff4f8b0-2ad6-4d32-93d4-23144151b0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492021358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2492021358
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2314395047
Short name T1178
Test name
Test status
Simulation time 79134406878 ps
CPU time 19.84 seconds
Started Mar 12 01:11:31 PM PDT 24
Finished Mar 12 01:11:51 PM PDT 24
Peak memory 216144 kb
Host smart-fba689c8-eda3-4191-a21f-fc597a7b576b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314395047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2314395047
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.4056761870
Short name T1545
Test name
Test status
Simulation time 322397901 ps
CPU time 1.42 seconds
Started Mar 12 03:07:36 PM PDT 24
Finished Mar 12 03:07:38 PM PDT 24
Peak memory 206552 kb
Host smart-eb47d795-4bb2-417f-ac4e-bf02833e8a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056761870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.4056761870
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3298051514
Short name T1787
Test name
Test status
Simulation time 23938927 ps
CPU time 1.47 seconds
Started Mar 12 03:07:39 PM PDT 24
Finished Mar 12 03:07:41 PM PDT 24
Peak memory 208028 kb
Host smart-faf8e79b-630e-4c5f-9018-afeed55ce3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298051514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3298051514
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.4088086811
Short name T1327
Test name
Test status
Simulation time 266966239 ps
CPU time 0.88 seconds
Started Mar 12 01:11:32 PM PDT 24
Finished Mar 12 01:11:34 PM PDT 24
Peak memory 206440 kb
Host smart-0ff0d933-6fbf-42bb-bb1d-bc61d2f503a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088086811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.4088086811
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1034735321
Short name T1685
Test name
Test status
Simulation time 40821431 ps
CPU time 0.9 seconds
Started Mar 12 01:11:30 PM PDT 24
Finished Mar 12 01:11:31 PM PDT 24
Peak memory 205220 kb
Host smart-55c77702-7c12-46ac-af4e-19a14b0bb56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034735321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1034735321
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.3839272744
Short name T1416
Test name
Test status
Simulation time 421319220 ps
CPU time 0.84 seconds
Started Mar 12 03:07:38 PM PDT 24
Finished Mar 12 03:07:40 PM PDT 24
Peak memory 205284 kb
Host smart-5a6974a3-ebf5-4d04-b01a-b66045e9bc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839272744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3839272744
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2131175992
Short name T972
Test name
Test status
Simulation time 14828838802 ps
CPU time 17.73 seconds
Started Mar 12 01:11:32 PM PDT 24
Finished Mar 12 01:11:51 PM PDT 24
Peak memory 240492 kb
Host smart-40dc2d57-76a9-46a2-915f-b33d3b7bb0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131175992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2131175992
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_upload.425769755
Short name T88
Test name
Test status
Simulation time 5313545825 ps
CPU time 15.29 seconds
Started Mar 12 03:07:43 PM PDT 24
Finished Mar 12 03:07:58 PM PDT 24
Peak memory 247712 kb
Host smart-7633034e-9e94-4c9a-a8be-bf1aef3cf545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425769755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.425769755
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3207508936
Short name T869
Test name
Test status
Simulation time 55416108 ps
CPU time 0.72 seconds
Started Mar 12 03:07:53 PM PDT 24
Finished Mar 12 03:07:54 PM PDT 24
Peak memory 204260 kb
Host smart-d98b1b50-9b0a-4379-bf5a-a8f777842589
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207508936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3207508936
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.4182027852
Short name T1064
Test name
Test status
Simulation time 13810123 ps
CPU time 0.73 seconds
Started Mar 12 01:11:31 PM PDT 24
Finished Mar 12 01:11:32 PM PDT 24
Peak memory 204800 kb
Host smart-d38082a5-e1ac-4e33-90a7-a174ab6e9f08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182027852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
4182027852
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.4093223077
Short name T1723
Test name
Test status
Simulation time 140924830 ps
CPU time 2.48 seconds
Started Mar 12 03:07:48 PM PDT 24
Finished Mar 12 03:07:50 PM PDT 24
Peak memory 232920 kb
Host smart-c2ebd285-ae71-4000-b9b7-44a1da877b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093223077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.4093223077
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.658612914
Short name T809
Test name
Test status
Simulation time 121647898 ps
CPU time 2.42 seconds
Started Mar 12 01:11:31 PM PDT 24
Finished Mar 12 01:11:35 PM PDT 24
Peak memory 223992 kb
Host smart-59513122-964c-4c0e-b578-03692a393b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658612914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.658612914
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1798287982
Short name T391
Test name
Test status
Simulation time 92102900 ps
CPU time 0.8 seconds
Started Mar 12 01:11:34 PM PDT 24
Finished Mar 12 01:11:35 PM PDT 24
Peak memory 205928 kb
Host smart-11179a5e-ef37-4c95-aecc-88658dbe81b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798287982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1798287982
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.282436034
Short name T525
Test name
Test status
Simulation time 63891456 ps
CPU time 0.81 seconds
Started Mar 12 03:07:47 PM PDT 24
Finished Mar 12 03:07:49 PM PDT 24
Peak memory 205956 kb
Host smart-9125388e-ab6d-4c1f-8bc8-2d4dd18c64e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282436034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.282436034
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.948443593
Short name T1761
Test name
Test status
Simulation time 23409861710 ps
CPU time 28.53 seconds
Started Mar 12 03:07:50 PM PDT 24
Finished Mar 12 03:08:18 PM PDT 24
Peak memory 224216 kb
Host smart-3905d0d6-39ea-4b88-b3f9-62759980b014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948443593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.948443593
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.98868776
Short name T1344
Test name
Test status
Simulation time 5887928927 ps
CPU time 55.99 seconds
Started Mar 12 01:11:33 PM PDT 24
Finished Mar 12 01:12:29 PM PDT 24
Peak memory 249352 kb
Host smart-3864582a-4a23-49dc-9a56-1fa44fb59511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98868776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.98868776
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3998662075
Short name T1804
Test name
Test status
Simulation time 13358056216 ps
CPU time 43.37 seconds
Started Mar 12 01:11:32 PM PDT 24
Finished Mar 12 01:12:16 PM PDT 24
Peak memory 253132 kb
Host smart-46b89279-6367-4afc-b1cf-b32a01936406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998662075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3998662075
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.716712134
Short name T1566
Test name
Test status
Simulation time 32029618453 ps
CPU time 232.14 seconds
Started Mar 12 03:07:56 PM PDT 24
Finished Mar 12 03:11:48 PM PDT 24
Peak memory 256628 kb
Host smart-9690c170-a66a-4459-9d28-f5abcdaafd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716712134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.716712134
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3153284651
Short name T1306
Test name
Test status
Simulation time 70936827325 ps
CPU time 498.21 seconds
Started Mar 12 01:11:35 PM PDT 24
Finished Mar 12 01:19:53 PM PDT 24
Peak memory 248972 kb
Host smart-c7d37293-9ec4-4647-96ae-c982e8e781ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153284651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3153284651
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1586245371
Short name T1078
Test name
Test status
Simulation time 1227365329 ps
CPU time 9.54 seconds
Started Mar 12 01:11:35 PM PDT 24
Finished Mar 12 01:11:44 PM PDT 24
Peak memory 247712 kb
Host smart-17814661-451c-4660-a6c6-ecd11394218f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586245371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1586245371
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.4036313115
Short name T866
Test name
Test status
Simulation time 7840072105 ps
CPU time 22.57 seconds
Started Mar 12 03:07:47 PM PDT 24
Finished Mar 12 03:08:10 PM PDT 24
Peak memory 240232 kb
Host smart-ff2b2fca-a6a7-4bfd-a96b-18f2afb65a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036313115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.4036313115
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3486519725
Short name T930
Test name
Test status
Simulation time 843537279 ps
CPU time 3.5 seconds
Started Mar 12 03:07:49 PM PDT 24
Finished Mar 12 03:07:53 PM PDT 24
Peak memory 232444 kb
Host smart-e23058fd-0c3a-4d0e-9770-068b3109f92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486519725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3486519725
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3963218230
Short name T727
Test name
Test status
Simulation time 344444032 ps
CPU time 4.84 seconds
Started Mar 12 01:11:32 PM PDT 24
Finished Mar 12 01:11:38 PM PDT 24
Peak memory 224168 kb
Host smart-9c9920d3-74ca-40d3-be95-923e8206353c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963218230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3963218230
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3812720117
Short name T197
Test name
Test status
Simulation time 494521964 ps
CPU time 5.52 seconds
Started Mar 12 01:11:31 PM PDT 24
Finished Mar 12 01:11:39 PM PDT 24
Peak memory 217248 kb
Host smart-a5557044-636a-485e-9cf7-a941c95660d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812720117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3812720117
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.824946261
Short name T1011
Test name
Test status
Simulation time 1408681005 ps
CPU time 7.52 seconds
Started Mar 12 03:07:47 PM PDT 24
Finished Mar 12 03:07:55 PM PDT 24
Peak memory 218176 kb
Host smart-fc63a828-3fba-4575-a68d-fc39cfdf148b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824946261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.824946261
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.1671812145
Short name T1591
Test name
Test status
Simulation time 61559479 ps
CPU time 1.13 seconds
Started Mar 12 03:07:49 PM PDT 24
Finished Mar 12 03:07:51 PM PDT 24
Peak memory 216372 kb
Host smart-c2348144-9bb7-40ef-8b8e-66f2f28b320d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671812145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.1671812145
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.3212343924
Short name T1436
Test name
Test status
Simulation time 109863422 ps
CPU time 1 seconds
Started Mar 12 01:11:31 PM PDT 24
Finished Mar 12 01:11:32 PM PDT 24
Peak memory 217584 kb
Host smart-55f592c7-fd14-4754-ab73-2a9dbeea7063
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212343924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.3212343924
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1077581222
Short name T299
Test name
Test status
Simulation time 1656592653 ps
CPU time 4.68 seconds
Started Mar 12 01:11:32 PM PDT 24
Finished Mar 12 01:11:38 PM PDT 24
Peak memory 233236 kb
Host smart-97aac4ea-b94c-4f43-a774-87e9d43a643f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077581222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1077581222
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.4042557547
Short name T1244
Test name
Test status
Simulation time 1287100577 ps
CPU time 5.67 seconds
Started Mar 12 03:07:48 PM PDT 24
Finished Mar 12 03:07:54 PM PDT 24
Peak memory 219832 kb
Host smart-e3da232a-8061-4ee8-b5f4-430ccbc4dbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042557547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.4042557547
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1363960971
Short name T89
Test name
Test status
Simulation time 40729850 ps
CPU time 2.12 seconds
Started Mar 12 01:11:34 PM PDT 24
Finished Mar 12 01:11:36 PM PDT 24
Peak memory 224060 kb
Host smart-73af1c4b-8c93-4433-a769-4bcb518c5969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363960971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1363960971
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.284734847
Short name T437
Test name
Test status
Simulation time 2145115217 ps
CPU time 4.91 seconds
Started Mar 12 03:07:50 PM PDT 24
Finished Mar 12 03:07:55 PM PDT 24
Peak memory 234200 kb
Host smart-b31cd938-e1f7-416c-b715-a259aaa87f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284734847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.284734847
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.3060346583
Short name T414
Test name
Test status
Simulation time 35228572 ps
CPU time 0.71 seconds
Started Mar 12 01:11:31 PM PDT 24
Finished Mar 12 01:11:32 PM PDT 24
Peak memory 215956 kb
Host smart-0ecfd5ec-71d9-4b2c-ba7d-a7298a3dc7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060346583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.3060346583
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.3742758035
Short name T1142
Test name
Test status
Simulation time 18169635 ps
CPU time 0.79 seconds
Started Mar 12 03:07:49 PM PDT 24
Finished Mar 12 03:07:49 PM PDT 24
Peak memory 215940 kb
Host smart-eae7a95c-40c0-4057-997a-769709780865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742758035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.3742758035
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2352203259
Short name T1883
Test name
Test status
Simulation time 904008677 ps
CPU time 5.16 seconds
Started Mar 12 03:07:49 PM PDT 24
Finished Mar 12 03:07:54 PM PDT 24
Peak memory 219588 kb
Host smart-b233e7cf-9050-4173-b56a-ea4e7102de1d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2352203259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2352203259
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2634461773
Short name T1575
Test name
Test status
Simulation time 166818045 ps
CPU time 3.4 seconds
Started Mar 12 01:11:33 PM PDT 24
Finished Mar 12 01:11:37 PM PDT 24
Peak memory 222432 kb
Host smart-48881bb7-4e8d-4312-9a2f-d4dc1f546c53
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2634461773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2634461773
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.288036849
Short name T1469
Test name
Test status
Simulation time 24962316331 ps
CPU time 90.68 seconds
Started Mar 12 03:07:53 PM PDT 24
Finished Mar 12 03:09:24 PM PDT 24
Peak memory 250448 kb
Host smart-aba09c35-cb73-427f-b59b-536f47f594d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288036849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.288036849
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2894181922
Short name T1831
Test name
Test status
Simulation time 4564558016 ps
CPU time 24.86 seconds
Started Mar 12 01:11:32 PM PDT 24
Finished Mar 12 01:11:58 PM PDT 24
Peak memory 216140 kb
Host smart-c864f18b-86d9-4909-a766-211ed24ddaa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894181922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2894181922
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3729716663
Short name T1295
Test name
Test status
Simulation time 1576218023 ps
CPU time 16.08 seconds
Started Mar 12 03:07:51 PM PDT 24
Finished Mar 12 03:08:07 PM PDT 24
Peak memory 216036 kb
Host smart-ff916b45-522f-4ef7-b4e3-5a6b5052f17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729716663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3729716663
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3342628022
Short name T636
Test name
Test status
Simulation time 14745225527 ps
CPU time 13.01 seconds
Started Mar 12 01:11:32 PM PDT 24
Finished Mar 12 01:11:46 PM PDT 24
Peak memory 216132 kb
Host smart-35e6e816-e719-4973-b582-80676c7a0de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342628022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3342628022
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.899422438
Short name T1584
Test name
Test status
Simulation time 1278153822 ps
CPU time 7.68 seconds
Started Mar 12 03:07:49 PM PDT 24
Finished Mar 12 03:07:57 PM PDT 24
Peak memory 216020 kb
Host smart-6b9966ed-f38a-405f-8754-82db7ae2b078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899422438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.899422438
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1736484800
Short name T531
Test name
Test status
Simulation time 286183450 ps
CPU time 2.65 seconds
Started Mar 12 01:11:31 PM PDT 24
Finished Mar 12 01:11:36 PM PDT 24
Peak memory 216204 kb
Host smart-8fdbd01e-1d2e-4456-aa6b-15b929bab8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736484800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1736484800
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2219108597
Short name T436
Test name
Test status
Simulation time 209712653 ps
CPU time 6.38 seconds
Started Mar 12 03:07:51 PM PDT 24
Finished Mar 12 03:07:58 PM PDT 24
Peak memory 216080 kb
Host smart-4079c4c6-72b5-4e8f-9c8b-e281fd067122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219108597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2219108597
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1766389724
Short name T1212
Test name
Test status
Simulation time 159358190 ps
CPU time 0.86 seconds
Started Mar 12 03:07:48 PM PDT 24
Finished Mar 12 03:07:49 PM PDT 24
Peak memory 205252 kb
Host smart-03d96248-11e3-411b-bf4d-b39bbd5f538b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766389724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1766389724
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3660347911
Short name T947
Test name
Test status
Simulation time 164450865 ps
CPU time 0.83 seconds
Started Mar 12 01:11:31 PM PDT 24
Finished Mar 12 01:11:32 PM PDT 24
Peak memory 205228 kb
Host smart-1ff274d5-1daf-4a66-a9a5-193ee4f38582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660347911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3660347911
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1019731327
Short name T1230
Test name
Test status
Simulation time 9485694309 ps
CPU time 15.43 seconds
Started Mar 12 01:11:32 PM PDT 24
Finished Mar 12 01:11:49 PM PDT 24
Peak memory 237084 kb
Host smart-7b136489-4a65-4ea5-bcd2-a0151b19cb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019731327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1019731327
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_upload.352650745
Short name T1841
Test name
Test status
Simulation time 463546039 ps
CPU time 5.85 seconds
Started Mar 12 03:07:48 PM PDT 24
Finished Mar 12 03:07:54 PM PDT 24
Peak memory 219412 kb
Host smart-40750fb9-8c26-4ef1-a682-1221a01eed44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352650745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.352650745
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3746480176
Short name T374
Test name
Test status
Simulation time 15820730 ps
CPU time 0.76 seconds
Started Mar 12 01:10:30 PM PDT 24
Finished Mar 12 01:10:31 PM PDT 24
Peak memory 204812 kb
Host smart-417a2185-3a68-4988-a032-527277752c1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746480176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
746480176
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2041849699
Short name T1528
Test name
Test status
Simulation time 1875071852 ps
CPU time 3.6 seconds
Started Mar 12 03:05:28 PM PDT 24
Finished Mar 12 03:05:33 PM PDT 24
Peak memory 217196 kb
Host smart-ae9b1b88-7374-4f86-9c6a-1683a2cd2829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041849699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2041849699
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.267695480
Short name T1698
Test name
Test status
Simulation time 2976629968 ps
CPU time 4.79 seconds
Started Mar 12 01:10:16 PM PDT 24
Finished Mar 12 01:10:22 PM PDT 24
Peak memory 233200 kb
Host smart-017b1fff-0165-4e0e-8758-878245751d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267695480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.267695480
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2439765020
Short name T1852
Test name
Test status
Simulation time 24168027 ps
CPU time 0.76 seconds
Started Mar 12 03:05:18 PM PDT 24
Finished Mar 12 03:05:21 PM PDT 24
Peak memory 206264 kb
Host smart-15f2e508-4f7b-4c3c-95fb-0f03d8ba8578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439765020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2439765020
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.4162594444
Short name T1812
Test name
Test status
Simulation time 81077252 ps
CPU time 0.82 seconds
Started Mar 12 01:10:16 PM PDT 24
Finished Mar 12 01:10:17 PM PDT 24
Peak memory 205952 kb
Host smart-3fb5fe95-d49c-403d-acd5-1eeaff35ba7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162594444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.4162594444
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1195915923
Short name T255
Test name
Test status
Simulation time 39075632437 ps
CPU time 77.21 seconds
Started Mar 12 03:05:29 PM PDT 24
Finished Mar 12 03:06:46 PM PDT 24
Peak memory 248792 kb
Host smart-b5cfa8a4-86a7-45fe-b55e-06b048513f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195915923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1195915923
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1598319104
Short name T1220
Test name
Test status
Simulation time 8051774983 ps
CPU time 31.84 seconds
Started Mar 12 01:10:16 PM PDT 24
Finished Mar 12 01:10:49 PM PDT 24
Peak memory 248776 kb
Host smart-0b2f4d45-eb8c-4141-bfeb-37f50f73f313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598319104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1598319104
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1198438143
Short name T54
Test name
Test status
Simulation time 5549664801 ps
CPU time 98.89 seconds
Started Mar 12 01:10:18 PM PDT 24
Finished Mar 12 01:11:57 PM PDT 24
Peak memory 264212 kb
Host smart-c042319a-4e77-4c9e-82bd-2fc8c8dc9a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198438143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1198438143
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.269372208
Short name T1811
Test name
Test status
Simulation time 239813671661 ps
CPU time 320.16 seconds
Started Mar 12 03:05:28 PM PDT 24
Finished Mar 12 03:10:49 PM PDT 24
Peak memory 255088 kb
Host smart-69411dbc-5911-4ad2-9458-e195e497563b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269372208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.269372208
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1663643339
Short name T1474
Test name
Test status
Simulation time 16599778959 ps
CPU time 193.78 seconds
Started Mar 12 03:05:30 PM PDT 24
Finished Mar 12 03:08:48 PM PDT 24
Peak memory 267176 kb
Host smart-f9c86958-9af4-40cc-9c50-4508993a7315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663643339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1663643339
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.480127401
Short name T300
Test name
Test status
Simulation time 120909500843 ps
CPU time 56.32 seconds
Started Mar 12 01:10:20 PM PDT 24
Finished Mar 12 01:11:17 PM PDT 24
Peak memory 222212 kb
Host smart-a148dbda-4a15-442b-9aa2-059b3457c2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480127401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
480127401
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.4143482102
Short name T1371
Test name
Test status
Simulation time 5840557949 ps
CPU time 12.05 seconds
Started Mar 12 03:05:30 PM PDT 24
Finished Mar 12 03:05:46 PM PDT 24
Peak memory 231256 kb
Host smart-988146c4-b177-44cc-b394-935fd84c87fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143482102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.4143482102
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.161934583
Short name T841
Test name
Test status
Simulation time 7468999358 ps
CPU time 13.3 seconds
Started Mar 12 01:10:22 PM PDT 24
Finished Mar 12 01:10:36 PM PDT 24
Peak memory 232732 kb
Host smart-af313985-e2c4-415d-9483-d3d4ce607565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161934583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.161934583
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3461636873
Short name T1839
Test name
Test status
Simulation time 2536194057 ps
CPU time 3.81 seconds
Started Mar 12 03:05:30 PM PDT 24
Finished Mar 12 03:05:38 PM PDT 24
Peak memory 219896 kb
Host smart-2b403a1a-069d-432e-8639-9ceff3a36ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461636873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3461636873
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2338472855
Short name T241
Test name
Test status
Simulation time 1217794285 ps
CPU time 7.14 seconds
Started Mar 12 01:10:17 PM PDT 24
Finished Mar 12 01:10:25 PM PDT 24
Peak memory 232364 kb
Host smart-3e53db3e-6a6e-4bbd-9ed2-021bbf1793c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338472855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2338472855
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3742611680
Short name T637
Test name
Test status
Simulation time 13509844213 ps
CPU time 21.07 seconds
Started Mar 12 03:05:27 PM PDT 24
Finished Mar 12 03:05:49 PM PDT 24
Peak memory 232464 kb
Host smart-82020b8d-c7b4-49ec-a6ad-b91cb6bc500c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742611680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3742611680
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.1554965605
Short name T683
Test name
Test status
Simulation time 84481976 ps
CPU time 1.14 seconds
Started Mar 12 03:05:18 PM PDT 24
Finished Mar 12 03:05:21 PM PDT 24
Peak memory 216372 kb
Host smart-d7308f71-5106-4c8b-a5b0-4cbbdb701378
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554965605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.1554965605
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.32312035
Short name T1876
Test name
Test status
Simulation time 91522117 ps
CPU time 1 seconds
Started Mar 12 01:10:16 PM PDT 24
Finished Mar 12 01:10:17 PM PDT 24
Peak memory 216256 kb
Host smart-ce3ab788-891f-4515-a155-498900c2563a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32312035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.spi_device_mem_parity.32312035
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1141345091
Short name T1430
Test name
Test status
Simulation time 1128792092 ps
CPU time 5.04 seconds
Started Mar 12 01:10:16 PM PDT 24
Finished Mar 12 01:10:22 PM PDT 24
Peak memory 216312 kb
Host smart-b9c6689d-db90-4632-bb6a-4fea8d904cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141345091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1141345091
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2142525167
Short name T259
Test name
Test status
Simulation time 1102098214 ps
CPU time 4.74 seconds
Started Mar 12 03:05:15 PM PDT 24
Finished Mar 12 03:05:21 PM PDT 24
Peak memory 236224 kb
Host smart-c8c59f4f-8d06-47cf-b25e-d896ea7b16ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142525167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2142525167
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2466048245
Short name T523
Test name
Test status
Simulation time 43962914305 ps
CPU time 15.23 seconds
Started Mar 12 01:10:17 PM PDT 24
Finished Mar 12 01:10:32 PM PDT 24
Peak memory 216556 kb
Host smart-bf8dd138-dad7-422d-ae81-2ca96834d2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466048245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2466048245
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.4039062628
Short name T237
Test name
Test status
Simulation time 1082946936 ps
CPU time 6.24 seconds
Started Mar 12 03:05:18 PM PDT 24
Finished Mar 12 03:05:26 PM PDT 24
Peak memory 232936 kb
Host smart-baeac74c-9709-4be1-94bb-04bc21333ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039062628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.4039062628
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.3257393698
Short name T754
Test name
Test status
Simulation time 26588039 ps
CPU time 0.72 seconds
Started Mar 12 01:10:16 PM PDT 24
Finished Mar 12 01:10:17 PM PDT 24
Peak memory 215932 kb
Host smart-f24222b5-ede3-4593-a192-d71fc712e354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257393698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.3257393698
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.4155954735
Short name T1913
Test name
Test status
Simulation time 19525653 ps
CPU time 0.77 seconds
Started Mar 12 03:05:17 PM PDT 24
Finished Mar 12 03:05:18 PM PDT 24
Peak memory 215992 kb
Host smart-12f9078b-9b48-4998-996d-b8a23449c4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155954735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.4155954735
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1658260438
Short name T438
Test name
Test status
Simulation time 3610840067 ps
CPU time 7.11 seconds
Started Mar 12 01:10:15 PM PDT 24
Finished Mar 12 01:10:23 PM PDT 24
Peak memory 222456 kb
Host smart-2d6ee377-b270-4012-ae5c-5b970cd5bf7c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1658260438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1658260438
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.616398691
Short name T144
Test name
Test status
Simulation time 1118383614 ps
CPU time 5.14 seconds
Started Mar 12 03:05:26 PM PDT 24
Finished Mar 12 03:05:32 PM PDT 24
Peak memory 219536 kb
Host smart-603fe921-afd5-46b6-8d00-5aed898e5d20
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=616398691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.616398691
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1825386593
Short name T70
Test name
Test status
Simulation time 34738904 ps
CPU time 0.99 seconds
Started Mar 12 01:10:27 PM PDT 24
Finished Mar 12 01:10:29 PM PDT 24
Peak memory 234724 kb
Host smart-287e95f8-85c6-4ff2-831b-44e8da2318ca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825386593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1825386593
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3396014183
Short name T67
Test name
Test status
Simulation time 310261921 ps
CPU time 1.19 seconds
Started Mar 12 03:05:28 PM PDT 24
Finished Mar 12 03:05:30 PM PDT 24
Peak memory 235212 kb
Host smart-631c9c36-70c1-49e3-9316-1a0505b43bb2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396014183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3396014183
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1006595607
Short name T704
Test name
Test status
Simulation time 10160124472 ps
CPU time 40.33 seconds
Started Mar 12 01:10:15 PM PDT 24
Finished Mar 12 01:10:55 PM PDT 24
Peak memory 240044 kb
Host smart-42d3b1ca-e6ff-490b-b2b2-aeeb34aa77a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006595607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1006595607
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1027443968
Short name T849
Test name
Test status
Simulation time 45353277 ps
CPU time 1.03 seconds
Started Mar 12 03:05:26 PM PDT 24
Finished Mar 12 03:05:28 PM PDT 24
Peak memory 206352 kb
Host smart-5b27d7b6-55a2-4975-b500-a69edd67769e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027443968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1027443968
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1299278088
Short name T1021
Test name
Test status
Simulation time 588508148 ps
CPU time 3.5 seconds
Started Mar 12 03:05:18 PM PDT 24
Finished Mar 12 03:05:24 PM PDT 24
Peak memory 216016 kb
Host smart-6ffaf8bb-ceb1-4567-a463-5359772ce331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299278088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1299278088
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3603986627
Short name T750
Test name
Test status
Simulation time 11806769402 ps
CPU time 31.47 seconds
Started Mar 12 01:10:17 PM PDT 24
Finished Mar 12 01:10:49 PM PDT 24
Peak memory 216160 kb
Host smart-db2162de-1304-44ca-a110-5e39b60a5841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603986627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3603986627
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.242201478
Short name T1058
Test name
Test status
Simulation time 1682293180 ps
CPU time 2 seconds
Started Mar 12 01:10:17 PM PDT 24
Finished Mar 12 01:10:19 PM PDT 24
Peak memory 207424 kb
Host smart-5e8f96e4-e43e-4d64-b8a2-72bff92742a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242201478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.242201478
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.954703805
Short name T912
Test name
Test status
Simulation time 13934532015 ps
CPU time 18.51 seconds
Started Mar 12 03:05:17 PM PDT 24
Finished Mar 12 03:05:36 PM PDT 24
Peak memory 217100 kb
Host smart-3254672a-914a-4a24-af3b-485aa2f66aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954703805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.954703805
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1082731061
Short name T584
Test name
Test status
Simulation time 1161897613 ps
CPU time 5.61 seconds
Started Mar 12 03:05:16 PM PDT 24
Finished Mar 12 03:05:23 PM PDT 24
Peak memory 216040 kb
Host smart-9ac15bef-3929-4375-ae4d-7b56e561b828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082731061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1082731061
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3929204053
Short name T954
Test name
Test status
Simulation time 252658560 ps
CPU time 2.16 seconds
Started Mar 12 01:10:18 PM PDT 24
Finished Mar 12 01:10:21 PM PDT 24
Peak memory 216120 kb
Host smart-f3d38171-ab43-48b5-af1a-24d78c242d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929204053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3929204053
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1830715364
Short name T570
Test name
Test status
Simulation time 464082012 ps
CPU time 0.97 seconds
Started Mar 12 03:05:17 PM PDT 24
Finished Mar 12 03:05:18 PM PDT 24
Peak memory 205268 kb
Host smart-f2cdbe9f-4dc0-4bad-831f-e962a29b3a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830715364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1830715364
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.548307237
Short name T325
Test name
Test status
Simulation time 58893970 ps
CPU time 0.82 seconds
Started Mar 12 01:10:16 PM PDT 24
Finished Mar 12 01:10:16 PM PDT 24
Peak memory 205228 kb
Host smart-ad2d6a71-a7ca-48b9-8421-5b5e539b4199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548307237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.548307237
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1730507098
Short name T1595
Test name
Test status
Simulation time 10135050236 ps
CPU time 10.52 seconds
Started Mar 12 03:05:29 PM PDT 24
Finished Mar 12 03:05:40 PM PDT 24
Peak memory 239660 kb
Host smart-0e8d3c65-59b2-4e11-bf45-3d351a4a3b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730507098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1730507098
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_upload.2865607466
Short name T720
Test name
Test status
Simulation time 15804167251 ps
CPU time 23.76 seconds
Started Mar 12 01:10:15 PM PDT 24
Finished Mar 12 01:10:39 PM PDT 24
Peak memory 233808 kb
Host smart-a4370137-34f2-41c9-9af6-a0db99200864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865607466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2865607466
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2038526210
Short name T336
Test name
Test status
Simulation time 40365435 ps
CPU time 0.71 seconds
Started Mar 12 01:11:43 PM PDT 24
Finished Mar 12 01:11:44 PM PDT 24
Peak memory 204240 kb
Host smart-3b465132-7da1-43cb-8f04-48eb3c323fcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038526210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2038526210
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2348352400
Short name T1861
Test name
Test status
Simulation time 21733929 ps
CPU time 0.79 seconds
Started Mar 12 03:08:04 PM PDT 24
Finished Mar 12 03:08:05 PM PDT 24
Peak memory 204784 kb
Host smart-5c2a053a-ccf1-449d-9494-ede1f333ff2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348352400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2348352400
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2521429735
Short name T1688
Test name
Test status
Simulation time 5921385846 ps
CPU time 11.73 seconds
Started Mar 12 03:08:04 PM PDT 24
Finished Mar 12 03:08:15 PM PDT 24
Peak memory 219836 kb
Host smart-2dc1632a-ba0a-4967-bd71-2607d38bffa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521429735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2521429735
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3651773726
Short name T1619
Test name
Test status
Simulation time 171130786 ps
CPU time 3.18 seconds
Started Mar 12 01:11:41 PM PDT 24
Finished Mar 12 01:11:44 PM PDT 24
Peak memory 233416 kb
Host smart-9faff540-5ceb-49a0-848a-e204e7cf5829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651773726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3651773726
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3036256037
Short name T1468
Test name
Test status
Simulation time 16560889 ps
CPU time 0.78 seconds
Started Mar 12 01:11:42 PM PDT 24
Finished Mar 12 01:11:43 PM PDT 24
Peak memory 205940 kb
Host smart-ca9f0db7-a000-4fbf-aa29-001bbd45e5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036256037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3036256037
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.552991399
Short name T1616
Test name
Test status
Simulation time 18552921 ps
CPU time 0.76 seconds
Started Mar 12 03:07:49 PM PDT 24
Finished Mar 12 03:07:50 PM PDT 24
Peak memory 204908 kb
Host smart-dd554102-f625-42b7-938a-16a64c9a34f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552991399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.552991399
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2157449921
Short name T170
Test name
Test status
Simulation time 16230261913 ps
CPU time 64.29 seconds
Started Mar 12 03:08:04 PM PDT 24
Finished Mar 12 03:09:09 PM PDT 24
Peak memory 249816 kb
Host smart-dd1f3598-ebb7-4d95-8cd7-87cdbd694d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157449921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2157449921
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3170489553
Short name T1039
Test name
Test status
Simulation time 130582807700 ps
CPU time 112.98 seconds
Started Mar 12 01:11:41 PM PDT 24
Finished Mar 12 01:13:34 PM PDT 24
Peak memory 255868 kb
Host smart-628bc4ff-4006-4090-b758-7a0ffab09673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170489553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3170489553
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2534045538
Short name T611
Test name
Test status
Simulation time 14778786955 ps
CPU time 68.15 seconds
Started Mar 12 01:11:44 PM PDT 24
Finished Mar 12 01:12:52 PM PDT 24
Peak memory 249328 kb
Host smart-1d0e41a1-0c44-4fc0-a9d2-1c46e2c39d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534045538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2534045538
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.492030767
Short name T1661
Test name
Test status
Simulation time 21094730227 ps
CPU time 120.86 seconds
Started Mar 12 03:08:03 PM PDT 24
Finished Mar 12 03:10:04 PM PDT 24
Peak memory 249044 kb
Host smart-fc4b79da-0dc8-44e8-ac5b-d989e21f3c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492030767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.492030767
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.37452561
Short name T1586
Test name
Test status
Simulation time 80157847798 ps
CPU time 161.04 seconds
Started Mar 12 01:11:43 PM PDT 24
Finished Mar 12 01:14:25 PM PDT 24
Peak memory 273060 kb
Host smart-3b86ae05-5651-4741-a501-bc707efe056b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37452561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle.37452561
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2819068904
Short name T1166
Test name
Test status
Simulation time 8531625782 ps
CPU time 27.66 seconds
Started Mar 12 01:11:43 PM PDT 24
Finished Mar 12 01:12:11 PM PDT 24
Peak memory 232320 kb
Host smart-145db5d7-46b9-45d7-aad8-c847dcb88e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819068904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2819068904
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2967464393
Short name T48
Test name
Test status
Simulation time 312712083 ps
CPU time 8.95 seconds
Started Mar 12 03:08:04 PM PDT 24
Finished Mar 12 03:08:13 PM PDT 24
Peak memory 237132 kb
Host smart-4e304e22-8ea1-4e94-9ead-ba94757e6875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967464393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2967464393
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3373645964
Short name T1029
Test name
Test status
Simulation time 970469445 ps
CPU time 4.84 seconds
Started Mar 12 01:11:41 PM PDT 24
Finished Mar 12 01:11:46 PM PDT 24
Peak memory 233148 kb
Host smart-f70bfa81-934c-4ad2-ba9c-59359aa9f05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373645964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3373645964
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_intercept.4015623774
Short name T747
Test name
Test status
Simulation time 199815662 ps
CPU time 5.09 seconds
Started Mar 12 03:08:02 PM PDT 24
Finished Mar 12 03:08:07 PM PDT 24
Peak memory 234524 kb
Host smart-b88f139d-520c-46ff-9690-48c4dd7d3107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015623774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.4015623774
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1616887907
Short name T466
Test name
Test status
Simulation time 5449464418 ps
CPU time 16.61 seconds
Started Mar 12 03:08:04 PM PDT 24
Finished Mar 12 03:08:21 PM PDT 24
Peak memory 236944 kb
Host smart-5d8bdb30-ac9d-4289-97fe-d05ecb03f58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616887907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1616887907
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2099777452
Short name T516
Test name
Test status
Simulation time 12350231298 ps
CPU time 9.98 seconds
Started Mar 12 01:11:46 PM PDT 24
Finished Mar 12 01:11:56 PM PDT 24
Peak memory 232464 kb
Host smart-6f23b62a-ee01-44df-92bc-2e43289fa627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099777452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2099777452
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2469346117
Short name T933
Test name
Test status
Simulation time 16566021969 ps
CPU time 45.22 seconds
Started Mar 12 03:08:01 PM PDT 24
Finished Mar 12 03:08:46 PM PDT 24
Peak memory 254536 kb
Host smart-8c6e2b25-0282-46bc-9ff7-4f6bf90ca4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469346117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2469346117
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.461833909
Short name T469
Test name
Test status
Simulation time 37639207 ps
CPU time 2.2 seconds
Started Mar 12 01:11:44 PM PDT 24
Finished Mar 12 01:11:47 PM PDT 24
Peak memory 232404 kb
Host smart-af47cb62-bda3-4db2-99cc-85e35a763eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461833909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.461833909
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1171107456
Short name T928
Test name
Test status
Simulation time 10015889015 ps
CPU time 21.22 seconds
Started Mar 12 03:08:02 PM PDT 24
Finished Mar 12 03:08:23 PM PDT 24
Peak memory 237312 kb
Host smart-050bd830-6315-424b-b00f-ad279f60c266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171107456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1171107456
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2559085562
Short name T461
Test name
Test status
Simulation time 537386977 ps
CPU time 4.93 seconds
Started Mar 12 01:11:44 PM PDT 24
Finished Mar 12 01:11:49 PM PDT 24
Peak memory 233260 kb
Host smart-39cf798d-b959-4519-a592-f0fcc97013e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559085562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2559085562
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1424324686
Short name T878
Test name
Test status
Simulation time 2017966983 ps
CPU time 4.95 seconds
Started Mar 12 01:11:43 PM PDT 24
Finished Mar 12 01:11:49 PM PDT 24
Peak memory 222356 kb
Host smart-4759e05f-a792-4701-9afa-1449c903c8b7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1424324686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1424324686
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.854817590
Short name T365
Test name
Test status
Simulation time 848175779 ps
CPU time 4.39 seconds
Started Mar 12 03:08:03 PM PDT 24
Finished Mar 12 03:08:07 PM PDT 24
Peak memory 221708 kb
Host smart-e38a410b-8874-45bd-951d-d75497063311
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=854817590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.854817590
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1657974330
Short name T1124
Test name
Test status
Simulation time 22696023362 ps
CPU time 151.36 seconds
Started Mar 12 01:11:42 PM PDT 24
Finished Mar 12 01:14:14 PM PDT 24
Peak memory 273532 kb
Host smart-5c8c68af-0201-43f4-ad65-3a8001d1fc6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657974330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1657974330
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3301389759
Short name T1503
Test name
Test status
Simulation time 24688693249 ps
CPU time 183.3 seconds
Started Mar 12 03:08:03 PM PDT 24
Finished Mar 12 03:11:06 PM PDT 24
Peak memory 249032 kb
Host smart-a34937ba-8d3e-4fcd-a70a-c3afb1bc873e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301389759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3301389759
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.1413998089
Short name T1085
Test name
Test status
Simulation time 945080111 ps
CPU time 5.36 seconds
Started Mar 12 01:11:49 PM PDT 24
Finished Mar 12 01:11:54 PM PDT 24
Peak memory 215956 kb
Host smart-0e4cdf67-6780-4771-a4ab-cb31898d3475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413998089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1413998089
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2420008265
Short name T1666
Test name
Test status
Simulation time 120385143952 ps
CPU time 58.84 seconds
Started Mar 12 03:07:49 PM PDT 24
Finished Mar 12 03:08:48 PM PDT 24
Peak memory 216108 kb
Host smart-8e225013-eec5-41f2-8cc7-2f268dfa5447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420008265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2420008265
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3193415257
Short name T686
Test name
Test status
Simulation time 22341178842 ps
CPU time 17.29 seconds
Started Mar 12 01:11:43 PM PDT 24
Finished Mar 12 01:12:01 PM PDT 24
Peak memory 216104 kb
Host smart-bcc4ec01-bcab-4910-ba80-951c13994b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193415257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3193415257
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.4246481665
Short name T535
Test name
Test status
Simulation time 14457149954 ps
CPU time 23.33 seconds
Started Mar 12 03:07:49 PM PDT 24
Finished Mar 12 03:08:12 PM PDT 24
Peak memory 216144 kb
Host smart-fca3284f-d9f5-4f92-a8d6-e28e547960eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246481665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.4246481665
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2144887157
Short name T711
Test name
Test status
Simulation time 390869313 ps
CPU time 2.5 seconds
Started Mar 12 01:11:46 PM PDT 24
Finished Mar 12 01:11:48 PM PDT 24
Peak memory 216200 kb
Host smart-55830733-6e10-4fbe-b9e4-20186b2a8771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144887157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2144887157
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.3091157316
Short name T1433
Test name
Test status
Simulation time 64495452 ps
CPU time 1.14 seconds
Started Mar 12 03:08:03 PM PDT 24
Finished Mar 12 03:08:04 PM PDT 24
Peak memory 206916 kb
Host smart-f6afdefb-c014-42a7-811a-c43afd87b0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091157316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3091157316
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2500404041
Short name T1939
Test name
Test status
Simulation time 60796132 ps
CPU time 0.75 seconds
Started Mar 12 03:07:48 PM PDT 24
Finished Mar 12 03:07:49 PM PDT 24
Peak memory 205240 kb
Host smart-79623d01-84d9-416b-97e3-b3506f9f59a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500404041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2500404041
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2722608253
Short name T419
Test name
Test status
Simulation time 579562462 ps
CPU time 1.13 seconds
Started Mar 12 01:11:42 PM PDT 24
Finished Mar 12 01:11:44 PM PDT 24
Peak memory 206284 kb
Host smart-d7c0fab2-2987-4d9c-8d24-40cc94ac0b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722608253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2722608253
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.164423165
Short name T1107
Test name
Test status
Simulation time 2587061043 ps
CPU time 19.24 seconds
Started Mar 12 03:08:04 PM PDT 24
Finished Mar 12 03:08:23 PM PDT 24
Peak memory 248480 kb
Host smart-02b72e95-8341-46c7-88e8-5f3017f03ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164423165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.164423165
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_upload.610835748
Short name T520
Test name
Test status
Simulation time 184309573 ps
CPU time 2.87 seconds
Started Mar 12 01:11:41 PM PDT 24
Finished Mar 12 01:11:44 PM PDT 24
Peak memory 232380 kb
Host smart-734ef176-bfa2-41bd-b7ca-9ec995fa242f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610835748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.610835748
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2659953899
Short name T1037
Test name
Test status
Simulation time 44830662 ps
CPU time 0.69 seconds
Started Mar 12 01:11:43 PM PDT 24
Finished Mar 12 01:11:45 PM PDT 24
Peak memory 205120 kb
Host smart-7e40999a-1a4c-46b2-be16-cd259fc6123c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659953899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2659953899
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.505504174
Short name T649
Test name
Test status
Simulation time 22750721 ps
CPU time 0.76 seconds
Started Mar 12 03:08:04 PM PDT 24
Finished Mar 12 03:08:04 PM PDT 24
Peak memory 204208 kb
Host smart-4a8bc9f1-53ca-422c-88d3-1afb7d5d281e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505504174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.505504174
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.3552375353
Short name T1877
Test name
Test status
Simulation time 150188271 ps
CPU time 3.18 seconds
Started Mar 12 03:08:01 PM PDT 24
Finished Mar 12 03:08:05 PM PDT 24
Peak memory 233380 kb
Host smart-7b07111d-817d-4391-8c53-f991558e7b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552375353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3552375353
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.908271232
Short name T931
Test name
Test status
Simulation time 704573624 ps
CPU time 3.58 seconds
Started Mar 12 01:11:44 PM PDT 24
Finished Mar 12 01:11:47 PM PDT 24
Peak memory 232676 kb
Host smart-b584ac32-ba1b-4c1a-8421-38189a0086f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908271232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.908271232
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2518826233
Short name T1387
Test name
Test status
Simulation time 47171103 ps
CPU time 0.73 seconds
Started Mar 12 03:08:04 PM PDT 24
Finished Mar 12 03:08:05 PM PDT 24
Peak memory 205920 kb
Host smart-a87dde51-b244-4b7d-9e48-d926b622ba40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518826233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2518826233
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2875007647
Short name T989
Test name
Test status
Simulation time 65179003 ps
CPU time 0.8 seconds
Started Mar 12 01:11:45 PM PDT 24
Finished Mar 12 01:11:46 PM PDT 24
Peak memory 205928 kb
Host smart-ed3b4f92-7362-47ff-b79c-d9ed6ea818c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875007647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2875007647
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1128862305
Short name T521
Test name
Test status
Simulation time 14303111453 ps
CPU time 68.12 seconds
Started Mar 12 01:11:51 PM PDT 24
Finished Mar 12 01:12:59 PM PDT 24
Peak memory 240096 kb
Host smart-9b53387a-3c6e-40e6-9ef3-45589841028b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128862305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1128862305
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.901272755
Short name T1798
Test name
Test status
Simulation time 3473788725 ps
CPU time 57.78 seconds
Started Mar 12 03:08:04 PM PDT 24
Finished Mar 12 03:09:02 PM PDT 24
Peak memory 265240 kb
Host smart-e1a2da7f-dbec-4b09-8dc6-da8f58539bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901272755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.901272755
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3166945262
Short name T548
Test name
Test status
Simulation time 10931627709 ps
CPU time 36.64 seconds
Started Mar 12 03:08:02 PM PDT 24
Finished Mar 12 03:08:39 PM PDT 24
Peak memory 233620 kb
Host smart-2e3a3e5f-5b5e-41e1-a3ee-8d93442d7c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166945262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3166945262
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.877175541
Short name T915
Test name
Test status
Simulation time 11578579892 ps
CPU time 73.72 seconds
Started Mar 12 01:11:43 PM PDT 24
Finished Mar 12 01:12:57 PM PDT 24
Peak memory 232592 kb
Host smart-42bd6bc8-fa54-4b62-aca8-8f8dc695e584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877175541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.877175541
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1440502428
Short name T1772
Test name
Test status
Simulation time 4684622006 ps
CPU time 60.37 seconds
Started Mar 12 01:11:46 PM PDT 24
Finished Mar 12 01:12:46 PM PDT 24
Peak memory 252868 kb
Host smart-f2d44f71-fbd6-484f-ad49-2b02722c9dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440502428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1440502428
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3481224356
Short name T691
Test name
Test status
Simulation time 102964692116 ps
CPU time 173.12 seconds
Started Mar 12 03:08:02 PM PDT 24
Finished Mar 12 03:10:56 PM PDT 24
Peak memory 264772 kb
Host smart-c7a234ec-9577-48a3-b37a-c41ebf904155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481224356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3481224356
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.186644180
Short name T1263
Test name
Test status
Simulation time 2482589746 ps
CPU time 13.93 seconds
Started Mar 12 03:08:02 PM PDT 24
Finished Mar 12 03:08:16 PM PDT 24
Peak memory 235272 kb
Host smart-18e9c8f2-55d4-4286-adae-056f050c5fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186644180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.186644180
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3324131506
Short name T1596
Test name
Test status
Simulation time 2174946797 ps
CPU time 16.87 seconds
Started Mar 12 01:11:41 PM PDT 24
Finished Mar 12 01:11:59 PM PDT 24
Peak memory 234980 kb
Host smart-a3ea4aa0-a1d9-4644-8d03-f2f778feec2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324131506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3324131506
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1402828045
Short name T1717
Test name
Test status
Simulation time 93182768 ps
CPU time 2.83 seconds
Started Mar 12 01:11:42 PM PDT 24
Finished Mar 12 01:11:45 PM PDT 24
Peak memory 224172 kb
Host smart-a56cc3e8-42f6-441c-b597-37da64e3bee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402828045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1402828045
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1557916191
Short name T762
Test name
Test status
Simulation time 4016153303 ps
CPU time 8.95 seconds
Started Mar 12 03:08:04 PM PDT 24
Finished Mar 12 03:08:13 PM PDT 24
Peak memory 232804 kb
Host smart-d135439c-b591-4f46-8db9-cba12ef9a43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557916191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1557916191
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.146517926
Short name T185
Test name
Test status
Simulation time 15729412275 ps
CPU time 45.81 seconds
Started Mar 12 03:08:02 PM PDT 24
Finished Mar 12 03:08:48 PM PDT 24
Peak memory 239916 kb
Host smart-5c393699-361b-420b-8928-34c2f755e770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146517926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.146517926
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1468179889
Short name T1449
Test name
Test status
Simulation time 122247808721 ps
CPU time 28.5 seconds
Started Mar 12 01:11:43 PM PDT 24
Finished Mar 12 01:12:12 PM PDT 24
Peak memory 224192 kb
Host smart-ceff90fb-02f5-4084-b9d0-5ab05abf286d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468179889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1468179889
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3207045169
Short name T527
Test name
Test status
Simulation time 1694109776 ps
CPU time 7.58 seconds
Started Mar 12 03:08:01 PM PDT 24
Finished Mar 12 03:08:09 PM PDT 24
Peak memory 218228 kb
Host smart-73aef24a-106e-4b1c-b1da-514b51a3a1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207045169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3207045169
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.375115496
Short name T1879
Test name
Test status
Simulation time 1932485012 ps
CPU time 7.6 seconds
Started Mar 12 01:11:45 PM PDT 24
Finished Mar 12 01:11:52 PM PDT 24
Peak memory 222216 kb
Host smart-347e4763-da90-4c31-a4b2-b1e0e516a1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375115496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.375115496
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.4002086049
Short name T1650
Test name
Test status
Simulation time 1602470119 ps
CPU time 5.73 seconds
Started Mar 12 03:08:01 PM PDT 24
Finished Mar 12 03:08:07 PM PDT 24
Peak memory 217856 kb
Host smart-964b728e-c15b-4843-b6aa-ffd4c9740ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002086049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.4002086049
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.4018715203
Short name T623
Test name
Test status
Simulation time 2766156057 ps
CPU time 15.91 seconds
Started Mar 12 01:11:48 PM PDT 24
Finished Mar 12 01:12:04 PM PDT 24
Peak memory 247596 kb
Host smart-acd70963-a611-43e7-b764-dd3c432c5e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018715203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.4018715203
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1940123676
Short name T1126
Test name
Test status
Simulation time 623821057 ps
CPU time 3.37 seconds
Started Mar 12 01:11:39 PM PDT 24
Finished Mar 12 01:11:43 PM PDT 24
Peak memory 218596 kb
Host smart-6967ce86-be4d-4637-940e-f80098cb0f2f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1940123676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1940123676
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.540058067
Short name T1636
Test name
Test status
Simulation time 466711565 ps
CPU time 3.31 seconds
Started Mar 12 03:08:03 PM PDT 24
Finished Mar 12 03:08:07 PM PDT 24
Peak memory 220580 kb
Host smart-110fe7fb-871c-415a-94e0-a7c3241c283f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=540058067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.540058067
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3113272797
Short name T1294
Test name
Test status
Simulation time 16911523713 ps
CPU time 68.46 seconds
Started Mar 12 01:11:43 PM PDT 24
Finished Mar 12 01:12:52 PM PDT 24
Peak memory 249016 kb
Host smart-5a98c31e-956a-4993-a848-c5d5b6ddd40d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113272797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3113272797
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3977522748
Short name T261
Test name
Test status
Simulation time 98644876994 ps
CPU time 342.21 seconds
Started Mar 12 03:08:04 PM PDT 24
Finished Mar 12 03:13:46 PM PDT 24
Peak memory 266108 kb
Host smart-f40b00ef-6371-4672-8528-e558248589e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977522748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3977522748
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2916856364
Short name T1923
Test name
Test status
Simulation time 9905659410 ps
CPU time 27.01 seconds
Started Mar 12 01:11:43 PM PDT 24
Finished Mar 12 01:12:10 PM PDT 24
Peak memory 216116 kb
Host smart-3dc59545-2c52-4ae7-ba05-900d731dabf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916856364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2916856364
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3592351523
Short name T565
Test name
Test status
Simulation time 2761766688 ps
CPU time 31.67 seconds
Started Mar 12 03:08:02 PM PDT 24
Finished Mar 12 03:08:34 PM PDT 24
Peak memory 216076 kb
Host smart-6a95d23a-8412-470f-9ac0-9bb85b1b3ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592351523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3592351523
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2124649034
Short name T1331
Test name
Test status
Simulation time 546349474 ps
CPU time 1.35 seconds
Started Mar 12 03:08:01 PM PDT 24
Finished Mar 12 03:08:03 PM PDT 24
Peak memory 206588 kb
Host smart-a04902c8-11ee-4145-b20c-6818e5e165fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124649034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2124649034
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.734013878
Short name T1708
Test name
Test status
Simulation time 7291967146 ps
CPU time 22.23 seconds
Started Mar 12 01:11:45 PM PDT 24
Finished Mar 12 01:12:08 PM PDT 24
Peak memory 216168 kb
Host smart-164130bf-71ba-46d9-a37d-bc2c112a50d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734013878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.734013878
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1123271375
Short name T1123
Test name
Test status
Simulation time 83615928 ps
CPU time 1.22 seconds
Started Mar 12 03:08:03 PM PDT 24
Finished Mar 12 03:08:04 PM PDT 24
Peak memory 206356 kb
Host smart-fae38975-d77b-4a57-bffe-2e60b9f36ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123271375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1123271375
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2754716214
Short name T1116
Test name
Test status
Simulation time 43499356 ps
CPU time 1.01 seconds
Started Mar 12 01:11:47 PM PDT 24
Finished Mar 12 01:11:48 PM PDT 24
Peak memory 207228 kb
Host smart-9026dd98-6d02-4f02-8f20-574b69e78076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754716214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2754716214
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.184562530
Short name T799
Test name
Test status
Simulation time 29824266 ps
CPU time 0.87 seconds
Started Mar 12 03:08:03 PM PDT 24
Finished Mar 12 03:08:04 PM PDT 24
Peak memory 205260 kb
Host smart-82383b1a-b58a-47ac-a396-c1264f4bde11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184562530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.184562530
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2828174283
Short name T1573
Test name
Test status
Simulation time 15418875 ps
CPU time 0.73 seconds
Started Mar 12 01:11:44 PM PDT 24
Finished Mar 12 01:11:45 PM PDT 24
Peak memory 205184 kb
Host smart-bfadff7e-c8ae-4d21-a709-f1f952056416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828174283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2828174283
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3195508852
Short name T1702
Test name
Test status
Simulation time 609774228 ps
CPU time 6.26 seconds
Started Mar 12 03:08:04 PM PDT 24
Finished Mar 12 03:08:11 PM PDT 24
Peak memory 231576 kb
Host smart-4af4d9e3-faeb-48a6-bac7-a043a9c027a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195508852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3195508852
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_upload.4288672177
Short name T1524
Test name
Test status
Simulation time 434039769 ps
CPU time 4.77 seconds
Started Mar 12 01:11:46 PM PDT 24
Finished Mar 12 01:11:51 PM PDT 24
Peak memory 239724 kb
Host smart-58d1f908-42b6-4956-9163-81385d4f7a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288672177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.4288672177
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1028227916
Short name T1083
Test name
Test status
Simulation time 24078006 ps
CPU time 0.7 seconds
Started Mar 12 01:11:44 PM PDT 24
Finished Mar 12 01:11:45 PM PDT 24
Peak memory 204780 kb
Host smart-fea737a4-5e92-4b26-9bf5-297270b7c3ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028227916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1028227916
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1610398408
Short name T1122
Test name
Test status
Simulation time 42452515 ps
CPU time 0.72 seconds
Started Mar 12 03:08:14 PM PDT 24
Finished Mar 12 03:08:15 PM PDT 24
Peak memory 205168 kb
Host smart-a7962e6b-11cd-42f5-a4fc-e93e2279b2b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610398408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1610398408
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2025764951
Short name T1261
Test name
Test status
Simulation time 22465246385 ps
CPU time 6.93 seconds
Started Mar 12 03:08:14 PM PDT 24
Finished Mar 12 03:08:22 PM PDT 24
Peak memory 234236 kb
Host smart-cd02bca6-b6ca-4a6e-9d54-1c5361bd827a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025764951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2025764951
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2571097402
Short name T243
Test name
Test status
Simulation time 133389610 ps
CPU time 2.82 seconds
Started Mar 12 01:11:39 PM PDT 24
Finished Mar 12 01:11:42 PM PDT 24
Peak memory 224180 kb
Host smart-914a26b5-f77b-4bd9-96ef-44fd6bd05517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571097402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2571097402
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3101146224
Short name T1808
Test name
Test status
Simulation time 67397738 ps
CPU time 0.74 seconds
Started Mar 12 01:11:42 PM PDT 24
Finished Mar 12 01:11:43 PM PDT 24
Peak memory 204880 kb
Host smart-d9b85e93-4bfd-4227-aa6b-daea37fceca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101146224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3101146224
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3610430453
Short name T164
Test name
Test status
Simulation time 43388728 ps
CPU time 0.74 seconds
Started Mar 12 03:08:03 PM PDT 24
Finished Mar 12 03:08:04 PM PDT 24
Peak memory 205124 kb
Host smart-f6f19193-2222-4c3a-adea-61575ce3e8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610430453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3610430453
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2036860700
Short name T1677
Test name
Test status
Simulation time 678737784 ps
CPU time 5.09 seconds
Started Mar 12 01:11:42 PM PDT 24
Finished Mar 12 01:11:47 PM PDT 24
Peak memory 233800 kb
Host smart-47f4955d-be8c-4664-8c94-8fb1e4718908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036860700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2036860700
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2651979751
Short name T279
Test name
Test status
Simulation time 30120073778 ps
CPU time 97.73 seconds
Started Mar 12 03:08:13 PM PDT 24
Finished Mar 12 03:09:51 PM PDT 24
Peak memory 267296 kb
Host smart-9a68f5a4-2303-4e7c-b2cb-3adb33a74131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651979751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2651979751
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2202118154
Short name T1829
Test name
Test status
Simulation time 50057454021 ps
CPU time 343.61 seconds
Started Mar 12 03:08:17 PM PDT 24
Finished Mar 12 03:14:02 PM PDT 24
Peak memory 249244 kb
Host smart-46a7cd6a-735f-4071-aa5b-397c9b127b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202118154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2202118154
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3967587571
Short name T39
Test name
Test status
Simulation time 10921440967 ps
CPU time 75.8 seconds
Started Mar 12 01:11:44 PM PDT 24
Finished Mar 12 01:13:00 PM PDT 24
Peak memory 250008 kb
Host smart-125f831b-e246-47d2-abd5-2bb609dcad5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967587571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3967587571
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1227458238
Short name T413
Test name
Test status
Simulation time 5729917122 ps
CPU time 27.28 seconds
Started Mar 12 01:11:44 PM PDT 24
Finished Mar 12 01:12:11 PM PDT 24
Peak memory 245592 kb
Host smart-496ccf8c-dcf3-4d62-9b96-e81c9a7178e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227458238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1227458238
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.496808968
Short name T1339
Test name
Test status
Simulation time 2448558168 ps
CPU time 12.81 seconds
Started Mar 12 03:08:13 PM PDT 24
Finished Mar 12 03:08:26 PM PDT 24
Peak memory 239244 kb
Host smart-27e70ac7-e27a-474f-8aaf-624ba6bb726b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496808968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.496808968
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.240685717
Short name T74
Test name
Test status
Simulation time 762928064 ps
CPU time 3.32 seconds
Started Mar 12 01:11:41 PM PDT 24
Finished Mar 12 01:11:45 PM PDT 24
Peak memory 233628 kb
Host smart-6acdca78-3e2a-48bf-9d1e-08e4799ac425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240685717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.240685717
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_intercept.791494009
Short name T478
Test name
Test status
Simulation time 2313684965 ps
CPU time 10.33 seconds
Started Mar 12 03:08:16 PM PDT 24
Finished Mar 12 03:08:26 PM PDT 24
Peak memory 232664 kb
Host smart-389b99ea-ebe7-4470-a021-1216d0f068a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791494009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.791494009
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1932602865
Short name T1457
Test name
Test status
Simulation time 21862232826 ps
CPU time 19.09 seconds
Started Mar 12 03:08:14 PM PDT 24
Finished Mar 12 03:08:35 PM PDT 24
Peak memory 233640 kb
Host smart-1b9ec5e5-593c-4f26-bb05-9c24be39f80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932602865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1932602865
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2483090425
Short name T1114
Test name
Test status
Simulation time 128242632688 ps
CPU time 54.69 seconds
Started Mar 12 01:11:49 PM PDT 24
Finished Mar 12 01:12:43 PM PDT 24
Peak memory 233472 kb
Host smart-200abe23-b883-42d6-8c5c-f4ebeafd5191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483090425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2483090425
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1085250224
Short name T731
Test name
Test status
Simulation time 466962467 ps
CPU time 6.67 seconds
Started Mar 12 01:11:40 PM PDT 24
Finished Mar 12 01:11:47 PM PDT 24
Peak memory 233040 kb
Host smart-45362860-2716-4289-b300-79c294adfb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085250224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1085250224
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1743471310
Short name T38
Test name
Test status
Simulation time 100501040991 ps
CPU time 20.54 seconds
Started Mar 12 03:08:17 PM PDT 24
Finished Mar 12 03:08:38 PM PDT 24
Peak memory 232492 kb
Host smart-de7a6cc8-007c-49c8-8cab-6326ffc1c096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743471310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1743471310
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2392434868
Short name T1890
Test name
Test status
Simulation time 30307360916 ps
CPU time 9.82 seconds
Started Mar 12 01:11:41 PM PDT 24
Finished Mar 12 01:11:51 PM PDT 24
Peak memory 232420 kb
Host smart-c23d137e-a0ee-419d-afa8-d4b8400ef59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392434868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2392434868
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.4114217130
Short name T504
Test name
Test status
Simulation time 268140120 ps
CPU time 2.97 seconds
Started Mar 12 03:08:15 PM PDT 24
Finished Mar 12 03:08:18 PM PDT 24
Peak memory 233204 kb
Host smart-c9cf7e9f-fabc-4dd4-9766-c3ee30281021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114217130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.4114217130
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1729921065
Short name T75
Test name
Test status
Simulation time 540754369 ps
CPU time 3.16 seconds
Started Mar 12 01:11:44 PM PDT 24
Finished Mar 12 01:11:47 PM PDT 24
Peak memory 219600 kb
Host smart-af9878ca-904f-4762-a2e9-0c38dbadc9af
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1729921065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1729921065
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2033776376
Short name T738
Test name
Test status
Simulation time 233276982 ps
CPU time 3.83 seconds
Started Mar 12 03:08:16 PM PDT 24
Finished Mar 12 03:08:19 PM PDT 24
Peak memory 221924 kb
Host smart-36c49e2e-97a3-42ea-956f-a6ea934695ba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2033776376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2033776376
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.5393309
Short name T979
Test name
Test status
Simulation time 116894370589 ps
CPU time 194.25 seconds
Started Mar 12 03:08:15 PM PDT 24
Finished Mar 12 03:11:30 PM PDT 24
Peak memory 240516 kb
Host smart-3dd9876b-8b51-4477-855c-9b0b835960dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5393309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stress_
all.5393309
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2965532860
Short name T1228
Test name
Test status
Simulation time 9035855973 ps
CPU time 46.64 seconds
Started Mar 12 03:08:04 PM PDT 24
Finished Mar 12 03:08:51 PM PDT 24
Peak memory 216160 kb
Host smart-6de70ede-1e75-446c-866b-e58ddc7ee293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965532860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2965532860
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.781669338
Short name T638
Test name
Test status
Simulation time 6846690900 ps
CPU time 17.16 seconds
Started Mar 12 01:11:42 PM PDT 24
Finished Mar 12 01:12:00 PM PDT 24
Peak memory 216152 kb
Host smart-0feaaa42-ad0b-4638-b568-91e7456987af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781669338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.781669338
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1175653579
Short name T1405
Test name
Test status
Simulation time 1893203254 ps
CPU time 4.78 seconds
Started Mar 12 03:08:05 PM PDT 24
Finished Mar 12 03:08:10 PM PDT 24
Peak memory 216108 kb
Host smart-237bdd23-4373-49a7-a4e6-92b275804495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175653579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1175653579
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.331515544
Short name T745
Test name
Test status
Simulation time 7096667658 ps
CPU time 3.84 seconds
Started Mar 12 01:11:49 PM PDT 24
Finished Mar 12 01:11:53 PM PDT 24
Peak memory 207712 kb
Host smart-dd769000-09fd-44ae-97f3-801160d777f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331515544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.331515544
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1662142033
Short name T1801
Test name
Test status
Simulation time 382576165 ps
CPU time 1.37 seconds
Started Mar 12 03:08:15 PM PDT 24
Finished Mar 12 03:08:17 PM PDT 24
Peak memory 208116 kb
Host smart-2f77d4ac-d71c-4b88-a46a-89fa4b13b0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662142033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1662142033
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.365232417
Short name T1621
Test name
Test status
Simulation time 431437865 ps
CPU time 1.79 seconds
Started Mar 12 01:11:44 PM PDT 24
Finished Mar 12 01:11:46 PM PDT 24
Peak memory 216076 kb
Host smart-4c31b831-1094-43df-84b4-ac8ec3607e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365232417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.365232417
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1008487880
Short name T1907
Test name
Test status
Simulation time 82070496 ps
CPU time 0.7 seconds
Started Mar 12 01:11:44 PM PDT 24
Finished Mar 12 01:11:45 PM PDT 24
Peak memory 205204 kb
Host smart-33e9ba49-9838-4980-959e-fda295c765b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008487880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1008487880
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2328882716
Short name T791
Test name
Test status
Simulation time 84778789 ps
CPU time 0.94 seconds
Started Mar 12 03:08:17 PM PDT 24
Finished Mar 12 03:08:18 PM PDT 24
Peak memory 205236 kb
Host smart-3e3e4fe9-3db9-45d9-8081-2929f6c057e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328882716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2328882716
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2961599186
Short name T1940
Test name
Test status
Simulation time 1091654013 ps
CPU time 5.28 seconds
Started Mar 12 03:08:12 PM PDT 24
Finished Mar 12 03:08:18 PM PDT 24
Peak memory 217988 kb
Host smart-6e1dd328-2b63-4f64-aae2-62fbbf3b1871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961599186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2961599186
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_upload.962769878
Short name T268
Test name
Test status
Simulation time 10138576928 ps
CPU time 13.42 seconds
Started Mar 12 01:11:41 PM PDT 24
Finished Mar 12 01:11:55 PM PDT 24
Peak memory 229136 kb
Host smart-aaef59f3-1724-4183-89c7-9bd6badf6681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962769878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.962769878
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2605629272
Short name T685
Test name
Test status
Simulation time 19763100 ps
CPU time 0.71 seconds
Started Mar 12 01:11:50 PM PDT 24
Finished Mar 12 01:11:51 PM PDT 24
Peak memory 204800 kb
Host smart-fcb5b4ce-b1b4-4af0-99a4-b3523812435b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605629272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2605629272
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3859944350
Short name T1590
Test name
Test status
Simulation time 24405830 ps
CPU time 0.74 seconds
Started Mar 12 03:08:13 PM PDT 24
Finished Mar 12 03:08:14 PM PDT 24
Peak memory 204772 kb
Host smart-6c5621d9-3ae3-4ff2-9269-211cd63c9b7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859944350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3859944350
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2297642622
Short name T1440
Test name
Test status
Simulation time 3302128591 ps
CPU time 7.02 seconds
Started Mar 12 03:08:14 PM PDT 24
Finished Mar 12 03:08:21 PM PDT 24
Peak memory 224272 kb
Host smart-cc3a06c7-8fff-4663-a860-506e7cdb399a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297642622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2297642622
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.3064021265
Short name T894
Test name
Test status
Simulation time 287031876 ps
CPU time 2.86 seconds
Started Mar 12 01:11:49 PM PDT 24
Finished Mar 12 01:11:53 PM PDT 24
Peak memory 217328 kb
Host smart-aee0b9ff-2633-41e4-b0b1-2f750a3760f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064021265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3064021265
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1984940807
Short name T58
Test name
Test status
Simulation time 199578494 ps
CPU time 0.75 seconds
Started Mar 12 03:08:13 PM PDT 24
Finished Mar 12 03:08:14 PM PDT 24
Peak memory 204924 kb
Host smart-397df363-3913-46de-b25e-378e945166c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984940807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1984940807
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.946629308
Short name T1786
Test name
Test status
Simulation time 21798739 ps
CPU time 0.79 seconds
Started Mar 12 01:11:42 PM PDT 24
Finished Mar 12 01:11:43 PM PDT 24
Peak memory 205912 kb
Host smart-dc7e663b-2bed-49e0-be6e-61c6a3c4bfbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946629308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.946629308
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1929619831
Short name T1329
Test name
Test status
Simulation time 19905198743 ps
CPU time 103.58 seconds
Started Mar 12 03:08:19 PM PDT 24
Finished Mar 12 03:10:03 PM PDT 24
Peak memory 248876 kb
Host smart-af6e3c86-86af-493b-bc30-accc890a5eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929619831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1929619831
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2588770382
Short name T1844
Test name
Test status
Simulation time 27935688728 ps
CPU time 177.43 seconds
Started Mar 12 01:11:47 PM PDT 24
Finished Mar 12 01:14:44 PM PDT 24
Peak memory 252688 kb
Host smart-ccff8d25-73a2-4ae8-a380-7c4ded0bd57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588770382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2588770382
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1743826739
Short name T1571
Test name
Test status
Simulation time 18687378987 ps
CPU time 124.92 seconds
Started Mar 12 03:08:14 PM PDT 24
Finished Mar 12 03:10:19 PM PDT 24
Peak memory 240140 kb
Host smart-b6d2a2f4-7fe7-4c46-a194-3e323d981a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743826739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1743826739
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.2436447706
Short name T874
Test name
Test status
Simulation time 9732803407 ps
CPU time 125.36 seconds
Started Mar 12 01:11:48 PM PDT 24
Finished Mar 12 01:13:53 PM PDT 24
Peak memory 255664 kb
Host smart-676b09b4-7a90-44a3-a459-65581f66023e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436447706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2436447706
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1729181705
Short name T749
Test name
Test status
Simulation time 2015505167 ps
CPU time 39.51 seconds
Started Mar 12 03:08:14 PM PDT 24
Finished Mar 12 03:08:55 PM PDT 24
Peak memory 232536 kb
Host smart-7bc28645-d1b4-4293-aa1a-1afdae424ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729181705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.1729181705
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.4222131356
Short name T262
Test name
Test status
Simulation time 19679556954 ps
CPU time 126.27 seconds
Started Mar 12 01:11:48 PM PDT 24
Finished Mar 12 01:13:54 PM PDT 24
Peak memory 249808 kb
Host smart-40c862a0-583f-4ee9-b504-4ab395a58682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222131356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.4222131356
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1185343977
Short name T1325
Test name
Test status
Simulation time 1921372782 ps
CPU time 9.84 seconds
Started Mar 12 03:08:15 PM PDT 24
Finished Mar 12 03:08:25 PM PDT 24
Peak memory 238676 kb
Host smart-be51591e-3e19-464c-957b-ed8f16933a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185343977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1185343977
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2740998713
Short name T199
Test name
Test status
Simulation time 6637154538 ps
CPU time 3.32 seconds
Started Mar 12 01:11:42 PM PDT 24
Finished Mar 12 01:11:46 PM PDT 24
Peak memory 224224 kb
Host smart-e3f7d0a7-3a7a-4cf7-9c51-6d2e62f12b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740998713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2740998713
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_intercept.558936832
Short name T1278
Test name
Test status
Simulation time 308487377 ps
CPU time 3.05 seconds
Started Mar 12 03:08:14 PM PDT 24
Finished Mar 12 03:08:17 PM PDT 24
Peak memory 233636 kb
Host smart-0606fd1b-3ad9-4d86-b555-1785a058ee1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558936832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.558936832
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3475234443
Short name T842
Test name
Test status
Simulation time 793903767 ps
CPU time 2.81 seconds
Started Mar 12 01:11:49 PM PDT 24
Finished Mar 12 01:11:53 PM PDT 24
Peak memory 216496 kb
Host smart-f2545d6f-d4c9-48be-89f2-c5d866cb1158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475234443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3475234443
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.938006847
Short name T585
Test name
Test status
Simulation time 4743055803 ps
CPU time 8.27 seconds
Started Mar 12 03:08:15 PM PDT 24
Finished Mar 12 03:08:24 PM PDT 24
Peak memory 228960 kb
Host smart-c22467df-c8bb-4459-9919-1ad9e9de6e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938006847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.938006847
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2653302597
Short name T742
Test name
Test status
Simulation time 1144041632 ps
CPU time 6.29 seconds
Started Mar 12 03:08:14 PM PDT 24
Finished Mar 12 03:08:20 PM PDT 24
Peak memory 233300 kb
Host smart-0870d555-0250-424d-9418-4f72000b3584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653302597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2653302597
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.441202092
Short name T792
Test name
Test status
Simulation time 12030986978 ps
CPU time 26.95 seconds
Started Mar 12 01:11:49 PM PDT 24
Finished Mar 12 01:12:16 PM PDT 24
Peak memory 233328 kb
Host smart-d418a1c1-af20-4d9f-9b7c-a92e39b26d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441202092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.441202092
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.2143349384
Short name T567
Test name
Test status
Simulation time 21779474963 ps
CPU time 14.3 seconds
Started Mar 12 01:11:43 PM PDT 24
Finished Mar 12 01:11:58 PM PDT 24
Peak memory 245024 kb
Host smart-359bbd96-7306-4577-aecf-4d6508edea5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143349384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2143349384
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3244076185
Short name T1917
Test name
Test status
Simulation time 994412610 ps
CPU time 4.46 seconds
Started Mar 12 03:08:14 PM PDT 24
Finished Mar 12 03:08:20 PM PDT 24
Peak memory 232800 kb
Host smart-5433b831-4b33-463c-8a18-35d8503c3a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244076185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3244076185
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.282470277
Short name T967
Test name
Test status
Simulation time 478036159 ps
CPU time 4.18 seconds
Started Mar 12 03:08:13 PM PDT 24
Finished Mar 12 03:08:17 PM PDT 24
Peak memory 221800 kb
Host smart-c4022063-c1e7-404b-91e9-4590922e2703
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=282470277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.282470277
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3434176139
Short name T1362
Test name
Test status
Simulation time 331733232 ps
CPU time 4.14 seconds
Started Mar 12 01:11:48 PM PDT 24
Finished Mar 12 01:11:52 PM PDT 24
Peak memory 220144 kb
Host smart-c6351545-ec9c-4756-8d9a-96c9b259799e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3434176139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3434176139
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1245828820
Short name T1800
Test name
Test status
Simulation time 162808066894 ps
CPU time 375.53 seconds
Started Mar 12 03:08:14 PM PDT 24
Finished Mar 12 03:14:29 PM PDT 24
Peak memory 266604 kb
Host smart-cec26607-d829-4879-a2b6-a1756411e4cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245828820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1245828820
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.634406477
Short name T233
Test name
Test status
Simulation time 185980751033 ps
CPU time 341.8 seconds
Started Mar 12 01:11:48 PM PDT 24
Finished Mar 12 01:17:30 PM PDT 24
Peak memory 266948 kb
Host smart-c1e073f5-d755-43e4-a8a4-67bbe416cfaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634406477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.634406477
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3700513324
Short name T987
Test name
Test status
Simulation time 8562699735 ps
CPU time 45 seconds
Started Mar 12 01:11:51 PM PDT 24
Finished Mar 12 01:12:36 PM PDT 24
Peak memory 216112 kb
Host smart-2ae992d0-1068-4538-9a69-8fa47b18b825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700513324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3700513324
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1594016046
Short name T1235
Test name
Test status
Simulation time 928716264 ps
CPU time 5.26 seconds
Started Mar 12 01:11:47 PM PDT 24
Finished Mar 12 01:11:52 PM PDT 24
Peak memory 207792 kb
Host smart-1e949e36-41b9-495e-8b79-b2c7e8f2961e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594016046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1594016046
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3518661935
Short name T1669
Test name
Test status
Simulation time 60323066 ps
CPU time 1.17 seconds
Started Mar 12 03:08:13 PM PDT 24
Finished Mar 12 03:08:14 PM PDT 24
Peak memory 206296 kb
Host smart-12ebdd3e-73fb-4cea-9d2a-eeeaf24ed242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518661935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3518661935
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3086080349
Short name T812
Test name
Test status
Simulation time 297552113 ps
CPU time 1.31 seconds
Started Mar 12 01:11:49 PM PDT 24
Finished Mar 12 01:11:51 PM PDT 24
Peak memory 216052 kb
Host smart-152d07f4-e6a8-4001-a8d8-4a7ee2e10959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086080349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3086080349
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3886377819
Short name T816
Test name
Test status
Simulation time 31247779 ps
CPU time 1.78 seconds
Started Mar 12 03:08:16 PM PDT 24
Finished Mar 12 03:08:18 PM PDT 24
Peak memory 216172 kb
Host smart-60ccee2a-e52a-4bc0-867e-811ca3d502b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886377819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3886377819
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1487565408
Short name T1111
Test name
Test status
Simulation time 52549327 ps
CPU time 0.74 seconds
Started Mar 12 03:08:14 PM PDT 24
Finished Mar 12 03:08:16 PM PDT 24
Peak memory 205252 kb
Host smart-edf314d4-691d-484f-955b-5779a295b2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487565408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1487565408
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3188727209
Short name T824
Test name
Test status
Simulation time 228531404 ps
CPU time 0.71 seconds
Started Mar 12 01:11:43 PM PDT 24
Finished Mar 12 01:11:44 PM PDT 24
Peak memory 205212 kb
Host smart-a354fccf-3d3d-4089-b108-332c6c01fa47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188727209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3188727209
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2530646749
Short name T956
Test name
Test status
Simulation time 372342193 ps
CPU time 3.06 seconds
Started Mar 12 03:08:15 PM PDT 24
Finished Mar 12 03:08:19 PM PDT 24
Peak memory 216992 kb
Host smart-bb8610c0-a87f-4068-ac1a-587bcdbd7f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530646749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2530646749
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_upload.3589439590
Short name T1476
Test name
Test status
Simulation time 234341474 ps
CPU time 2.21 seconds
Started Mar 12 01:11:42 PM PDT 24
Finished Mar 12 01:11:45 PM PDT 24
Peak memory 216036 kb
Host smart-6e40fdfd-9624-4d12-8e53-e923c65df676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589439590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3589439590
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2808540087
Short name T1652
Test name
Test status
Simulation time 48739830 ps
CPU time 0.71 seconds
Started Mar 12 01:11:51 PM PDT 24
Finished Mar 12 01:11:52 PM PDT 24
Peak memory 205092 kb
Host smart-ee333500-bdad-48b7-aa42-2a5ce89d76ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808540087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2808540087
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.345662989
Short name T1564
Test name
Test status
Simulation time 14224682 ps
CPU time 0.72 seconds
Started Mar 12 03:08:28 PM PDT 24
Finished Mar 12 03:08:29 PM PDT 24
Peak memory 204672 kb
Host smart-d88f1f41-14b9-4132-9f41-93eef839567a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345662989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.345662989
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.1237545114
Short name T1317
Test name
Test status
Simulation time 1288204552 ps
CPU time 3.04 seconds
Started Mar 12 03:08:29 PM PDT 24
Finished Mar 12 03:08:32 PM PDT 24
Peak memory 217336 kb
Host smart-d0a36063-6fd6-47cd-85fd-2dcfad387a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237545114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1237545114
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2383657019
Short name T626
Test name
Test status
Simulation time 95305437 ps
CPU time 2.57 seconds
Started Mar 12 01:11:48 PM PDT 24
Finished Mar 12 01:11:50 PM PDT 24
Peak memory 223796 kb
Host smart-0492d477-4c9a-4dac-81ee-a263bd36e27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383657019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2383657019
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.280720870
Short name T664
Test name
Test status
Simulation time 66089889 ps
CPU time 0.78 seconds
Started Mar 12 01:11:48 PM PDT 24
Finished Mar 12 01:11:49 PM PDT 24
Peak memory 206228 kb
Host smart-d285568a-df7c-4e6e-97fc-735a48fb9638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280720870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.280720870
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3672917245
Short name T483
Test name
Test status
Simulation time 34709878 ps
CPU time 0.79 seconds
Started Mar 12 03:08:17 PM PDT 24
Finished Mar 12 03:08:19 PM PDT 24
Peak memory 206256 kb
Host smart-243b8d5c-da98-42ab-bc15-bdeaa09ce5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672917245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3672917245
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1514659325
Short name T1820
Test name
Test status
Simulation time 153544405120 ps
CPU time 193.8 seconds
Started Mar 12 03:08:27 PM PDT 24
Finished Mar 12 03:11:41 PM PDT 24
Peak memory 254828 kb
Host smart-a5b09152-b940-4154-b789-0ea217205ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514659325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1514659325
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3632328547
Short name T4
Test name
Test status
Simulation time 9884038704 ps
CPU time 25.51 seconds
Started Mar 12 01:11:53 PM PDT 24
Finished Mar 12 01:12:19 PM PDT 24
Peak memory 238960 kb
Host smart-a5e7dd69-4e3c-440e-a57c-82f08e6d5851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632328547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3632328547
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1615147160
Short name T85
Test name
Test status
Simulation time 16756900943 ps
CPU time 61.91 seconds
Started Mar 12 01:11:49 PM PDT 24
Finished Mar 12 01:12:51 PM PDT 24
Peak memory 253832 kb
Host smart-5e7c6687-09c2-4ec5-b1f6-228c7da69ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615147160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1615147160
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3598165677
Short name T1207
Test name
Test status
Simulation time 5647581280 ps
CPU time 44.05 seconds
Started Mar 12 03:08:26 PM PDT 24
Finished Mar 12 03:09:11 PM PDT 24
Peak memory 238880 kb
Host smart-25edc329-1c97-4ee4-b80f-345a216128e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598165677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3598165677
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1119026319
Short name T1190
Test name
Test status
Simulation time 196748452320 ps
CPU time 330.65 seconds
Started Mar 12 03:08:28 PM PDT 24
Finished Mar 12 03:13:59 PM PDT 24
Peak memory 265304 kb
Host smart-869603d8-cd12-4994-ae94-1f9908c55560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119026319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1119026319
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1348605461
Short name T301
Test name
Test status
Simulation time 18248025681 ps
CPU time 91.56 seconds
Started Mar 12 01:12:06 PM PDT 24
Finished Mar 12 01:13:38 PM PDT 24
Peak memory 266524 kb
Host smart-81ce9198-6fd4-4438-8308-33fa4b5bba6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348605461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1348605461
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2023478987
Short name T1769
Test name
Test status
Simulation time 1053592442 ps
CPU time 20.79 seconds
Started Mar 12 03:08:25 PM PDT 24
Finished Mar 12 03:08:48 PM PDT 24
Peak memory 232420 kb
Host smart-0017afe1-5c4e-489a-82b3-51ad693c38f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023478987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2023478987
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2488587035
Short name T641
Test name
Test status
Simulation time 7496816568 ps
CPU time 21.72 seconds
Started Mar 12 01:11:43 PM PDT 24
Finished Mar 12 01:12:05 PM PDT 24
Peak memory 233948 kb
Host smart-9a12b1d1-3d37-4fa9-9684-2c7c1126cd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488587035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2488587035
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.4032569085
Short name T722
Test name
Test status
Simulation time 3797222664 ps
CPU time 7.19 seconds
Started Mar 12 03:08:27 PM PDT 24
Finished Mar 12 03:08:34 PM PDT 24
Peak memory 216928 kb
Host smart-08eccb88-98a3-411b-a3d6-6777dccf448e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032569085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.4032569085
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_intercept.4188277525
Short name T1859
Test name
Test status
Simulation time 166304811 ps
CPU time 2.84 seconds
Started Mar 12 01:11:44 PM PDT 24
Finished Mar 12 01:11:47 PM PDT 24
Peak memory 224160 kb
Host smart-bdcf5dd4-fd12-405d-9a25-0b0607f81411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188277525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.4188277525
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2508285659
Short name T251
Test name
Test status
Simulation time 14999808575 ps
CPU time 12.97 seconds
Started Mar 12 01:11:48 PM PDT 24
Finished Mar 12 01:12:01 PM PDT 24
Peak memory 232792 kb
Host smart-20ec4150-4309-48f5-8ab4-762f04b18832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508285659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2508285659
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3507722736
Short name T1094
Test name
Test status
Simulation time 4566935439 ps
CPU time 17.45 seconds
Started Mar 12 03:08:29 PM PDT 24
Finished Mar 12 03:08:46 PM PDT 24
Peak memory 248832 kb
Host smart-57844337-032e-4185-836d-88d6fbc5f34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507722736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3507722736
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3231798549
Short name T488
Test name
Test status
Simulation time 2246116550 ps
CPU time 9.74 seconds
Started Mar 12 03:08:28 PM PDT 24
Finished Mar 12 03:08:38 PM PDT 24
Peak memory 224240 kb
Host smart-e0a51dfb-e390-477c-9f87-49fad2511231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231798549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3231798549
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3717783103
Short name T307
Test name
Test status
Simulation time 28778013029 ps
CPU time 23.99 seconds
Started Mar 12 01:11:42 PM PDT 24
Finished Mar 12 01:12:06 PM PDT 24
Peak memory 238380 kb
Host smart-3acbf88b-9c93-490c-9d4f-5916db8e9164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717783103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3717783103
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3395703046
Short name T373
Test name
Test status
Simulation time 4597258457 ps
CPU time 6.74 seconds
Started Mar 12 03:08:15 PM PDT 24
Finished Mar 12 03:08:22 PM PDT 24
Peak memory 220252 kb
Host smart-92f0b94c-acea-4772-8605-69c5984febca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395703046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3395703046
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.70615879
Short name T603
Test name
Test status
Simulation time 21251270233 ps
CPU time 34.76 seconds
Started Mar 12 01:11:48 PM PDT 24
Finished Mar 12 01:12:23 PM PDT 24
Peak memory 234520 kb
Host smart-7ed4884a-de45-42b0-91fb-a78780ebf97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70615879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.70615879
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3008111415
Short name T829
Test name
Test status
Simulation time 1108070808 ps
CPU time 4.17 seconds
Started Mar 12 01:11:45 PM PDT 24
Finished Mar 12 01:11:49 PM PDT 24
Peak memory 218168 kb
Host smart-08fad6b2-6249-493c-a863-40bbd0dd79bd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3008111415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3008111415
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.4179721678
Short name T741
Test name
Test status
Simulation time 129520304 ps
CPU time 3.18 seconds
Started Mar 12 03:08:26 PM PDT 24
Finished Mar 12 03:08:30 PM PDT 24
Peak memory 217020 kb
Host smart-fafce887-08d9-4096-9311-d0d92c7b1ee7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4179721678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.4179721678
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.2363481531
Short name T957
Test name
Test status
Simulation time 99621007950 ps
CPU time 265.5 seconds
Started Mar 12 01:11:52 PM PDT 24
Finished Mar 12 01:16:18 PM PDT 24
Peak memory 264156 kb
Host smart-29aebfb5-bb1e-4612-99cd-ae01c6eea6a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363481531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.2363481531
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.2656739875
Short name T628
Test name
Test status
Simulation time 6892462004 ps
CPU time 68.22 seconds
Started Mar 12 03:08:28 PM PDT 24
Finished Mar 12 03:09:36 PM PDT 24
Peak memory 236352 kb
Host smart-06e5dba3-12f1-4010-a67b-7fddf738dc2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656739875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.2656739875
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1414790973
Short name T1133
Test name
Test status
Simulation time 111686362560 ps
CPU time 42.13 seconds
Started Mar 12 03:08:16 PM PDT 24
Finished Mar 12 03:08:58 PM PDT 24
Peak memory 216136 kb
Host smart-5492012b-f53d-45ca-9cfd-cffbe99d91a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414790973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1414790973
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.604439717
Short name T1397
Test name
Test status
Simulation time 413146978 ps
CPU time 5.39 seconds
Started Mar 12 01:11:48 PM PDT 24
Finished Mar 12 01:11:53 PM PDT 24
Peak memory 215864 kb
Host smart-b72b2e18-e401-4246-9ee4-1bacfc68b19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604439717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.604439717
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2017560343
Short name T782
Test name
Test status
Simulation time 11055489168 ps
CPU time 9.81 seconds
Started Mar 12 03:08:16 PM PDT 24
Finished Mar 12 03:08:26 PM PDT 24
Peak memory 216140 kb
Host smart-69f7ed54-574b-4436-a41b-f0393e91ba57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017560343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2017560343
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.4104843369
Short name T16
Test name
Test status
Simulation time 24102798282 ps
CPU time 32.53 seconds
Started Mar 12 01:11:49 PM PDT 24
Finished Mar 12 01:12:21 PM PDT 24
Peak memory 216064 kb
Host smart-25db42e4-0856-4589-984b-e2cca3660074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104843369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.4104843369
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1347494188
Short name T453
Test name
Test status
Simulation time 94752723 ps
CPU time 2.09 seconds
Started Mar 12 03:08:20 PM PDT 24
Finished Mar 12 03:08:23 PM PDT 24
Peak memory 216056 kb
Host smart-e0d3479f-53d1-416c-a1ad-898fb2ac1491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347494188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1347494188
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.961582367
Short name T1542
Test name
Test status
Simulation time 79087810 ps
CPU time 1.05 seconds
Started Mar 12 01:11:44 PM PDT 24
Finished Mar 12 01:11:45 PM PDT 24
Peak memory 207244 kb
Host smart-97294cd3-8480-4122-ad4a-d1c7c7c72d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961582367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.961582367
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2866283259
Short name T472
Test name
Test status
Simulation time 179028918 ps
CPU time 1.03 seconds
Started Mar 12 03:08:14 PM PDT 24
Finished Mar 12 03:08:16 PM PDT 24
Peak memory 206260 kb
Host smart-2094d37a-3188-4312-8084-57e059d5b7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866283259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2866283259
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.756970005
Short name T903
Test name
Test status
Simulation time 52247709 ps
CPU time 0.71 seconds
Started Mar 12 01:11:43 PM PDT 24
Finished Mar 12 01:11:44 PM PDT 24
Peak memory 205260 kb
Host smart-fb2b7e6c-9e83-4c18-b6a8-444df64d2f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756970005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.756970005
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1597577397
Short name T679
Test name
Test status
Simulation time 297279536 ps
CPU time 2.59 seconds
Started Mar 12 01:11:46 PM PDT 24
Finished Mar 12 01:11:49 PM PDT 24
Peak memory 215972 kb
Host smart-baec864e-c571-46df-ae32-a6051a73d325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597577397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1597577397
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_upload.3551228735
Short name T647
Test name
Test status
Simulation time 1440463628 ps
CPU time 11.71 seconds
Started Mar 12 03:08:27 PM PDT 24
Finished Mar 12 03:08:39 PM PDT 24
Peak memory 233624 kb
Host smart-c97895c6-a604-4f93-8df7-286977e9062d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551228735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3551228735
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3670218254
Short name T1895
Test name
Test status
Simulation time 29656141 ps
CPU time 0.69 seconds
Started Mar 12 01:12:04 PM PDT 24
Finished Mar 12 01:12:05 PM PDT 24
Peak memory 204748 kb
Host smart-2de56e90-8997-4d19-a09d-d40fa754bb91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670218254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3670218254
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.4029414972
Short name T1780
Test name
Test status
Simulation time 20111293 ps
CPU time 0.74 seconds
Started Mar 12 03:08:28 PM PDT 24
Finished Mar 12 03:08:29 PM PDT 24
Peak memory 204220 kb
Host smart-37b76228-c08e-4fdd-97f3-1609cc81f0a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029414972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
4029414972
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.106526490
Short name T1267
Test name
Test status
Simulation time 1844996475 ps
CPU time 3.34 seconds
Started Mar 12 03:08:29 PM PDT 24
Finished Mar 12 03:08:33 PM PDT 24
Peak memory 219112 kb
Host smart-95c3a825-b5ae-443c-a137-b83c81dc82dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106526490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.106526490
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2519426827
Short name T873
Test name
Test status
Simulation time 65769180 ps
CPU time 2.34 seconds
Started Mar 12 01:11:50 PM PDT 24
Finished Mar 12 01:11:53 PM PDT 24
Peak memory 224084 kb
Host smart-e90dbbea-4456-46e5-b5e6-fcbf6b28a56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519426827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2519426827
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.154193106
Short name T387
Test name
Test status
Simulation time 102953088 ps
CPU time 0.74 seconds
Started Mar 12 01:11:52 PM PDT 24
Finished Mar 12 01:11:53 PM PDT 24
Peak memory 204852 kb
Host smart-ab7bb5bb-033c-4627-a613-7a2feadaec1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154193106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.154193106
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1834921755
Short name T1042
Test name
Test status
Simulation time 65254209 ps
CPU time 0.79 seconds
Started Mar 12 03:08:30 PM PDT 24
Finished Mar 12 03:08:30 PM PDT 24
Peak memory 205948 kb
Host smart-c9111697-23fa-4f10-a43d-8863ec73dc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834921755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1834921755
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.2490018836
Short name T992
Test name
Test status
Simulation time 74690497425 ps
CPU time 136.59 seconds
Started Mar 12 03:08:28 PM PDT 24
Finished Mar 12 03:10:45 PM PDT 24
Peak memory 255176 kb
Host smart-1e265cbe-93a9-4968-9c9f-c43abc6c34bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490018836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2490018836
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.426435201
Short name T1719
Test name
Test status
Simulation time 5618456805 ps
CPU time 37.64 seconds
Started Mar 12 01:11:56 PM PDT 24
Finished Mar 12 01:12:36 PM PDT 24
Peak memory 248900 kb
Host smart-04f48e4f-1bc6-4e88-a5b4-b513376e3d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426435201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.426435201
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1488081558
Short name T137
Test name
Test status
Simulation time 102555294284 ps
CPU time 291.2 seconds
Started Mar 12 01:12:14 PM PDT 24
Finished Mar 12 01:17:05 PM PDT 24
Peak memory 252208 kb
Host smart-cde81165-0dfe-434f-90a0-76396d0f1dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488081558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1488081558
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3673596222
Short name T1365
Test name
Test status
Simulation time 26717816703 ps
CPU time 175.27 seconds
Started Mar 12 03:08:31 PM PDT 24
Finished Mar 12 03:11:26 PM PDT 24
Peak memory 248992 kb
Host smart-553a3a10-70c2-496e-a8a8-416c50d5e101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673596222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3673596222
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2682030838
Short name T1471
Test name
Test status
Simulation time 5541661866 ps
CPU time 58.86 seconds
Started Mar 12 03:08:26 PM PDT 24
Finished Mar 12 03:09:26 PM PDT 24
Peak memory 250052 kb
Host smart-98b319c8-78f1-450f-bcd9-d7024540f033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682030838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2682030838
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2825639534
Short name T1579
Test name
Test status
Simulation time 8181749816 ps
CPU time 69.19 seconds
Started Mar 12 01:12:06 PM PDT 24
Finished Mar 12 01:13:15 PM PDT 24
Peak memory 254040 kb
Host smart-b07e0ecd-3d49-490c-9f11-b8b5b1e2ec3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825639534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2825639534
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3449176268
Short name T879
Test name
Test status
Simulation time 5233181854 ps
CPU time 10.28 seconds
Started Mar 12 01:11:49 PM PDT 24
Finished Mar 12 01:12:00 PM PDT 24
Peak memory 224140 kb
Host smart-2ca67d46-db84-4c0e-8bc1-db8f3a8f4ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449176268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3449176268
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.4203235032
Short name T1383
Test name
Test status
Simulation time 20139712802 ps
CPU time 34.92 seconds
Started Mar 12 03:08:30 PM PDT 24
Finished Mar 12 03:09:05 PM PDT 24
Peak memory 247056 kb
Host smart-f76f3fa7-821b-499e-9d2e-d1d63a202546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203235032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.4203235032
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1258864350
Short name T934
Test name
Test status
Simulation time 3106287308 ps
CPU time 6.01 seconds
Started Mar 12 01:11:49 PM PDT 24
Finished Mar 12 01:11:56 PM PDT 24
Peak memory 224196 kb
Host smart-e30c0f66-2e74-4b17-8ea7-21aa3dc0ef96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258864350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1258864350
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_intercept.402011528
Short name T1020
Test name
Test status
Simulation time 149660477 ps
CPU time 3.18 seconds
Started Mar 12 03:08:26 PM PDT 24
Finished Mar 12 03:08:30 PM PDT 24
Peak memory 232496 kb
Host smart-df27c5e5-9ddc-4180-8d96-48d45fc7c9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402011528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.402011528
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.935424151
Short name T498
Test name
Test status
Simulation time 478309430 ps
CPU time 7.66 seconds
Started Mar 12 01:12:06 PM PDT 24
Finished Mar 12 01:12:14 PM PDT 24
Peak memory 239264 kb
Host smart-bb9219d0-1eb7-4e96-95db-894de3d06403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935424151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.935424151
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.96930002
Short name T1140
Test name
Test status
Simulation time 24438003798 ps
CPU time 26.38 seconds
Started Mar 12 03:08:27 PM PDT 24
Finished Mar 12 03:08:53 PM PDT 24
Peak memory 248476 kb
Host smart-be051b20-5578-4ab0-bd93-75e749f08d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96930002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.96930002
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2599528621
Short name T1342
Test name
Test status
Simulation time 18580659503 ps
CPU time 4.82 seconds
Started Mar 12 01:11:50 PM PDT 24
Finished Mar 12 01:11:55 PM PDT 24
Peak memory 224224 kb
Host smart-b0a19dd2-f94d-4639-8b4f-58d6e812cd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599528621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2599528621
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.855957344
Short name T646
Test name
Test status
Simulation time 2815420233 ps
CPU time 10.85 seconds
Started Mar 12 03:08:29 PM PDT 24
Finished Mar 12 03:08:40 PM PDT 24
Peak memory 234440 kb
Host smart-6f9f83a0-372c-4cbc-a16f-56906a0db385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855957344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.855957344
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3886945054
Short name T1743
Test name
Test status
Simulation time 5382994205 ps
CPU time 17.89 seconds
Started Mar 12 03:08:27 PM PDT 24
Finished Mar 12 03:08:45 PM PDT 24
Peak memory 239756 kb
Host smart-96a9a746-5113-453a-bab9-af19f1785ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886945054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3886945054
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.617904736
Short name T1176
Test name
Test status
Simulation time 23471731863 ps
CPU time 14.18 seconds
Started Mar 12 01:11:50 PM PDT 24
Finished Mar 12 01:12:05 PM PDT 24
Peak memory 233316 kb
Host smart-defa6c7c-5a8b-4164-b537-6532d654c6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617904736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.617904736
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3561067163
Short name T513
Test name
Test status
Simulation time 294226676 ps
CPU time 4.25 seconds
Started Mar 12 01:11:49 PM PDT 24
Finished Mar 12 01:11:54 PM PDT 24
Peak memory 222360 kb
Host smart-83f934e4-bad0-4266-9ce2-ca45fec730f3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3561067163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3561067163
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.736873718
Short name T544
Test name
Test status
Simulation time 937052113 ps
CPU time 3.91 seconds
Started Mar 12 03:08:29 PM PDT 24
Finished Mar 12 03:08:33 PM PDT 24
Peak memory 222328 kb
Host smart-bb243e62-7ae3-44be-a165-c0013fbfedbf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=736873718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.736873718
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3030406327
Short name T213
Test name
Test status
Simulation time 125297439595 ps
CPU time 141.67 seconds
Started Mar 12 01:12:06 PM PDT 24
Finished Mar 12 01:14:28 PM PDT 24
Peak memory 250140 kb
Host smart-2e8575ff-1efc-4adb-9194-871d300b1c4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030406327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3030406327
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3668863284
Short name T1296
Test name
Test status
Simulation time 153826920348 ps
CPU time 397.18 seconds
Started Mar 12 03:08:29 PM PDT 24
Finished Mar 12 03:15:06 PM PDT 24
Peak memory 265268 kb
Host smart-684ed1a0-ca92-4bf9-a653-33b94df9eb8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668863284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3668863284
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1878820323
Short name T820
Test name
Test status
Simulation time 9870885288 ps
CPU time 21.23 seconds
Started Mar 12 03:08:30 PM PDT 24
Finished Mar 12 03:08:52 PM PDT 24
Peak memory 216192 kb
Host smart-1375b779-8b9e-45a6-bacc-f2324bc74fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878820323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1878820323
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3197427430
Short name T991
Test name
Test status
Simulation time 7949977152 ps
CPU time 41.17 seconds
Started Mar 12 01:11:51 PM PDT 24
Finished Mar 12 01:12:33 PM PDT 24
Peak memory 216092 kb
Host smart-03e80087-6c1d-418c-ba4e-f2905ee71086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197427430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3197427430
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1107425403
Short name T630
Test name
Test status
Simulation time 28728497289 ps
CPU time 14.45 seconds
Started Mar 12 01:12:03 PM PDT 24
Finished Mar 12 01:12:18 PM PDT 24
Peak memory 216068 kb
Host smart-c6266ee1-7872-42db-a990-51a87e23f417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107425403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1107425403
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3936250234
Short name T1287
Test name
Test status
Simulation time 107354609773 ps
CPU time 38.72 seconds
Started Mar 12 03:08:28 PM PDT 24
Finished Mar 12 03:09:07 PM PDT 24
Peak memory 216152 kb
Host smart-e2bd3fc8-ecb0-4437-beb2-9ed5060406f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936250234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3936250234
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3116795510
Short name T1104
Test name
Test status
Simulation time 85549850 ps
CPU time 1.93 seconds
Started Mar 12 01:12:06 PM PDT 24
Finished Mar 12 01:12:09 PM PDT 24
Peak memory 215984 kb
Host smart-4b9abffe-4b98-4d12-ae58-c38f95c8437d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116795510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3116795510
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3558959362
Short name T363
Test name
Test status
Simulation time 84042987 ps
CPU time 1.31 seconds
Started Mar 12 03:08:30 PM PDT 24
Finished Mar 12 03:08:32 PM PDT 24
Peak memory 207708 kb
Host smart-f19c9dfa-b788-4344-b77e-4562b31c1eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558959362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3558959362
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3658861982
Short name T1032
Test name
Test status
Simulation time 306961765 ps
CPU time 0.94 seconds
Started Mar 12 01:12:07 PM PDT 24
Finished Mar 12 01:12:08 PM PDT 24
Peak memory 204868 kb
Host smart-4a885499-c337-4db1-8599-cb5fe047d3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658861982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3658861982
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3763695857
Short name T751
Test name
Test status
Simulation time 27043691 ps
CPU time 0.74 seconds
Started Mar 12 03:08:26 PM PDT 24
Finished Mar 12 03:08:28 PM PDT 24
Peak memory 205236 kb
Host smart-f82da7a2-05bc-450b-9c89-8e4fc39e8bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763695857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3763695857
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2469478492
Short name T993
Test name
Test status
Simulation time 166090886 ps
CPU time 2.37 seconds
Started Mar 12 03:08:26 PM PDT 24
Finished Mar 12 03:08:29 PM PDT 24
Peak memory 216608 kb
Host smart-0c6fb5bd-8735-4f4a-8309-7bb67215267b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469478492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2469478492
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_upload.3460242480
Short name T1620
Test name
Test status
Simulation time 8927484583 ps
CPU time 8.15 seconds
Started Mar 12 01:11:53 PM PDT 24
Finished Mar 12 01:12:02 PM PDT 24
Peak memory 232480 kb
Host smart-6c644fb2-aba3-425e-a460-3c3f680164d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460242480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3460242480
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1421857552
Short name T1790
Test name
Test status
Simulation time 41917252 ps
CPU time 0.7 seconds
Started Mar 12 03:08:36 PM PDT 24
Finished Mar 12 03:08:37 PM PDT 24
Peak memory 204216 kb
Host smart-e51280b3-f7d0-4c82-8547-a0032e955574
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421857552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1421857552
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1989440952
Short name T929
Test name
Test status
Simulation time 202785673 ps
CPU time 0.69 seconds
Started Mar 12 01:12:05 PM PDT 24
Finished Mar 12 01:12:05 PM PDT 24
Peak memory 204168 kb
Host smart-57821cd4-02bf-449b-a5b9-b1419ca14986
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989440952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1989440952
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.442076893
Short name T386
Test name
Test status
Simulation time 519944234 ps
CPU time 2.45 seconds
Started Mar 12 03:08:37 PM PDT 24
Finished Mar 12 03:08:41 PM PDT 24
Peak memory 233588 kb
Host smart-5d67a4d9-ed28-4ff0-878b-accf5d588c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442076893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.442076893
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.790283409
Short name T247
Test name
Test status
Simulation time 4562659291 ps
CPU time 15.07 seconds
Started Mar 12 01:11:52 PM PDT 24
Finished Mar 12 01:12:08 PM PDT 24
Peak memory 232856 kb
Host smart-1693084d-e975-4a45-bcbf-9b6a29f09abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790283409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.790283409
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3891698554
Short name T1629
Test name
Test status
Simulation time 15512296 ps
CPU time 0.71 seconds
Started Mar 12 01:11:52 PM PDT 24
Finished Mar 12 01:11:53 PM PDT 24
Peak memory 205464 kb
Host smart-b31e2e96-df5f-4650-b735-34aecf0f4336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891698554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3891698554
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.576684289
Short name T337
Test name
Test status
Simulation time 40928984 ps
CPU time 0.71 seconds
Started Mar 12 03:08:29 PM PDT 24
Finished Mar 12 03:08:30 PM PDT 24
Peak memory 205252 kb
Host smart-275cf067-524f-40bf-9164-705b25fb4557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576684289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.576684289
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1736218195
Short name T204
Test name
Test status
Simulation time 4548567149 ps
CPU time 47.47 seconds
Started Mar 12 01:11:51 PM PDT 24
Finished Mar 12 01:12:38 PM PDT 24
Peak memory 248840 kb
Host smart-8bc3a8a6-9ad8-44b1-81b3-3e8adf31bde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736218195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1736218195
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1811968385
Short name T886
Test name
Test status
Simulation time 73963022850 ps
CPU time 174.89 seconds
Started Mar 12 03:08:37 PM PDT 24
Finished Mar 12 03:11:32 PM PDT 24
Peak memory 249296 kb
Host smart-fe7ee304-d702-4fc4-8d1f-2f2e92609287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811968385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1811968385
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2252994338
Short name T1821
Test name
Test status
Simulation time 7024778782 ps
CPU time 115.11 seconds
Started Mar 12 03:08:37 PM PDT 24
Finished Mar 12 03:10:32 PM PDT 24
Peak memory 265384 kb
Host smart-9523f0a3-61ae-46cb-bce0-18888f0d3093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252994338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2252994338
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.8797692
Short name T593
Test name
Test status
Simulation time 5413488971 ps
CPU time 44.8 seconds
Started Mar 12 01:12:05 PM PDT 24
Finished Mar 12 01:12:50 PM PDT 24
Peak memory 236200 kb
Host smart-c9aa8ee0-09f2-49e7-9804-d8ba083bf875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8797692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.8797692
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1949951101
Short name T505
Test name
Test status
Simulation time 36803132868 ps
CPU time 25.07 seconds
Started Mar 12 03:08:47 PM PDT 24
Finished Mar 12 03:09:12 PM PDT 24
Peak memory 223316 kb
Host smart-660ca5ee-e0ff-41e5-b84d-98e11710be25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949951101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1949951101
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3152933545
Short name T84
Test name
Test status
Simulation time 5663474710 ps
CPU time 68.77 seconds
Started Mar 12 01:12:06 PM PDT 24
Finished Mar 12 01:13:15 PM PDT 24
Peak memory 252164 kb
Host smart-96cf24de-d659-46f3-b3b5-dad04374f1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152933545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3152933545
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.225894507
Short name T1568
Test name
Test status
Simulation time 21276722192 ps
CPU time 21.54 seconds
Started Mar 12 03:08:47 PM PDT 24
Finished Mar 12 03:09:08 PM PDT 24
Peak memory 239760 kb
Host smart-eac36408-0df6-498a-8200-10ae311d7f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225894507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.225894507
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2413455161
Short name T311
Test name
Test status
Simulation time 1157583193 ps
CPU time 12.18 seconds
Started Mar 12 01:12:07 PM PDT 24
Finished Mar 12 01:12:20 PM PDT 24
Peak memory 240060 kb
Host smart-fb66ee50-4b39-48fd-a251-32213e3a2ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413455161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2413455161
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2553358541
Short name T1239
Test name
Test status
Simulation time 421830182 ps
CPU time 3.24 seconds
Started Mar 12 03:08:38 PM PDT 24
Finished Mar 12 03:08:42 PM PDT 24
Peak memory 233420 kb
Host smart-4ebdb0fe-ede0-495b-b0b6-a1fa7cb46d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553358541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2553358541
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_intercept.537025340
Short name T1286
Test name
Test status
Simulation time 2815333761 ps
CPU time 9.23 seconds
Started Mar 12 01:11:57 PM PDT 24
Finished Mar 12 01:12:07 PM PDT 24
Peak memory 218752 kb
Host smart-710a871c-4458-41bb-905f-0ff12c8ea762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537025340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.537025340
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2366935039
Short name T877
Test name
Test status
Simulation time 13882131453 ps
CPU time 35.34 seconds
Started Mar 12 01:11:52 PM PDT 24
Finished Mar 12 01:12:28 PM PDT 24
Peak memory 229880 kb
Host smart-6f4b393a-fe85-401e-94e3-fa452d22f260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366935039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2366935039
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2673684743
Short name T1654
Test name
Test status
Simulation time 71743006177 ps
CPU time 54.46 seconds
Started Mar 12 03:08:39 PM PDT 24
Finished Mar 12 03:09:33 PM PDT 24
Peak memory 232052 kb
Host smart-3cde48a0-f996-403e-9a3a-84c3815ae533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673684743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2673684743
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.129896723
Short name T1538
Test name
Test status
Simulation time 814458776 ps
CPU time 11.49 seconds
Started Mar 12 03:08:39 PM PDT 24
Finished Mar 12 03:08:51 PM PDT 24
Peak memory 231004 kb
Host smart-0fe5d849-7ee4-4d09-867e-52d3df093e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129896723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.129896723
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2420906661
Short name T1304
Test name
Test status
Simulation time 1397351259 ps
CPU time 4.76 seconds
Started Mar 12 01:12:15 PM PDT 24
Finished Mar 12 01:12:20 PM PDT 24
Peak memory 218600 kb
Host smart-f1f8d034-33fb-455e-a69f-22971d7b901c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420906661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2420906661
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1343483804
Short name T1345
Test name
Test status
Simulation time 676626237 ps
CPU time 3.94 seconds
Started Mar 12 03:08:35 PM PDT 24
Finished Mar 12 03:08:40 PM PDT 24
Peak memory 232612 kb
Host smart-816c5581-8c23-4afd-86e6-0913f8bab736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343483804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1343483804
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2104057086
Short name T236
Test name
Test status
Simulation time 89596581883 ps
CPU time 55.44 seconds
Started Mar 12 01:11:52 PM PDT 24
Finished Mar 12 01:12:48 PM PDT 24
Peak memory 240580 kb
Host smart-ee783ec2-d49a-4cad-94ed-096dcd363dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104057086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2104057086
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2235937536
Short name T331
Test name
Test status
Simulation time 3922289036 ps
CPU time 5.26 seconds
Started Mar 12 01:11:53 PM PDT 24
Finished Mar 12 01:11:58 PM PDT 24
Peak memory 219552 kb
Host smart-8064a730-6999-4f65-b1f7-6d2a7807005d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2235937536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2235937536
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.622853456
Short name T1617
Test name
Test status
Simulation time 4032794405 ps
CPU time 4.74 seconds
Started Mar 12 03:08:47 PM PDT 24
Finished Mar 12 03:08:51 PM PDT 24
Peak memory 219740 kb
Host smart-56eaaff5-2b90-47a9-b29c-f4af7efe5d51
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=622853456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.622853456
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1255945828
Short name T1300
Test name
Test status
Simulation time 186825380972 ps
CPU time 177.96 seconds
Started Mar 12 01:11:51 PM PDT 24
Finished Mar 12 01:14:49 PM PDT 24
Peak memory 265048 kb
Host smart-fb3df4b5-064d-48e8-afff-630ad4334379
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255945828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1255945828
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.3797047158
Short name T55
Test name
Test status
Simulation time 20489083853 ps
CPU time 279.96 seconds
Started Mar 12 03:08:36 PM PDT 24
Finished Mar 12 03:13:16 PM PDT 24
Peak memory 265380 kb
Host smart-deaa4e22-505b-4250-be8a-e6a755c8cd31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797047158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.3797047158
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1006922258
Short name T1724
Test name
Test status
Simulation time 4310128563 ps
CPU time 22.79 seconds
Started Mar 12 03:08:29 PM PDT 24
Finished Mar 12 03:08:52 PM PDT 24
Peak memory 216168 kb
Host smart-c5fbb2f8-a245-486d-a518-e8186f6f7831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006922258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1006922258
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3197311299
Short name T462
Test name
Test status
Simulation time 9588516388 ps
CPU time 27.36 seconds
Started Mar 12 03:08:29 PM PDT 24
Finished Mar 12 03:08:57 PM PDT 24
Peak memory 217264 kb
Host smart-789437be-62d2-4963-98d7-9c86fd916d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197311299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3197311299
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3462498407
Short name T827
Test name
Test status
Simulation time 9856004955 ps
CPU time 26.79 seconds
Started Mar 12 01:11:51 PM PDT 24
Finished Mar 12 01:12:18 PM PDT 24
Peak memory 216172 kb
Host smart-cdf3a77a-d523-43ad-ae07-4aa76ece4852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462498407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3462498407
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2189583325
Short name T375
Test name
Test status
Simulation time 46016485 ps
CPU time 1.33 seconds
Started Mar 12 01:11:50 PM PDT 24
Finished Mar 12 01:11:52 PM PDT 24
Peak memory 215892 kb
Host smart-d925f665-087e-423a-8d0e-cecc5031da40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189583325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2189583325
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3307093672
Short name T1453
Test name
Test status
Simulation time 83485416 ps
CPU time 1.25 seconds
Started Mar 12 03:08:37 PM PDT 24
Finished Mar 12 03:08:39 PM PDT 24
Peak memory 215936 kb
Host smart-41789ada-c048-4c1c-8aba-e34ca973fc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307093672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3307093672
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1171863231
Short name T601
Test name
Test status
Simulation time 97710722 ps
CPU time 0.83 seconds
Started Mar 12 01:11:49 PM PDT 24
Finished Mar 12 01:11:51 PM PDT 24
Peak memory 205212 kb
Host smart-ed88b931-c7d3-4876-b113-d11db5359458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171863231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1171863231
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3848142992
Short name T807
Test name
Test status
Simulation time 331111240 ps
CPU time 1.01 seconds
Started Mar 12 03:08:36 PM PDT 24
Finished Mar 12 03:08:37 PM PDT 24
Peak memory 206240 kb
Host smart-34127002-07a0-4240-b8c7-ccbf8f121bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848142992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3848142992
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.281219840
Short name T1678
Test name
Test status
Simulation time 4022318909 ps
CPU time 13.49 seconds
Started Mar 12 01:11:52 PM PDT 24
Finished Mar 12 01:12:06 PM PDT 24
Peak memory 229036 kb
Host smart-78737ad0-bce8-433f-b9d5-f7f72754c0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281219840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.281219840
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_upload.424083868
Short name T1162
Test name
Test status
Simulation time 1782202931 ps
CPU time 9.22 seconds
Started Mar 12 03:08:37 PM PDT 24
Finished Mar 12 03:08:46 PM PDT 24
Peak memory 227556 kb
Host smart-f1206ad4-6918-4315-9920-e5a7c5f88cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424083868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.424083868
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2321691220
Short name T1093
Test name
Test status
Simulation time 38106422 ps
CPU time 0.76 seconds
Started Mar 12 03:08:54 PM PDT 24
Finished Mar 12 03:08:58 PM PDT 24
Peak memory 204204 kb
Host smart-b69a869b-5871-47e2-9e87-1f70f9179716
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321691220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2321691220
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2600641740
Short name T383
Test name
Test status
Simulation time 21781931 ps
CPU time 0.7 seconds
Started Mar 12 01:12:02 PM PDT 24
Finished Mar 12 01:12:03 PM PDT 24
Peak memory 204180 kb
Host smart-c45edc32-18b4-489d-9ba3-acdf2d07a0e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600641740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2600641740
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.158889168
Short name T1615
Test name
Test status
Simulation time 120646738 ps
CPU time 2.55 seconds
Started Mar 12 01:12:00 PM PDT 24
Finished Mar 12 01:12:03 PM PDT 24
Peak memory 216432 kb
Host smart-71c6c35e-1f58-4693-87db-833a0f63e28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158889168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.158889168
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3377187391
Short name T920
Test name
Test status
Simulation time 1123831394 ps
CPU time 4.87 seconds
Started Mar 12 03:08:37 PM PDT 24
Finished Mar 12 03:08:42 PM PDT 24
Peak memory 233060 kb
Host smart-33b769e8-625d-4163-a505-f3ac3f20203f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377187391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3377187391
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3123544394
Short name T850
Test name
Test status
Simulation time 34706476 ps
CPU time 0.79 seconds
Started Mar 12 03:08:38 PM PDT 24
Finished Mar 12 03:08:40 PM PDT 24
Peak memory 205936 kb
Host smart-acfec6ed-374d-49b2-914f-6bbcf177fb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123544394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3123544394
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.523334000
Short name T1155
Test name
Test status
Simulation time 44636455 ps
CPU time 0.77 seconds
Started Mar 12 01:11:51 PM PDT 24
Finished Mar 12 01:11:52 PM PDT 24
Peak memory 206244 kb
Host smart-a5bbb34d-9b0d-4b45-9602-5b96fd28eddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523334000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.523334000
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.43844338
Short name T1655
Test name
Test status
Simulation time 22232559495 ps
CPU time 75.96 seconds
Started Mar 12 03:08:39 PM PDT 24
Finished Mar 12 03:09:56 PM PDT 24
Peak memory 256356 kb
Host smart-a008c89e-b872-451c-86db-e9c294e7f781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43844338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.43844338
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.804887653
Short name T253
Test name
Test status
Simulation time 16271457887 ps
CPU time 108.44 seconds
Started Mar 12 01:12:02 PM PDT 24
Finished Mar 12 01:13:52 PM PDT 24
Peak memory 247728 kb
Host smart-baa87fe5-dd4c-4540-9a39-4f303e73de64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804887653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.804887653
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2628098653
Short name T30
Test name
Test status
Simulation time 91767022562 ps
CPU time 660.69 seconds
Started Mar 12 01:12:01 PM PDT 24
Finished Mar 12 01:23:03 PM PDT 24
Peak memory 264640 kb
Host smart-611c908c-29bd-41d3-b950-1ceda6c538aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628098653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2628098653
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.4159072549
Short name T1766
Test name
Test status
Simulation time 36368612285 ps
CPU time 69.17 seconds
Started Mar 12 03:08:40 PM PDT 24
Finished Mar 12 03:09:49 PM PDT 24
Peak memory 248976 kb
Host smart-9ed52bd6-e888-4c24-9dd9-e42d894412d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159072549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.4159072549
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3143196850
Short name T376
Test name
Test status
Simulation time 34565990649 ps
CPU time 170.85 seconds
Started Mar 12 03:08:38 PM PDT 24
Finished Mar 12 03:11:30 PM PDT 24
Peak memory 252156 kb
Host smart-b231b8fa-997d-40ba-b26f-a20662609cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143196850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3143196850
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3744707560
Short name T484
Test name
Test status
Simulation time 57003968030 ps
CPU time 303.69 seconds
Started Mar 12 01:12:02 PM PDT 24
Finished Mar 12 01:17:06 PM PDT 24
Peak memory 257044 kb
Host smart-dedb285e-129d-456d-b688-dfbddfc99a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744707560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3744707560
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.4063215835
Short name T927
Test name
Test status
Simulation time 2136130470 ps
CPU time 22.1 seconds
Started Mar 12 01:12:04 PM PDT 24
Finished Mar 12 01:12:27 PM PDT 24
Peak memory 249844 kb
Host smart-dfc3a440-3ceb-426c-93bd-13a78824b63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063215835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.4063215835
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.775932858
Short name T884
Test name
Test status
Simulation time 29618430043 ps
CPU time 50.08 seconds
Started Mar 12 03:08:40 PM PDT 24
Finished Mar 12 03:09:30 PM PDT 24
Peak memory 232452 kb
Host smart-8cad1bab-b430-4cb7-bda4-f4b22b39c6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775932858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.775932858
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1179939121
Short name T1833
Test name
Test status
Simulation time 5759201521 ps
CPU time 5.22 seconds
Started Mar 12 01:11:51 PM PDT 24
Finished Mar 12 01:11:56 PM PDT 24
Peak memory 224248 kb
Host smart-c22d2b2b-d8c6-47e6-8759-90d8658b7ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179939121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1179939121
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2365529815
Short name T1265
Test name
Test status
Simulation time 6788681705 ps
CPU time 6.28 seconds
Started Mar 12 03:08:35 PM PDT 24
Finished Mar 12 03:08:41 PM PDT 24
Peak memory 219864 kb
Host smart-4316e889-f687-40b0-a433-9b25fe5036c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365529815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2365529815
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2228202560
Short name T1465
Test name
Test status
Simulation time 3761192963 ps
CPU time 13.28 seconds
Started Mar 12 03:08:35 PM PDT 24
Finished Mar 12 03:08:50 PM PDT 24
Peak memory 232452 kb
Host smart-e6cda402-900b-47e0-a74d-ae1d69328e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228202560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2228202560
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3648500121
Short name T1380
Test name
Test status
Simulation time 9123788851 ps
CPU time 19.14 seconds
Started Mar 12 01:12:01 PM PDT 24
Finished Mar 12 01:12:21 PM PDT 24
Peak memory 226452 kb
Host smart-b13a9356-24a4-4d15-8bfe-36198e9a19eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648500121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3648500121
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1875223505
Short name T1233
Test name
Test status
Simulation time 73144195 ps
CPU time 2.23 seconds
Started Mar 12 01:11:53 PM PDT 24
Finished Mar 12 01:11:55 PM PDT 24
Peak memory 216328 kb
Host smart-c5df189d-2c21-444a-b080-4e36a9ab326c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875223505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1875223505
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3996214571
Short name T40
Test name
Test status
Simulation time 2415793250 ps
CPU time 8.51 seconds
Started Mar 12 03:08:36 PM PDT 24
Finished Mar 12 03:08:45 PM PDT 24
Peak memory 233116 kb
Host smart-ecf49920-ab91-4e04-9b96-9c120e454509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996214571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3996214571
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1486165519
Short name T973
Test name
Test status
Simulation time 14011645873 ps
CPU time 35.01 seconds
Started Mar 12 03:08:35 PM PDT 24
Finished Mar 12 03:09:11 PM PDT 24
Peak memory 234264 kb
Host smart-ef321b12-a942-4dfc-980c-8985a8767b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486165519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1486165519
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3553393088
Short name T515
Test name
Test status
Simulation time 852831521 ps
CPU time 7.99 seconds
Started Mar 12 01:12:06 PM PDT 24
Finished Mar 12 01:12:15 PM PDT 24
Peak memory 232268 kb
Host smart-141b01db-c28c-424e-be33-34c56d18694f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553393088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3553393088
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1119014830
Short name T1842
Test name
Test status
Simulation time 349773840 ps
CPU time 4.54 seconds
Started Mar 12 01:12:01 PM PDT 24
Finished Mar 12 01:12:06 PM PDT 24
Peak memory 222456 kb
Host smart-a0b45ab6-b50c-42a3-a984-9a077574e0fa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1119014830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1119014830
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.687605179
Short name T863
Test name
Test status
Simulation time 1722729865 ps
CPU time 3.6 seconds
Started Mar 12 03:08:37 PM PDT 24
Finished Mar 12 03:08:41 PM PDT 24
Peak memory 216164 kb
Host smart-fcdf6cb4-ca77-4f84-b359-281b93a6ccef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=687605179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.687605179
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.135900840
Short name T1105
Test name
Test status
Simulation time 2843054630 ps
CPU time 18.94 seconds
Started Mar 12 03:08:53 PM PDT 24
Finished Mar 12 03:09:13 PM PDT 24
Peak memory 234196 kb
Host smart-e70adcdf-8f72-4bf4-880d-1671a1001cf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135900840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.135900840
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.752804380
Short name T63
Test name
Test status
Simulation time 184388304 ps
CPU time 1.11 seconds
Started Mar 12 01:12:00 PM PDT 24
Finished Mar 12 01:12:02 PM PDT 24
Peak memory 206508 kb
Host smart-e0150280-dfac-4bcc-a47b-5af42b763238
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752804380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.752804380
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2001128532
Short name T552
Test name
Test status
Simulation time 7590340974 ps
CPU time 34.55 seconds
Started Mar 12 01:12:06 PM PDT 24
Finished Mar 12 01:12:41 PM PDT 24
Peak memory 216048 kb
Host smart-455b2310-c972-4f7d-a575-f262a87b5cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001128532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2001128532
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2964861848
Short name T428
Test name
Test status
Simulation time 1021025648 ps
CPU time 7.62 seconds
Started Mar 12 03:08:39 PM PDT 24
Finished Mar 12 03:08:48 PM PDT 24
Peak memory 216048 kb
Host smart-52fae1af-16ee-4fd8-95a8-b49dbbc4c010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964861848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2964861848
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1061328276
Short name T355
Test name
Test status
Simulation time 2968260808 ps
CPU time 7.6 seconds
Started Mar 12 03:08:35 PM PDT 24
Finished Mar 12 03:08:44 PM PDT 24
Peak memory 216084 kb
Host smart-87cbab12-d46b-410d-a34d-5364ab961dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061328276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1061328276
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3004381272
Short name T1819
Test name
Test status
Simulation time 4497826079 ps
CPU time 12.44 seconds
Started Mar 12 01:12:09 PM PDT 24
Finished Mar 12 01:12:22 PM PDT 24
Peak memory 216048 kb
Host smart-39cddc70-e0b9-4312-8254-5035b2aa4dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004381272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3004381272
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1184626275
Short name T1068
Test name
Test status
Simulation time 26557823 ps
CPU time 1 seconds
Started Mar 12 03:08:38 PM PDT 24
Finished Mar 12 03:08:40 PM PDT 24
Peak memory 206692 kb
Host smart-53adefe2-4dc2-4fc3-9526-d7dca4873a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184626275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1184626275
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.374664832
Short name T1725
Test name
Test status
Simulation time 80810377 ps
CPU time 1.06 seconds
Started Mar 12 01:12:05 PM PDT 24
Finished Mar 12 01:12:06 PM PDT 24
Peak memory 206288 kb
Host smart-5a280ca9-0820-4c23-b328-7e2d9131bc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374664832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.374664832
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3824684280
Short name T356
Test name
Test status
Simulation time 178326035 ps
CPU time 0.9 seconds
Started Mar 12 01:12:15 PM PDT 24
Finished Mar 12 01:12:17 PM PDT 24
Peak memory 205132 kb
Host smart-01a47a30-c0d5-4d85-ac2c-d9b647e7c355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824684280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3824684280
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3872849268
Short name T1060
Test name
Test status
Simulation time 94300394 ps
CPU time 0.9 seconds
Started Mar 12 03:08:39 PM PDT 24
Finished Mar 12 03:08:41 PM PDT 24
Peak memory 205248 kb
Host smart-5845d464-f206-4d01-97ac-3f61746d2602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872849268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3872849268
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.19510589
Short name T657
Test name
Test status
Simulation time 8354048135 ps
CPU time 25.59 seconds
Started Mar 12 01:12:03 PM PDT 24
Finished Mar 12 01:12:29 PM PDT 24
Peak memory 229828 kb
Host smart-75605f9a-3e7b-40fd-b1ac-e29064959d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19510589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.19510589
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_upload.859520059
Short name T1392
Test name
Test status
Simulation time 264138558 ps
CPU time 6.4 seconds
Started Mar 12 03:08:39 PM PDT 24
Finished Mar 12 03:08:46 PM PDT 24
Peak memory 233352 kb
Host smart-e33ac558-402e-4d25-a2a7-1a59d677279c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859520059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.859520059
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1289252394
Short name T1881
Test name
Test status
Simulation time 16380358 ps
CPU time 0.74 seconds
Started Mar 12 03:08:55 PM PDT 24
Finished Mar 12 03:08:58 PM PDT 24
Peak memory 205140 kb
Host smart-ba7bf32b-23aa-45f3-a8d6-8da428122fb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289252394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1289252394
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2976185922
Short name T1169
Test name
Test status
Simulation time 23005989 ps
CPU time 0.73 seconds
Started Mar 12 01:12:04 PM PDT 24
Finished Mar 12 01:12:05 PM PDT 24
Peak memory 204736 kb
Host smart-06eeeb87-660e-42ce-a658-012ded7802e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976185922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2976185922
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1609495965
Short name T1066
Test name
Test status
Simulation time 127527113 ps
CPU time 2.35 seconds
Started Mar 12 01:12:05 PM PDT 24
Finished Mar 12 01:12:08 PM PDT 24
Peak memory 224128 kb
Host smart-8f4ab768-0403-44f5-b263-4d84b21397b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609495965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1609495965
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3728094530
Short name T1336
Test name
Test status
Simulation time 1869982450 ps
CPU time 3.13 seconds
Started Mar 12 03:08:52 PM PDT 24
Finished Mar 12 03:08:58 PM PDT 24
Peak memory 233068 kb
Host smart-d80cdec4-9dca-4833-9559-12f281fad64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728094530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3728094530
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2436112885
Short name T871
Test name
Test status
Simulation time 36253379 ps
CPU time 0.88 seconds
Started Mar 12 01:12:01 PM PDT 24
Finished Mar 12 01:12:03 PM PDT 24
Peak memory 205932 kb
Host smart-506ddd7d-7b5a-4294-8f17-316a9214028d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436112885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2436112885
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.662206865
Short name T1587
Test name
Test status
Simulation time 77179548 ps
CPU time 0.78 seconds
Started Mar 12 03:08:53 PM PDT 24
Finished Mar 12 03:08:57 PM PDT 24
Peak memory 205896 kb
Host smart-74d2aa10-9a5a-4eda-b82a-1ef41bd3d2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662206865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.662206865
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3953225716
Short name T1222
Test name
Test status
Simulation time 71310786580 ps
CPU time 48.12 seconds
Started Mar 12 01:12:00 PM PDT 24
Finished Mar 12 01:12:49 PM PDT 24
Peak memory 249864 kb
Host smart-2ba8ac2c-aa6a-46f2-a8f2-b2674ec900d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953225716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3953225716
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.4107671090
Short name T1040
Test name
Test status
Simulation time 16764605242 ps
CPU time 103.59 seconds
Started Mar 12 03:08:53 PM PDT 24
Finished Mar 12 03:10:38 PM PDT 24
Peak memory 264924 kb
Host smart-ce33b7c4-4774-4d11-89eb-3d2611093f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107671090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.4107671090
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1092297529
Short name T282
Test name
Test status
Simulation time 38663668345 ps
CPU time 144.64 seconds
Started Mar 12 03:08:55 PM PDT 24
Finished Mar 12 03:11:22 PM PDT 24
Peak memory 266920 kb
Host smart-38ef0c89-dcd0-4554-80cc-32541d747a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092297529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1092297529
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3596847612
Short name T20
Test name
Test status
Simulation time 17195966295 ps
CPU time 30.34 seconds
Started Mar 12 01:12:04 PM PDT 24
Finished Mar 12 01:12:34 PM PDT 24
Peak memory 234604 kb
Host smart-da5406b5-3eda-4a4e-b3ba-82a5e6e26d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596847612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3596847612
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1187210226
Short name T189
Test name
Test status
Simulation time 51309943748 ps
CPU time 212.12 seconds
Started Mar 12 03:08:51 PM PDT 24
Finished Mar 12 03:12:25 PM PDT 24
Peak memory 251268 kb
Host smart-73aea69a-a027-44fb-b52f-7e99d0a6aebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187210226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1187210226
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2989266555
Short name T1399
Test name
Test status
Simulation time 3546457356 ps
CPU time 30.76 seconds
Started Mar 12 01:12:04 PM PDT 24
Finished Mar 12 01:12:35 PM PDT 24
Peak memory 235768 kb
Host smart-2cbec43d-d726-4a36-ae3e-e4fe10e1377a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989266555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2989266555
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1205857622
Short name T1647
Test name
Test status
Simulation time 5331463334 ps
CPU time 26.23 seconds
Started Mar 12 03:08:55 PM PDT 24
Finished Mar 12 03:09:23 PM PDT 24
Peak memory 233824 kb
Host smart-0a63b7eb-ed24-4ae2-bddd-92bb1b60582b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205857622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1205857622
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.753193631
Short name T876
Test name
Test status
Simulation time 8737707222 ps
CPU time 25.99 seconds
Started Mar 12 01:12:10 PM PDT 24
Finished Mar 12 01:12:36 PM PDT 24
Peak memory 235752 kb
Host smart-ea140128-6dd5-4064-9605-1526d8033c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753193631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.753193631
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3573577786
Short name T1916
Test name
Test status
Simulation time 15893823894 ps
CPU time 14 seconds
Started Mar 12 01:12:00 PM PDT 24
Finished Mar 12 01:12:14 PM PDT 24
Peak memory 233520 kb
Host smart-22870b9b-10c3-4b45-8999-8b004bdafe76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573577786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3573577786
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3926162133
Short name T1370
Test name
Test status
Simulation time 6111757515 ps
CPU time 6.79 seconds
Started Mar 12 03:08:53 PM PDT 24
Finished Mar 12 03:09:03 PM PDT 24
Peak memory 217368 kb
Host smart-9c10a60b-cdff-4324-96e2-76bdcce7edc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926162133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3926162133
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1545204469
Short name T542
Test name
Test status
Simulation time 4853348284 ps
CPU time 15.31 seconds
Started Mar 12 01:12:02 PM PDT 24
Finished Mar 12 01:12:18 PM PDT 24
Peak memory 224264 kb
Host smart-fb1ad2b2-ce9c-4427-bf0e-1668d5d89649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545204469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1545204469
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3826371077
Short name T246
Test name
Test status
Simulation time 28680976424 ps
CPU time 49.96 seconds
Started Mar 12 03:08:51 PM PDT 24
Finished Mar 12 03:09:43 PM PDT 24
Peak memory 232508 kb
Host smart-962aa21d-6096-4af5-b270-8b42fa25b7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826371077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3826371077
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1877929381
Short name T1164
Test name
Test status
Simulation time 991956111 ps
CPU time 8.24 seconds
Started Mar 12 01:12:05 PM PDT 24
Finished Mar 12 01:12:14 PM PDT 24
Peak memory 240508 kb
Host smart-d4990754-ea0a-489f-8acf-5cb3bc9e4e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877929381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1877929381
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3606900704
Short name T1882
Test name
Test status
Simulation time 294397704 ps
CPU time 3.98 seconds
Started Mar 12 03:08:52 PM PDT 24
Finished Mar 12 03:08:58 PM PDT 24
Peak memory 218056 kb
Host smart-52d2f7e0-7c0e-4eeb-aa14-79535a821371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606900704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3606900704
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2659147424
Short name T1809
Test name
Test status
Simulation time 2308487951 ps
CPU time 11.19 seconds
Started Mar 12 03:08:51 PM PDT 24
Finished Mar 12 03:09:04 PM PDT 24
Peak memory 237804 kb
Host smart-c931b1c7-c54b-44ad-b247-b9cb69783210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659147424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2659147424
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2986460513
Short name T1498
Test name
Test status
Simulation time 1313853968 ps
CPU time 12.7 seconds
Started Mar 12 01:12:01 PM PDT 24
Finished Mar 12 01:12:14 PM PDT 24
Peak memory 229860 kb
Host smart-999a2318-cffa-4e7c-92a0-450215ac70d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986460513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2986460513
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2723839894
Short name T1067
Test name
Test status
Simulation time 1522095360 ps
CPU time 3.96 seconds
Started Mar 12 03:08:51 PM PDT 24
Finished Mar 12 03:08:57 PM PDT 24
Peak memory 218736 kb
Host smart-5d7a94c0-ebb2-4b4c-88ab-e412d9c4e461
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2723839894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2723839894
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3661515964
Short name T980
Test name
Test status
Simulation time 905174749 ps
CPU time 4.24 seconds
Started Mar 12 01:12:01 PM PDT 24
Finished Mar 12 01:12:05 PM PDT 24
Peak memory 216276 kb
Host smart-7d6810a8-20b8-4789-b412-476ab38ddc4f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3661515964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3661515964
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2065914156
Short name T287
Test name
Test status
Simulation time 130371261325 ps
CPU time 175.58 seconds
Started Mar 12 03:08:51 PM PDT 24
Finished Mar 12 03:11:49 PM PDT 24
Peak memory 250160 kb
Host smart-5297033c-5707-4eb3-98ea-da3121ac5a8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065914156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2065914156
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.3278694239
Short name T284
Test name
Test status
Simulation time 97829740793 ps
CPU time 229.92 seconds
Started Mar 12 01:12:03 PM PDT 24
Finished Mar 12 01:15:53 PM PDT 24
Peak memory 251536 kb
Host smart-161809ff-8ca7-41ec-ad3e-b97e43170c0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278694239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3278694239
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1082704444
Short name T1742
Test name
Test status
Simulation time 1606202879 ps
CPU time 14.27 seconds
Started Mar 12 01:12:05 PM PDT 24
Finished Mar 12 01:12:19 PM PDT 24
Peak memory 216096 kb
Host smart-5455e431-cef2-4e7f-bf06-ebe5a8549a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082704444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1082704444
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2866262175
Short name T1080
Test name
Test status
Simulation time 3716068064 ps
CPU time 10.1 seconds
Started Mar 12 03:08:52 PM PDT 24
Finished Mar 12 03:09:04 PM PDT 24
Peak memory 216168 kb
Host smart-10bcb700-0321-48be-8487-e0e33c1b6afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866262175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2866262175
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1029720030
Short name T443
Test name
Test status
Simulation time 1123509542 ps
CPU time 3.55 seconds
Started Mar 12 01:12:01 PM PDT 24
Finished Mar 12 01:12:05 PM PDT 24
Peak memory 207904 kb
Host smart-6889250e-6d5b-4a07-a01b-78f9c7a14cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029720030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1029720030
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3920782612
Short name T512
Test name
Test status
Simulation time 2032576044 ps
CPU time 9.6 seconds
Started Mar 12 03:08:53 PM PDT 24
Finished Mar 12 03:09:04 PM PDT 24
Peak memory 216060 kb
Host smart-5c2c9e4d-689d-4253-9f85-ab7af4a034e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920782612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3920782612
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3467152029
Short name T682
Test name
Test status
Simulation time 795358655 ps
CPU time 3.26 seconds
Started Mar 12 01:12:03 PM PDT 24
Finished Mar 12 01:12:07 PM PDT 24
Peak memory 216064 kb
Host smart-99a13c86-eb35-4f46-9583-b0eddefe297d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467152029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3467152029
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3913768519
Short name T1919
Test name
Test status
Simulation time 297144541 ps
CPU time 1.9 seconds
Started Mar 12 03:08:54 PM PDT 24
Finished Mar 12 03:08:59 PM PDT 24
Peak memory 215936 kb
Host smart-d4d689d9-0131-4b84-93d5-f95e33fd5583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913768519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3913768519
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3041998976
Short name T676
Test name
Test status
Simulation time 67713409 ps
CPU time 1 seconds
Started Mar 12 01:12:01 PM PDT 24
Finished Mar 12 01:12:03 PM PDT 24
Peak memory 205164 kb
Host smart-891e7f21-e32b-48f7-a87b-9abeb1428703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041998976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3041998976
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.514510856
Short name T1773
Test name
Test status
Simulation time 847644609 ps
CPU time 1.11 seconds
Started Mar 12 03:08:52 PM PDT 24
Finished Mar 12 03:08:55 PM PDT 24
Peak memory 206272 kb
Host smart-a5f888a8-10ec-40f8-9347-e6c15390f5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514510856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.514510856
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2073993232
Short name T794
Test name
Test status
Simulation time 4993829149 ps
CPU time 15.61 seconds
Started Mar 12 03:08:52 PM PDT 24
Finished Mar 12 03:09:10 PM PDT 24
Peak memory 222684 kb
Host smart-bd2e9eb5-3a8b-4005-a374-6838c0543cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073993232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2073993232
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_upload.3164320834
Short name T1878
Test name
Test status
Simulation time 545463856 ps
CPU time 6.43 seconds
Started Mar 12 01:12:07 PM PDT 24
Finished Mar 12 01:12:13 PM PDT 24
Peak memory 234240 kb
Host smart-ad64f958-0f04-4ea4-b2b2-c0a53987559e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164320834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3164320834
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1565213404
Short name T1250
Test name
Test status
Simulation time 15166011 ps
CPU time 0.74 seconds
Started Mar 12 03:09:06 PM PDT 24
Finished Mar 12 03:09:07 PM PDT 24
Peak memory 205164 kb
Host smart-ab21541d-0e81-4955-9c89-46c8d28a5851
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565213404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1565213404
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.258112193
Short name T59
Test name
Test status
Simulation time 12772309 ps
CPU time 0.74 seconds
Started Mar 12 01:12:03 PM PDT 24
Finished Mar 12 01:12:05 PM PDT 24
Peak memory 204824 kb
Host smart-517a8f7d-32a1-4d71-a497-3381761da2ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258112193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.258112193
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2982967284
Short name T1534
Test name
Test status
Simulation time 219671245 ps
CPU time 4.02 seconds
Started Mar 12 01:12:01 PM PDT 24
Finished Mar 12 01:12:06 PM PDT 24
Peak memory 233420 kb
Host smart-748be104-f4a6-427c-ad01-1fb9efed9aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982967284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2982967284
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3245625687
Short name T902
Test name
Test status
Simulation time 469522007 ps
CPU time 2.95 seconds
Started Mar 12 03:08:52 PM PDT 24
Finished Mar 12 03:08:57 PM PDT 24
Peak memory 233400 kb
Host smart-9890b801-6a74-4720-bde8-0de91a81010b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245625687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3245625687
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2417271377
Short name T496
Test name
Test status
Simulation time 212495955 ps
CPU time 0.75 seconds
Started Mar 12 01:12:03 PM PDT 24
Finished Mar 12 01:12:05 PM PDT 24
Peak memory 206284 kb
Host smart-1035d445-2d0c-4040-8ed4-d793bab1d54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417271377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2417271377
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3521795984
Short name T1074
Test name
Test status
Simulation time 85635962 ps
CPU time 0.82 seconds
Started Mar 12 03:09:00 PM PDT 24
Finished Mar 12 03:09:02 PM PDT 24
Peak memory 205964 kb
Host smart-18f1c3db-2798-42f3-80e8-532c641e32a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521795984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3521795984
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.4198204616
Short name T186
Test name
Test status
Simulation time 90321478398 ps
CPU time 104.46 seconds
Started Mar 12 01:12:14 PM PDT 24
Finished Mar 12 01:13:59 PM PDT 24
Peak memory 249708 kb
Host smart-be6ac2e9-2c9f-46d8-8f31-c1807d513641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198204616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.4198204616
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.815846650
Short name T1450
Test name
Test status
Simulation time 67288688384 ps
CPU time 49.51 seconds
Started Mar 12 03:09:09 PM PDT 24
Finished Mar 12 03:09:59 PM PDT 24
Peak memory 234304 kb
Host smart-a554d558-221d-4685-987e-cf078391237f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815846650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.815846650
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1114982997
Short name T1152
Test name
Test status
Simulation time 46437547618 ps
CPU time 59.22 seconds
Started Mar 12 01:12:10 PM PDT 24
Finished Mar 12 01:13:10 PM PDT 24
Peak memory 220568 kb
Host smart-6bb23d57-2e73-4a19-8d9e-fb52634eef49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114982997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1114982997
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2358022550
Short name T1714
Test name
Test status
Simulation time 162762468749 ps
CPU time 107.43 seconds
Started Mar 12 03:10:03 PM PDT 24
Finished Mar 12 03:11:51 PM PDT 24
Peak memory 237112 kb
Host smart-079236dc-0fcb-4e7f-b84f-19912a789f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358022550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2358022550
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2562765869
Short name T360
Test name
Test status
Simulation time 37550404323 ps
CPU time 89.38 seconds
Started Mar 12 03:09:11 PM PDT 24
Finished Mar 12 03:10:41 PM PDT 24
Peak memory 248964 kb
Host smart-4a4b11e5-2ea9-4c7e-85f1-bf21580cc2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562765869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2562765869
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.4078716723
Short name T276
Test name
Test status
Simulation time 42995811117 ps
CPU time 344.45 seconds
Started Mar 12 01:12:04 PM PDT 24
Finished Mar 12 01:17:48 PM PDT 24
Peak memory 264824 kb
Host smart-24393fac-4bbe-42f9-a95d-a6e15b60a1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078716723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.4078716723
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1969778945
Short name T426
Test name
Test status
Simulation time 1621213215 ps
CPU time 15.96 seconds
Started Mar 12 01:12:02 PM PDT 24
Finished Mar 12 01:12:19 PM PDT 24
Peak memory 248144 kb
Host smart-a6b1bd75-4f23-4574-a7b1-0f20b0ef9f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969778945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1969778945
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.248571201
Short name T1846
Test name
Test status
Simulation time 4141423772 ps
CPU time 24.77 seconds
Started Mar 12 03:08:53 PM PDT 24
Finished Mar 12 03:09:19 PM PDT 24
Peak memory 232444 kb
Host smart-12c56fd5-0f23-4144-9fc7-d4ce086a909c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248571201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.248571201
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2949824713
Short name T245
Test name
Test status
Simulation time 318478174 ps
CPU time 2.63 seconds
Started Mar 12 01:12:03 PM PDT 24
Finished Mar 12 01:12:06 PM PDT 24
Peak memory 217644 kb
Host smart-c10679d3-88ed-4a55-8744-bbabb3bc2cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949824713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2949824713
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_intercept.4264304467
Short name T1593
Test name
Test status
Simulation time 12116265372 ps
CPU time 12.07 seconds
Started Mar 12 03:08:55 PM PDT 24
Finished Mar 12 03:09:09 PM PDT 24
Peak memory 233112 kb
Host smart-a1a4d826-0c6f-442a-aa7e-4a836e7a4221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264304467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.4264304467
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1052273583
Short name T1206
Test name
Test status
Simulation time 13509094326 ps
CPU time 12.6 seconds
Started Mar 12 01:12:03 PM PDT 24
Finished Mar 12 01:12:16 PM PDT 24
Peak memory 232812 kb
Host smart-0feb6df8-e1d9-4d08-8dbd-7afcc045570f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052273583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1052273583
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.131325468
Short name T1727
Test name
Test status
Simulation time 1130143095 ps
CPU time 5.68 seconds
Started Mar 12 03:08:54 PM PDT 24
Finished Mar 12 03:09:02 PM PDT 24
Peak memory 224188 kb
Host smart-5bb18a8e-817a-4321-96d5-e8728dc29f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131325468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.131325468
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2398529851
Short name T1792
Test name
Test status
Simulation time 12727666319 ps
CPU time 7.88 seconds
Started Mar 12 03:08:52 PM PDT 24
Finished Mar 12 03:09:02 PM PDT 24
Peak memory 234168 kb
Host smart-ab82ebfb-631d-40b9-8e71-2ed84654d280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398529851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2398529851
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.70009072
Short name T1352
Test name
Test status
Simulation time 5335699017 ps
CPU time 7.91 seconds
Started Mar 12 01:12:02 PM PDT 24
Finished Mar 12 01:12:10 PM PDT 24
Peak memory 224168 kb
Host smart-867acc9b-6932-4c21-a271-5f3951919689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70009072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap.70009072
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.504095408
Short name T1918
Test name
Test status
Simulation time 11195318746 ps
CPU time 8.77 seconds
Started Mar 12 03:08:53 PM PDT 24
Finished Mar 12 03:09:05 PM PDT 24
Peak memory 228404 kb
Host smart-3344a0fe-011c-44d7-8e27-52d12b27b5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504095408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.504095408
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.894443806
Short name T451
Test name
Test status
Simulation time 3712393692 ps
CPU time 12.63 seconds
Started Mar 12 01:12:01 PM PDT 24
Finished Mar 12 01:12:14 PM PDT 24
Peak memory 217060 kb
Host smart-1b0cb0ae-77c2-4f77-9811-1540e0f43ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894443806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.894443806
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2299208242
Short name T926
Test name
Test status
Simulation time 1943598270 ps
CPU time 5.94 seconds
Started Mar 12 03:09:08 PM PDT 24
Finished Mar 12 03:09:14 PM PDT 24
Peak memory 222392 kb
Host smart-95dce916-752a-4741-8072-1b34bba827a2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2299208242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2299208242
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.387347583
Short name T836
Test name
Test status
Simulation time 668645110 ps
CPU time 3.35 seconds
Started Mar 12 01:12:02 PM PDT 24
Finished Mar 12 01:12:06 PM PDT 24
Peak memory 218640 kb
Host smart-7b29e7e4-ad73-40a2-bb1e-211804d8228e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=387347583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.387347583
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3367371759
Short name T1181
Test name
Test status
Simulation time 93363579 ps
CPU time 1.02 seconds
Started Mar 12 01:12:15 PM PDT 24
Finished Mar 12 01:12:16 PM PDT 24
Peak memory 206208 kb
Host smart-3b1baa00-d21b-44b6-b252-47467b691b2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367371759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3367371759
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1803128436
Short name T7
Test name
Test status
Simulation time 39105014686 ps
CPU time 52.79 seconds
Started Mar 12 03:08:55 PM PDT 24
Finished Mar 12 03:09:50 PM PDT 24
Peak memory 216112 kb
Host smart-5515bcaa-9cbc-4f95-bd2b-a9286e211d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803128436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1803128436
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2003158226
Short name T834
Test name
Test status
Simulation time 7737315202 ps
CPU time 20.95 seconds
Started Mar 12 01:12:10 PM PDT 24
Finished Mar 12 01:12:31 PM PDT 24
Peak memory 216056 kb
Host smart-9026b266-b34b-448f-90be-f56cf2dfbdc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003158226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2003158226
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2124865639
Short name T394
Test name
Test status
Simulation time 2451053298 ps
CPU time 11.88 seconds
Started Mar 12 03:08:54 PM PDT 24
Finished Mar 12 03:09:09 PM PDT 24
Peak memory 216172 kb
Host smart-f74438ec-5d9f-4ef9-a3f0-a33a27c4278c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124865639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2124865639
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3775822526
Short name T708
Test name
Test status
Simulation time 16838001963 ps
CPU time 11.52 seconds
Started Mar 12 01:12:07 PM PDT 24
Finished Mar 12 01:12:18 PM PDT 24
Peak memory 216104 kb
Host smart-00c5649c-6753-4912-9b52-b21afa8329c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775822526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3775822526
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.189294348
Short name T530
Test name
Test status
Simulation time 47459180 ps
CPU time 1.1 seconds
Started Mar 12 01:12:02 PM PDT 24
Finished Mar 12 01:12:03 PM PDT 24
Peak memory 207072 kb
Host smart-491e524d-bbe8-4c6b-a1fc-a241c54ec956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189294348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.189294348
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.724003482
Short name T1146
Test name
Test status
Simulation time 31084629 ps
CPU time 1.12 seconds
Started Mar 12 03:08:52 PM PDT 24
Finished Mar 12 03:08:55 PM PDT 24
Peak memory 207028 kb
Host smart-54d61369-bdbd-4c0c-86c2-339311584881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724003482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.724003482
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3559911260
Short name T862
Test name
Test status
Simulation time 66017737 ps
CPU time 1 seconds
Started Mar 12 03:08:54 PM PDT 24
Finished Mar 12 03:08:58 PM PDT 24
Peak memory 206284 kb
Host smart-a7911f50-be92-4963-8264-452997c738a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559911260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3559911260
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.806975018
Short name T1198
Test name
Test status
Simulation time 195288167 ps
CPU time 1.01 seconds
Started Mar 12 01:12:04 PM PDT 24
Finished Mar 12 01:12:06 PM PDT 24
Peak memory 205608 kb
Host smart-06ea47e3-0762-4308-82b1-7a4ff500d8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806975018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.806975018
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1353974214
Short name T1732
Test name
Test status
Simulation time 1105693431 ps
CPU time 5.73 seconds
Started Mar 12 03:08:52 PM PDT 24
Finished Mar 12 03:09:00 PM PDT 24
Peak memory 236108 kb
Host smart-35a808e2-6187-494f-853b-24cdfdbc4f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353974214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1353974214
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_upload.2743003872
Short name T485
Test name
Test status
Simulation time 839554764 ps
CPU time 10.73 seconds
Started Mar 12 01:12:02 PM PDT 24
Finished Mar 12 01:12:13 PM PDT 24
Peak memory 222776 kb
Host smart-61cb6f3f-43a8-47b1-b341-d98f0ca059d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743003872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2743003872
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3184352797
Short name T617
Test name
Test status
Simulation time 14902817 ps
CPU time 0.71 seconds
Started Mar 12 01:10:30 PM PDT 24
Finished Mar 12 01:10:30 PM PDT 24
Peak memory 204836 kb
Host smart-98227fcf-9eae-4dcd-ab40-ffc879aefd63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184352797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
184352797
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.61661428
Short name T966
Test name
Test status
Simulation time 21654217 ps
CPU time 0.72 seconds
Started Mar 12 03:05:37 PM PDT 24
Finished Mar 12 03:05:39 PM PDT 24
Peak memory 204264 kb
Host smart-3bacd78c-3276-4ddf-96ec-a3a0f4fedd7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61661428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.61661428
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1866077195
Short name T766
Test name
Test status
Simulation time 758177561 ps
CPU time 3.71 seconds
Started Mar 12 03:05:27 PM PDT 24
Finished Mar 12 03:05:31 PM PDT 24
Peak memory 217244 kb
Host smart-394046aa-51a5-40aa-9e4f-9fea46e81d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866077195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1866077195
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2664960446
Short name T1660
Test name
Test status
Simulation time 374699778 ps
CPU time 3.43 seconds
Started Mar 12 01:10:30 PM PDT 24
Finished Mar 12 01:10:34 PM PDT 24
Peak memory 233384 kb
Host smart-bf49550f-158a-4bbf-b4da-6b7ab5d13f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664960446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2664960446
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2226502366
Short name T1605
Test name
Test status
Simulation time 37728682 ps
CPU time 0.77 seconds
Started Mar 12 01:10:27 PM PDT 24
Finished Mar 12 01:10:28 PM PDT 24
Peak memory 204916 kb
Host smart-91d6ce98-efc2-4f87-8c2f-da660e0aed51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226502366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2226502366
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3032470753
Short name T1710
Test name
Test status
Simulation time 49859315 ps
CPU time 0.78 seconds
Started Mar 12 03:05:28 PM PDT 24
Finished Mar 12 03:05:29 PM PDT 24
Peak memory 204932 kb
Host smart-df9eb50a-7e75-42bb-a7a1-40b48e9bc9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032470753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3032470753
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.313758568
Short name T1442
Test name
Test status
Simulation time 2825969436 ps
CPU time 27.79 seconds
Started Mar 12 01:10:28 PM PDT 24
Finished Mar 12 01:10:56 PM PDT 24
Peak memory 237388 kb
Host smart-a10ed4ca-1f62-4c7b-8831-9d47ccb44c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313758568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.313758568
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3761621916
Short name T348
Test name
Test status
Simulation time 587258486 ps
CPU time 8.25 seconds
Started Mar 12 03:05:37 PM PDT 24
Finished Mar 12 03:05:46 PM PDT 24
Peak memory 234032 kb
Host smart-2b6dee72-1923-4a34-815a-292fdffae2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761621916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3761621916
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2557283805
Short name T390
Test name
Test status
Simulation time 31063673139 ps
CPU time 216.96 seconds
Started Mar 12 03:05:36 PM PDT 24
Finished Mar 12 03:09:13 PM PDT 24
Peak memory 240756 kb
Host smart-eb74c44a-afb2-4058-886b-3fe5d45efdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557283805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2557283805
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3507565109
Short name T1815
Test name
Test status
Simulation time 16123246222 ps
CPU time 129.97 seconds
Started Mar 12 01:10:27 PM PDT 24
Finished Mar 12 01:12:37 PM PDT 24
Peak memory 256600 kb
Host smart-f966db5b-1adc-49d6-a613-c2ba8e3d82e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507565109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3507565109
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.50322603
Short name T51
Test name
Test status
Simulation time 49650966528 ps
CPU time 91.8 seconds
Started Mar 12 03:05:36 PM PDT 24
Finished Mar 12 03:07:08 PM PDT 24
Peak memory 249020 kb
Host smart-ebd0f0f1-23cf-469c-9096-adf2b35e3198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50322603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.50322603
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2615943461
Short name T1179
Test name
Test status
Simulation time 2511095851 ps
CPU time 11.44 seconds
Started Mar 12 03:05:38 PM PDT 24
Finished Mar 12 03:05:50 PM PDT 24
Peak memory 247316 kb
Host smart-47cd1f7d-de8b-4664-b948-393fff438207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615943461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2615943461
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3723299246
Short name T1242
Test name
Test status
Simulation time 6409116747 ps
CPU time 14.27 seconds
Started Mar 12 01:10:28 PM PDT 24
Finished Mar 12 01:10:43 PM PDT 24
Peak memory 239276 kb
Host smart-b5c11d83-5c1d-4f82-a549-5521a7022ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723299246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3723299246
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1904991050
Short name T1246
Test name
Test status
Simulation time 8010967243 ps
CPU time 6.94 seconds
Started Mar 12 03:05:27 PM PDT 24
Finished Mar 12 03:05:35 PM PDT 24
Peak memory 217364 kb
Host smart-73405b26-2d3f-470d-b5df-e48ea174bed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904991050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1904991050
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_intercept.4070129449
Short name T861
Test name
Test status
Simulation time 2813465116 ps
CPU time 8.31 seconds
Started Mar 12 01:10:26 PM PDT 24
Finished Mar 12 01:10:35 PM PDT 24
Peak memory 219196 kb
Host smart-e73e8b7d-0516-45f9-b40f-027b5f5605c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070129449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.4070129449
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3116395371
Short name T1081
Test name
Test status
Simulation time 1052176484 ps
CPU time 14.24 seconds
Started Mar 12 03:05:29 PM PDT 24
Finished Mar 12 03:05:43 PM PDT 24
Peak memory 248364 kb
Host smart-e739c9e4-eb92-4178-9124-dcb5a9cc11f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116395371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3116395371
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.465089920
Short name T44
Test name
Test status
Simulation time 5518229142 ps
CPU time 14.95 seconds
Started Mar 12 01:10:26 PM PDT 24
Finished Mar 12 01:10:41 PM PDT 24
Peak memory 232452 kb
Host smart-3cdd90d9-73c0-4a44-bb6e-ffecd843a82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465089920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.465089920
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.101564064
Short name T960
Test name
Test status
Simulation time 14924830 ps
CPU time 1.02 seconds
Started Mar 12 03:05:27 PM PDT 24
Finished Mar 12 03:05:28 PM PDT 24
Peak memory 217544 kb
Host smart-a9f91686-3e18-4017-a1af-907d85d05788
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101564064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.spi_device_mem_parity.101564064
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.1921866176
Short name T1214
Test name
Test status
Simulation time 15629321 ps
CPU time 0.95 seconds
Started Mar 12 01:10:27 PM PDT 24
Finished Mar 12 01:10:29 PM PDT 24
Peak memory 217576 kb
Host smart-933c5bba-e57f-4809-bd59-bca615ed9445
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921866176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.1921866176
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2257838116
Short name T474
Test name
Test status
Simulation time 16779887748 ps
CPU time 5.88 seconds
Started Mar 12 03:05:30 PM PDT 24
Finished Mar 12 03:05:40 PM PDT 24
Peak memory 224204 kb
Host smart-700065a6-76d0-4bc3-9908-08d7d67ba3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257838116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2257838116
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.519868748
Short name T1671
Test name
Test status
Simulation time 13500691118 ps
CPU time 11.5 seconds
Started Mar 12 01:10:31 PM PDT 24
Finished Mar 12 01:10:43 PM PDT 24
Peak memory 233140 kb
Host smart-3054641a-d162-4e5b-a21c-85568016f8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519868748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
519868748
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1701683283
Short name T1187
Test name
Test status
Simulation time 337296626 ps
CPU time 4.45 seconds
Started Mar 12 01:10:27 PM PDT 24
Finished Mar 12 01:10:32 PM PDT 24
Peak memory 233224 kb
Host smart-bd68395e-4d2f-4894-a8d1-916a00c015d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701683283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1701683283
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2822865895
Short name T43
Test name
Test status
Simulation time 10915030042 ps
CPU time 8.25 seconds
Started Mar 12 03:05:29 PM PDT 24
Finished Mar 12 03:05:37 PM PDT 24
Peak memory 216132 kb
Host smart-eb8bd49a-51e3-4186-8b6a-17b9ae768249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822865895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2822865895
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.2962890862
Short name T730
Test name
Test status
Simulation time 45349281 ps
CPU time 0.76 seconds
Started Mar 12 01:10:30 PM PDT 24
Finished Mar 12 01:10:31 PM PDT 24
Peak memory 215976 kb
Host smart-67ee6750-bbc1-4903-8ad8-020780b9cd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962890862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.2962890862
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.811264134
Short name T1481
Test name
Test status
Simulation time 16985095 ps
CPU time 0.75 seconds
Started Mar 12 03:05:29 PM PDT 24
Finished Mar 12 03:05:30 PM PDT 24
Peak memory 215928 kb
Host smart-7cedc6ca-2a48-4fb1-a57b-410d909f83a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811264134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.811264134
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1698762281
Short name T1858
Test name
Test status
Simulation time 2094390668 ps
CPU time 5.47 seconds
Started Mar 12 01:10:30 PM PDT 24
Finished Mar 12 01:10:36 PM PDT 24
Peak memory 219708 kb
Host smart-e69818c2-b5c9-4b46-8432-9f7c0863e45f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1698762281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1698762281
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2911687176
Short name T447
Test name
Test status
Simulation time 335974333 ps
CPU time 3.6 seconds
Started Mar 12 03:05:37 PM PDT 24
Finished Mar 12 03:05:41 PM PDT 24
Peak memory 221672 kb
Host smart-0042cbef-4070-4fd8-b4a0-5bbb7ff9a90a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2911687176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2911687176
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1002358424
Short name T68
Test name
Test status
Simulation time 197721676 ps
CPU time 1 seconds
Started Mar 12 01:10:28 PM PDT 24
Finished Mar 12 01:10:29 PM PDT 24
Peak memory 234704 kb
Host smart-8f8edc94-0e86-496b-b774-82c5a67f4338
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002358424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1002358424
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3348041217
Short name T69
Test name
Test status
Simulation time 477190080 ps
CPU time 1.19 seconds
Started Mar 12 03:05:38 PM PDT 24
Finished Mar 12 03:05:39 PM PDT 24
Peak memory 235848 kb
Host smart-71388b85-b509-4221-99c3-0cd2821d9620
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348041217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3348041217
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.164829958
Short name T1873
Test name
Test status
Simulation time 25409406606 ps
CPU time 79.44 seconds
Started Mar 12 01:10:28 PM PDT 24
Finished Mar 12 01:11:48 PM PDT 24
Peak memory 264924 kb
Host smart-581d50e4-c725-4526-a4a3-83b30c6420ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164829958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.164829958
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3625939236
Short name T1509
Test name
Test status
Simulation time 111887934 ps
CPU time 1.03 seconds
Started Mar 12 03:05:35 PM PDT 24
Finished Mar 12 03:05:37 PM PDT 24
Peak memory 206500 kb
Host smart-1bf57958-9c03-4ff1-aa63-02ab2ffa8e79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625939236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3625939236
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1022027068
Short name T765
Test name
Test status
Simulation time 5782945498 ps
CPU time 31.9 seconds
Started Mar 12 03:05:26 PM PDT 24
Finished Mar 12 03:05:59 PM PDT 24
Peak memory 216168 kb
Host smart-1eeba43e-8760-414a-aead-c273d8a64905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022027068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1022027068
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2408834492
Short name T380
Test name
Test status
Simulation time 5387484135 ps
CPU time 25.79 seconds
Started Mar 12 01:10:30 PM PDT 24
Finished Mar 12 01:10:56 PM PDT 24
Peak memory 216108 kb
Host smart-13ea6efb-3d5b-424d-9f17-1a9941d0bf9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408834492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2408834492
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1118650873
Short name T1059
Test name
Test status
Simulation time 13390481447 ps
CPU time 9.61 seconds
Started Mar 12 03:05:27 PM PDT 24
Finished Mar 12 03:05:37 PM PDT 24
Peak memory 216112 kb
Host smart-83293e64-e3f7-4e0a-8b10-580be88c9bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118650873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1118650873
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.4052720008
Short name T410
Test name
Test status
Simulation time 19063186757 ps
CPU time 18.25 seconds
Started Mar 12 01:10:27 PM PDT 24
Finished Mar 12 01:10:46 PM PDT 24
Peak memory 216116 kb
Host smart-b7d7e658-a8f2-49ab-8412-dbe1c31b6db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052720008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.4052720008
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1948234578
Short name T1599
Test name
Test status
Simulation time 440021464 ps
CPU time 2.66 seconds
Started Mar 12 03:05:28 PM PDT 24
Finished Mar 12 03:05:31 PM PDT 24
Peak memory 216028 kb
Host smart-8c4115ed-7c65-4704-84bf-8b5540ec7cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948234578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1948234578
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.855454411
Short name T1141
Test name
Test status
Simulation time 173924800 ps
CPU time 1.49 seconds
Started Mar 12 01:10:26 PM PDT 24
Finished Mar 12 01:10:28 PM PDT 24
Peak memory 216304 kb
Host smart-ced7a33d-88dc-4336-b405-504048741680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855454411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.855454411
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1381654284
Short name T1403
Test name
Test status
Simulation time 124457499 ps
CPU time 0.91 seconds
Started Mar 12 01:10:28 PM PDT 24
Finished Mar 12 01:10:29 PM PDT 24
Peak memory 205248 kb
Host smart-a36dfd30-ac7c-4066-aff1-dcda5c56827e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381654284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1381654284
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3254812058
Short name T1108
Test name
Test status
Simulation time 510309530 ps
CPU time 0.95 seconds
Started Mar 12 03:05:28 PM PDT 24
Finished Mar 12 03:05:29 PM PDT 24
Peak memory 205244 kb
Host smart-75251579-02c2-4569-bc78-15ae44716cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254812058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3254812058
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.3994297789
Short name T997
Test name
Test status
Simulation time 8651981798 ps
CPU time 8.31 seconds
Started Mar 12 01:10:25 PM PDT 24
Finished Mar 12 01:10:34 PM PDT 24
Peak memory 218300 kb
Host smart-ed234893-5c72-410c-82a1-ac1291c36251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994297789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3994297789
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_upload.4253239379
Short name T1762
Test name
Test status
Simulation time 127100191 ps
CPU time 2.89 seconds
Started Mar 12 03:05:27 PM PDT 24
Finished Mar 12 03:05:30 PM PDT 24
Peak memory 217048 kb
Host smart-40ce9e4d-f5bf-4097-8264-b14f9224315c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253239379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.4253239379
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2885087807
Short name T937
Test name
Test status
Simulation time 47484126 ps
CPU time 0.76 seconds
Started Mar 12 01:12:10 PM PDT 24
Finished Mar 12 01:12:11 PM PDT 24
Peak memory 203536 kb
Host smart-8294be58-e089-49d8-b47c-a5834d5bb165
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885087807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2885087807
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3197408318
Short name T1128
Test name
Test status
Simulation time 203324097 ps
CPU time 0.73 seconds
Started Mar 12 03:09:06 PM PDT 24
Finished Mar 12 03:09:06 PM PDT 24
Peak memory 204768 kb
Host smart-02532824-0f19-475a-aa08-8e6d45b9ab58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197408318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3197408318
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1282136536
Short name T1634
Test name
Test status
Simulation time 6650145464 ps
CPU time 6.41 seconds
Started Mar 12 01:12:04 PM PDT 24
Finished Mar 12 01:12:10 PM PDT 24
Peak memory 219448 kb
Host smart-aaf41294-2dd7-4fd6-b064-d6172e08b29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282136536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1282136536
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.4040107272
Short name T534
Test name
Test status
Simulation time 806833601 ps
CPU time 2.25 seconds
Started Mar 12 03:09:11 PM PDT 24
Finished Mar 12 03:09:14 PM PDT 24
Peak memory 218116 kb
Host smart-2573642d-7773-4289-9a16-30d300045481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040107272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.4040107272
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1046228024
Short name T439
Test name
Test status
Simulation time 22708693 ps
CPU time 0.71 seconds
Started Mar 12 03:09:10 PM PDT 24
Finished Mar 12 03:09:10 PM PDT 24
Peak memory 204908 kb
Host smart-3aa7dc83-d59d-428f-bc4c-d20d6eb1ee4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046228024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1046228024
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2117725888
Short name T330
Test name
Test status
Simulation time 137885937 ps
CPU time 0.73 seconds
Started Mar 12 01:12:03 PM PDT 24
Finished Mar 12 01:12:05 PM PDT 24
Peak memory 206268 kb
Host smart-69d75cb5-4264-461a-a0ce-d29a26877df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117725888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2117725888
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1252054560
Short name T21
Test name
Test status
Simulation time 41605374917 ps
CPU time 204.17 seconds
Started Mar 12 03:09:10 PM PDT 24
Finished Mar 12 03:12:34 PM PDT 24
Peak memory 252600 kb
Host smart-200a4a60-16b3-4ac9-a2ce-5648dfeb7650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252054560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1252054560
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3117333408
Short name T887
Test name
Test status
Simulation time 462540099 ps
CPU time 5.59 seconds
Started Mar 12 01:12:09 PM PDT 24
Finished Mar 12 01:12:15 PM PDT 24
Peak memory 224152 kb
Host smart-e60046a9-b05d-4604-94dd-c2d6a82358bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117333408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3117333408
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.2962832862
Short name T1052
Test name
Test status
Simulation time 14561789923 ps
CPU time 131.68 seconds
Started Mar 12 01:12:05 PM PDT 24
Finished Mar 12 01:14:17 PM PDT 24
Peak memory 249008 kb
Host smart-4f7f15b8-acf6-41af-a475-486b883866bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962832862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2962832862
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3597996400
Short name T19
Test name
Test status
Simulation time 56992495381 ps
CPU time 362.56 seconds
Started Mar 12 03:09:14 PM PDT 24
Finished Mar 12 03:15:17 PM PDT 24
Peak memory 256792 kb
Host smart-507f986f-47e9-4dbb-86e8-21e83a8af551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597996400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3597996400
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3438896585
Short name T15
Test name
Test status
Simulation time 36945026363 ps
CPU time 70.56 seconds
Started Mar 12 03:09:11 PM PDT 24
Finished Mar 12 03:10:22 PM PDT 24
Peak memory 237144 kb
Host smart-c080f88b-9b31-4933-8045-93b9a58cbb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438896585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3438896585
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.485199359
Short name T1305
Test name
Test status
Simulation time 16078449623 ps
CPU time 148.35 seconds
Started Mar 12 01:12:04 PM PDT 24
Finished Mar 12 01:14:33 PM PDT 24
Peak memory 249004 kb
Host smart-960bdaab-f5cf-4eca-802a-6cde0fa74abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485199359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.485199359
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3842558044
Short name T1793
Test name
Test status
Simulation time 2681185160 ps
CPU time 9.32 seconds
Started Mar 12 03:09:09 PM PDT 24
Finished Mar 12 03:09:19 PM PDT 24
Peak memory 227044 kb
Host smart-3e0e0775-6c27-4f33-94aa-9ff90a49f409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842558044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3842558044
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.4081125622
Short name T771
Test name
Test status
Simulation time 992198493 ps
CPU time 12.22 seconds
Started Mar 12 01:12:04 PM PDT 24
Finished Mar 12 01:12:16 PM PDT 24
Peak memory 240616 kb
Host smart-b98d9f16-d83b-451e-96d5-f13d33688216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081125622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.4081125622
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3192976203
Short name T1537
Test name
Test status
Simulation time 485915868 ps
CPU time 3.52 seconds
Started Mar 12 01:12:03 PM PDT 24
Finished Mar 12 01:12:07 PM PDT 24
Peak memory 224040 kb
Host smart-1ca94a7d-495a-4fcd-a8e4-7e0b574233b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192976203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3192976203
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_intercept.806450507
Short name T1421
Test name
Test status
Simulation time 9230284176 ps
CPU time 8.81 seconds
Started Mar 12 03:09:08 PM PDT 24
Finished Mar 12 03:09:16 PM PDT 24
Peak memory 233784 kb
Host smart-a2b98fb1-469a-4b05-9c8d-19a53e32083a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806450507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.806450507
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2051168951
Short name T875
Test name
Test status
Simulation time 13301930328 ps
CPU time 17.28 seconds
Started Mar 12 03:09:08 PM PDT 24
Finished Mar 12 03:09:25 PM PDT 24
Peak memory 239620 kb
Host smart-5adef75a-7df9-4055-a534-944309f055c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051168951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2051168951
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2299247802
Short name T210
Test name
Test status
Simulation time 1609468475 ps
CPU time 12.21 seconds
Started Mar 12 01:12:03 PM PDT 24
Finished Mar 12 01:12:16 PM PDT 24
Peak memory 232896 kb
Host smart-f4cbe4f5-b07d-401d-83a9-b7df5d771b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299247802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2299247802
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1591975864
Short name T1554
Test name
Test status
Simulation time 263430569 ps
CPU time 5.14 seconds
Started Mar 12 01:12:10 PM PDT 24
Finished Mar 12 01:12:15 PM PDT 24
Peak memory 236260 kb
Host smart-81d8c09b-aa87-43a5-a43a-0c84343a7dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591975864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1591975864
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2811418634
Short name T372
Test name
Test status
Simulation time 18089266037 ps
CPU time 12.74 seconds
Started Mar 12 03:09:07 PM PDT 24
Finished Mar 12 03:09:19 PM PDT 24
Peak memory 224240 kb
Host smart-d071639c-4c3f-43e1-93d0-c8be4ea75b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811418634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2811418634
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3688086554
Short name T1215
Test name
Test status
Simulation time 666056360 ps
CPU time 5.35 seconds
Started Mar 12 01:12:09 PM PDT 24
Finished Mar 12 01:12:15 PM PDT 24
Peak memory 232676 kb
Host smart-2adf66f8-91ea-49da-b2f1-5dd1fb1b5986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688086554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3688086554
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3916992849
Short name T1827
Test name
Test status
Simulation time 99545360 ps
CPU time 2.22 seconds
Started Mar 12 03:09:10 PM PDT 24
Finished Mar 12 03:09:12 PM PDT 24
Peak memory 224136 kb
Host smart-9e0a5a03-b7c9-4980-bc93-033a57ff7469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916992849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3916992849
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1979902732
Short name T1115
Test name
Test status
Simulation time 1762161134 ps
CPU time 5 seconds
Started Mar 12 01:12:09 PM PDT 24
Finished Mar 12 01:12:14 PM PDT 24
Peak memory 221788 kb
Host smart-bc99b2a7-eae1-4759-9fec-97edbbebd587
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1979902732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1979902732
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2284225642
Short name T1073
Test name
Test status
Simulation time 647098610 ps
CPU time 4.89 seconds
Started Mar 12 03:09:14 PM PDT 24
Finished Mar 12 03:09:19 PM PDT 24
Peak memory 222508 kb
Host smart-0b90cc1f-69cf-4565-9763-c593e17323ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2284225642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2284225642
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2862128799
Short name T41
Test name
Test status
Simulation time 31447478172 ps
CPU time 254.19 seconds
Started Mar 12 03:09:07 PM PDT 24
Finished Mar 12 03:13:22 PM PDT 24
Peak memory 263052 kb
Host smart-2e43d0af-ef94-4f57-b6f4-b5e8bc22d2d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862128799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2862128799
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.712077777
Short name T509
Test name
Test status
Simulation time 84243539300 ps
CPU time 161.96 seconds
Started Mar 12 01:12:10 PM PDT 24
Finished Mar 12 01:14:52 PM PDT 24
Peak memory 248892 kb
Host smart-0d04b6ed-4c2c-41a5-8ac7-938c588cd689
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712077777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.712077777
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2710695892
Short name T1425
Test name
Test status
Simulation time 877932278 ps
CPU time 16.2 seconds
Started Mar 12 01:12:03 PM PDT 24
Finished Mar 12 01:12:20 PM PDT 24
Peak memory 216064 kb
Host smart-76b185ff-8e47-4c5f-a4be-c302b85cd7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710695892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2710695892
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.869484098
Short name T971
Test name
Test status
Simulation time 31630399422 ps
CPU time 47.14 seconds
Started Mar 12 03:09:05 PM PDT 24
Finished Mar 12 03:09:52 PM PDT 24
Peak memory 216104 kb
Host smart-44e91d01-7016-46cc-8a4f-d85ac3629cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869484098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.869484098
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2950482007
Short name T1044
Test name
Test status
Simulation time 1107456435 ps
CPU time 2.59 seconds
Started Mar 12 01:12:02 PM PDT 24
Finished Mar 12 01:12:06 PM PDT 24
Peak memory 207940 kb
Host smart-a260e8e5-1476-427f-acd4-730ab580ebf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950482007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2950482007
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.900836552
Short name T962
Test name
Test status
Simulation time 843109601 ps
CPU time 1.69 seconds
Started Mar 12 03:09:07 PM PDT 24
Finished Mar 12 03:09:09 PM PDT 24
Peak memory 206500 kb
Host smart-571ff737-0567-4cdf-8e3b-52edac3ade74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900836552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.900836552
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2015844799
Short name T629
Test name
Test status
Simulation time 243897835 ps
CPU time 3.55 seconds
Started Mar 12 01:12:04 PM PDT 24
Finished Mar 12 01:12:08 PM PDT 24
Peak memory 216080 kb
Host smart-6bd3b079-5a8a-470b-8b81-0769f7be4f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015844799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2015844799
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.519474814
Short name T579
Test name
Test status
Simulation time 593878820 ps
CPU time 3.26 seconds
Started Mar 12 03:09:07 PM PDT 24
Finished Mar 12 03:09:10 PM PDT 24
Peak memory 216008 kb
Host smart-83b5f64c-ecae-4912-978d-a9dd0598cf33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519474814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.519474814
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2071423265
Short name T895
Test name
Test status
Simulation time 106919431 ps
CPU time 1.04 seconds
Started Mar 12 01:12:03 PM PDT 24
Finished Mar 12 01:12:04 PM PDT 24
Peak memory 206256 kb
Host smart-5dfb2180-bcbf-486f-9928-3eb00e492867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071423265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2071423265
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3628037256
Short name T786
Test name
Test status
Simulation time 66253681 ps
CPU time 0.7 seconds
Started Mar 12 03:09:07 PM PDT 24
Finished Mar 12 03:09:08 PM PDT 24
Peak memory 205256 kb
Host smart-ba56c98a-cdf4-403e-82bb-5aae6f0762a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628037256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3628037256
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.2542213467
Short name T1211
Test name
Test status
Simulation time 552824816 ps
CPU time 10.29 seconds
Started Mar 12 01:12:03 PM PDT 24
Finished Mar 12 01:12:14 PM PDT 24
Peak memory 248596 kb
Host smart-d742e40b-b987-4d18-ae60-c49069be2e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542213467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2542213467
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_upload.805236300
Short name T195
Test name
Test status
Simulation time 76068873901 ps
CPU time 34.77 seconds
Started Mar 12 03:09:14 PM PDT 24
Finished Mar 12 03:09:49 PM PDT 24
Peak memory 234184 kb
Host smart-c857240f-9bcd-4432-9c3a-cd84fd1d75c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805236300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.805236300
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1400453316
Short name T744
Test name
Test status
Simulation time 15985811 ps
CPU time 0.73 seconds
Started Mar 12 03:09:14 PM PDT 24
Finished Mar 12 03:09:15 PM PDT 24
Peak memory 204196 kb
Host smart-110776e7-4195-421c-97c4-761f160a92c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400453316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1400453316
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2172577594
Short name T1100
Test name
Test status
Simulation time 40757549 ps
CPU time 0.73 seconds
Started Mar 12 01:12:17 PM PDT 24
Finished Mar 12 01:12:18 PM PDT 24
Peak memory 204792 kb
Host smart-551e14d0-a17a-4ab8-b5ab-601b1ba2828f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172577594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2172577594
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2862621282
Short name T1689
Test name
Test status
Simulation time 61157835 ps
CPU time 2.48 seconds
Started Mar 12 01:12:17 PM PDT 24
Finished Mar 12 01:12:20 PM PDT 24
Peak memory 233340 kb
Host smart-52f26b60-fc1a-4dd6-a400-b87cd21d2f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862621282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2862621282
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3164531443
Short name T1258
Test name
Test status
Simulation time 853390689 ps
CPU time 4.77 seconds
Started Mar 12 03:09:06 PM PDT 24
Finished Mar 12 03:09:11 PM PDT 24
Peak memory 233204 kb
Host smart-62fb485e-64e6-432c-a0c5-e61e05515637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164531443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3164531443
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1528139642
Short name T404
Test name
Test status
Simulation time 13140721 ps
CPU time 0.79 seconds
Started Mar 12 01:12:06 PM PDT 24
Finished Mar 12 01:12:07 PM PDT 24
Peak memory 205928 kb
Host smart-5459fd86-f2d3-4662-bae3-86b83bde705a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528139642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1528139642
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.33300927
Short name T501
Test name
Test status
Simulation time 92566481 ps
CPU time 0.72 seconds
Started Mar 12 03:09:09 PM PDT 24
Finished Mar 12 03:09:10 PM PDT 24
Peak memory 204908 kb
Host smart-c1a9fbea-2752-4a65-b7f7-4d22a78bf102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33300927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.33300927
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.1290666475
Short name T1182
Test name
Test status
Simulation time 9666592514 ps
CPU time 42.56 seconds
Started Mar 12 03:09:09 PM PDT 24
Finished Mar 12 03:09:52 PM PDT 24
Peak memory 232504 kb
Host smart-44741954-a57a-4b8e-8a5d-e844cbec3815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290666475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.1290666475
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2549447467
Short name T1680
Test name
Test status
Simulation time 316271051816 ps
CPU time 249.76 seconds
Started Mar 12 01:12:15 PM PDT 24
Finished Mar 12 01:16:25 PM PDT 24
Peak memory 248208 kb
Host smart-586a6167-9307-4ef9-a5b6-04171559f550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549447467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2549447467
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2432806998
Short name T756
Test name
Test status
Simulation time 10768518382 ps
CPU time 114 seconds
Started Mar 12 03:09:07 PM PDT 24
Finished Mar 12 03:11:01 PM PDT 24
Peak memory 248972 kb
Host smart-e10a02bb-e2da-4312-943b-3c2e739c12a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432806998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2432806998
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.952376715
Short name T367
Test name
Test status
Simulation time 11854096796 ps
CPU time 39.03 seconds
Started Mar 12 01:12:18 PM PDT 24
Finished Mar 12 01:12:57 PM PDT 24
Peak memory 235816 kb
Host smart-e7cda755-11e5-456a-9146-8bab7037d65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952376715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.952376715
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1619674059
Short name T1373
Test name
Test status
Simulation time 17404899667 ps
CPU time 113.19 seconds
Started Mar 12 03:09:05 PM PDT 24
Finished Mar 12 03:10:58 PM PDT 24
Peak memory 272792 kb
Host smart-f26ef4e3-f322-408d-9b86-55d170f2d4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619674059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1619674059
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3765503662
Short name T1548
Test name
Test status
Simulation time 39539616648 ps
CPU time 266.92 seconds
Started Mar 12 01:12:15 PM PDT 24
Finished Mar 12 01:16:42 PM PDT 24
Peak memory 239556 kb
Host smart-29ee1d47-4d3d-4c8f-8102-bd706b575c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765503662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3765503662
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3729898850
Short name T435
Test name
Test status
Simulation time 466180214 ps
CPU time 9.54 seconds
Started Mar 12 03:09:05 PM PDT 24
Finished Mar 12 03:09:14 PM PDT 24
Peak memory 232744 kb
Host smart-d4abbd92-ea7c-4410-ae28-e3089701c399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729898850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3729898850
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.83854489
Short name T430
Test name
Test status
Simulation time 1194355471 ps
CPU time 7.24 seconds
Started Mar 12 01:12:14 PM PDT 24
Finished Mar 12 01:12:22 PM PDT 24
Peak memory 237400 kb
Host smart-e1880bd4-d777-4e94-a766-da045810985f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83854489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.83854489
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.195717571
Short name T620
Test name
Test status
Simulation time 1643382579 ps
CPU time 6.56 seconds
Started Mar 12 01:12:16 PM PDT 24
Finished Mar 12 01:12:22 PM PDT 24
Peak memory 235516 kb
Host smart-114f471b-ca44-4973-8397-355ecd4e7863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195717571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.195717571
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_intercept.480328024
Short name T9
Test name
Test status
Simulation time 576433970 ps
CPU time 3.83 seconds
Started Mar 12 03:09:05 PM PDT 24
Finished Mar 12 03:09:09 PM PDT 24
Peak memory 217200 kb
Host smart-973f82fb-4b1e-445f-a15f-97463002a3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480328024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.480328024
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2891487819
Short name T598
Test name
Test status
Simulation time 3943578596 ps
CPU time 13.68 seconds
Started Mar 12 03:09:06 PM PDT 24
Finished Mar 12 03:09:20 PM PDT 24
Peak memory 233284 kb
Host smart-6ccf39b5-15f6-489c-8b46-879a33397b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891487819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2891487819
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.37187404
Short name T1441
Test name
Test status
Simulation time 33949112144 ps
CPU time 46.7 seconds
Started Mar 12 01:12:17 PM PDT 24
Finished Mar 12 01:13:03 PM PDT 24
Peak memory 238236 kb
Host smart-f63423b8-2e45-4aa1-aa9e-a10dd8c0a571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37187404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.37187404
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2208582669
Short name T1559
Test name
Test status
Simulation time 588794281 ps
CPU time 6.96 seconds
Started Mar 12 03:09:07 PM PDT 24
Finished Mar 12 03:09:15 PM PDT 24
Peak memory 233252 kb
Host smart-a4114e1e-ec75-4f40-8d7a-a2977c387266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208582669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2208582669
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2759034517
Short name T222
Test name
Test status
Simulation time 7489360630 ps
CPU time 13.49 seconds
Started Mar 12 01:12:14 PM PDT 24
Finished Mar 12 01:12:28 PM PDT 24
Peak memory 218848 kb
Host smart-65cf7d38-c242-424e-886a-f1ac04fe8b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759034517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2759034517
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3265831352
Short name T1905
Test name
Test status
Simulation time 1798844417 ps
CPU time 6.96 seconds
Started Mar 12 01:12:16 PM PDT 24
Finished Mar 12 01:12:23 PM PDT 24
Peak memory 240008 kb
Host smart-7876a919-ebf0-4f4e-b2e9-a049019ecc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265831352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3265831352
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.4289668869
Short name T996
Test name
Test status
Simulation time 943576555 ps
CPU time 8.06 seconds
Started Mar 12 03:09:07 PM PDT 24
Finished Mar 12 03:09:15 PM PDT 24
Peak memory 233596 kb
Host smart-27a19079-49e9-4f75-8765-aa2ec04aaaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289668869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.4289668869
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1100500645
Short name T1195
Test name
Test status
Simulation time 1230120156 ps
CPU time 6.9 seconds
Started Mar 12 03:09:09 PM PDT 24
Finished Mar 12 03:09:16 PM PDT 24
Peak memory 222288 kb
Host smart-e06a3b78-07a2-4a5d-861e-1e66154869c9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1100500645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1100500645
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3938063778
Short name T1030
Test name
Test status
Simulation time 4572413096 ps
CPU time 5.72 seconds
Started Mar 12 01:12:16 PM PDT 24
Finished Mar 12 01:12:22 PM PDT 24
Peak memory 216292 kb
Host smart-b1ded1b2-1918-4c7a-bf52-4f87eb18433b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3938063778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3938063778
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1052021850
Short name T293
Test name
Test status
Simulation time 356602587956 ps
CPU time 674.96 seconds
Started Mar 12 03:09:08 PM PDT 24
Finished Mar 12 03:20:24 PM PDT 24
Peak memory 272808 kb
Host smart-43a5d344-07d5-428f-93aa-882318af791b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052021850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1052021850
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.607307672
Short name T1149
Test name
Test status
Simulation time 1029091516166 ps
CPU time 551.62 seconds
Started Mar 12 01:12:16 PM PDT 24
Finished Mar 12 01:21:28 PM PDT 24
Peak memory 271068 kb
Host smart-617e238a-ca1f-4403-90c9-c1c9229cde94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607307672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.607307672
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1840400822
Short name T1379
Test name
Test status
Simulation time 11518770819 ps
CPU time 35.39 seconds
Started Mar 12 03:09:05 PM PDT 24
Finished Mar 12 03:09:41 PM PDT 24
Peak memory 216100 kb
Host smart-419c4ee0-6b13-4d85-9f1a-063798a3fcae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840400822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1840400822
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2924722459
Short name T165
Test name
Test status
Simulation time 10145985364 ps
CPU time 55.54 seconds
Started Mar 12 01:12:15 PM PDT 24
Finished Mar 12 01:13:11 PM PDT 24
Peak memory 216156 kb
Host smart-b6e3bc3d-2d99-4666-9ae4-e48870f731d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924722459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2924722459
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1187116339
Short name T1253
Test name
Test status
Simulation time 1807800690 ps
CPU time 9.15 seconds
Started Mar 12 01:12:16 PM PDT 24
Finished Mar 12 01:12:25 PM PDT 24
Peak memory 215840 kb
Host smart-d76132ea-b519-4401-a0d4-06355ea35e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187116339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1187116339
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3542736972
Short name T1583
Test name
Test status
Simulation time 2898281016 ps
CPU time 8.82 seconds
Started Mar 12 03:09:11 PM PDT 24
Finished Mar 12 03:09:21 PM PDT 24
Peak memory 216096 kb
Host smart-46e3196c-ff8c-4f07-b721-a5a3641c9bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542736972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3542736972
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2712817613
Short name T172
Test name
Test status
Simulation time 247409812 ps
CPU time 1.5 seconds
Started Mar 12 01:12:18 PM PDT 24
Finished Mar 12 01:12:19 PM PDT 24
Peak memory 216012 kb
Host smart-4df792af-124e-4397-b432-7e11643bf343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712817613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2712817613
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3777056881
Short name T382
Test name
Test status
Simulation time 88124621 ps
CPU time 1.89 seconds
Started Mar 12 03:09:09 PM PDT 24
Finished Mar 12 03:09:11 PM PDT 24
Peak memory 207856 kb
Host smart-f5cdc65e-d1e9-4892-b2c5-348bbec6333d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777056881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3777056881
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2589753355
Short name T1006
Test name
Test status
Simulation time 310124685 ps
CPU time 0.77 seconds
Started Mar 12 03:09:06 PM PDT 24
Finished Mar 12 03:09:07 PM PDT 24
Peak memory 205288 kb
Host smart-6c099269-1666-471b-8738-3691caba091d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589753355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2589753355
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.719519076
Short name T1277
Test name
Test status
Simulation time 217455548 ps
CPU time 0.89 seconds
Started Mar 12 01:12:15 PM PDT 24
Finished Mar 12 01:12:16 PM PDT 24
Peak memory 205276 kb
Host smart-71c8801c-8340-45c2-bfaf-cb2fce045906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719519076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.719519076
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3298471620
Short name T671
Test name
Test status
Simulation time 9041116632 ps
CPU time 8.49 seconds
Started Mar 12 01:12:15 PM PDT 24
Finished Mar 12 01:12:23 PM PDT 24
Peak memory 237652 kb
Host smart-fff829b9-4913-4360-a453-8e019e2a1fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298471620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3298471620
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_upload.4075880519
Short name T883
Test name
Test status
Simulation time 27057004719 ps
CPU time 25.59 seconds
Started Mar 12 03:09:14 PM PDT 24
Finished Mar 12 03:09:40 PM PDT 24
Peak memory 239048 kb
Host smart-bf20f8fc-956d-4cc4-b310-ba9b8c6de3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075880519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.4075880519
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2715036821
Short name T582
Test name
Test status
Simulation time 49859521 ps
CPU time 0.72 seconds
Started Mar 12 01:12:17 PM PDT 24
Finished Mar 12 01:12:17 PM PDT 24
Peak memory 204820 kb
Host smart-bcdccfda-cc7d-4c89-99b9-2b741625acd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715036821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2715036821
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3697960773
Short name T1288
Test name
Test status
Simulation time 14488762 ps
CPU time 0.73 seconds
Started Mar 12 03:09:20 PM PDT 24
Finished Mar 12 03:09:20 PM PDT 24
Peak memory 204796 kb
Host smart-5785d865-7853-4418-ad87-d072d0642f06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697960773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3697960773
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1020622337
Short name T406
Test name
Test status
Simulation time 289807071 ps
CPU time 2.37 seconds
Started Mar 12 01:12:13 PM PDT 24
Finished Mar 12 01:12:16 PM PDT 24
Peak memory 218132 kb
Host smart-5492aa1d-bbc9-421f-b941-4b2d11b5fc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020622337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1020622337
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1875037270
Short name T1009
Test name
Test status
Simulation time 1713742463 ps
CPU time 7.45 seconds
Started Mar 12 03:09:18 PM PDT 24
Finished Mar 12 03:09:26 PM PDT 24
Peak memory 234620 kb
Host smart-e6de6bcb-623d-4cb8-8509-332bb926cbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875037270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1875037270
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3608648254
Short name T442
Test name
Test status
Simulation time 19833528 ps
CPU time 0.77 seconds
Started Mar 12 01:12:18 PM PDT 24
Finished Mar 12 01:12:19 PM PDT 24
Peak memory 205808 kb
Host smart-90cff942-271e-4b09-8597-a05280ef618c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608648254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3608648254
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3860826479
Short name T495
Test name
Test status
Simulation time 17320141 ps
CPU time 0.82 seconds
Started Mar 12 03:09:07 PM PDT 24
Finished Mar 12 03:09:08 PM PDT 24
Peak memory 205912 kb
Host smart-71fc0fe2-fbad-46b9-8d93-ba95cd2fe08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860826479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3860826479
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.395108760
Short name T304
Test name
Test status
Simulation time 39431995121 ps
CPU time 57.05 seconds
Started Mar 12 01:12:17 PM PDT 24
Finished Mar 12 01:13:14 PM PDT 24
Peak memory 249440 kb
Host smart-97f39252-e23b-4cd2-b951-18404da43c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395108760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.395108760
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1474976354
Short name T918
Test name
Test status
Simulation time 21860792961 ps
CPU time 44.2 seconds
Started Mar 12 01:12:15 PM PDT 24
Finished Mar 12 01:12:59 PM PDT 24
Peak memory 232016 kb
Host smart-ee74ca0a-ff40-44e0-80ed-c87013535073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474976354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1474976354
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.4244248147
Short name T1252
Test name
Test status
Simulation time 30507244480 ps
CPU time 95.49 seconds
Started Mar 12 03:09:20 PM PDT 24
Finished Mar 12 03:10:57 PM PDT 24
Peak memory 253876 kb
Host smart-89d80fa6-48b8-43c0-8b9b-d0d05bc2288d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244248147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.4244248147
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.2088445203
Short name T1648
Test name
Test status
Simulation time 27040669702 ps
CPU time 42.75 seconds
Started Mar 12 01:12:15 PM PDT 24
Finished Mar 12 01:12:58 PM PDT 24
Peak memory 234612 kb
Host smart-4d998cc6-6b9b-47b1-a9db-68ca4695c093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088445203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.2088445203
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.740157592
Short name T1418
Test name
Test status
Simulation time 12489363267 ps
CPU time 52.12 seconds
Started Mar 12 03:09:21 PM PDT 24
Finished Mar 12 03:10:14 PM PDT 24
Peak memory 232596 kb
Host smart-ceda7a43-258d-43eb-86cf-03beccb7fb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740157592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.740157592
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2451621106
Short name T143
Test name
Test status
Simulation time 5477577350 ps
CPU time 17.05 seconds
Started Mar 12 01:12:16 PM PDT 24
Finished Mar 12 01:12:33 PM PDT 24
Peak memory 224240 kb
Host smart-83301a04-7dd5-4b25-9220-e9b14fe4529d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451621106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2451621106
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3736497356
Short name T858
Test name
Test status
Simulation time 414695145 ps
CPU time 8.39 seconds
Started Mar 12 03:09:20 PM PDT 24
Finished Mar 12 03:09:29 PM PDT 24
Peak memory 234876 kb
Host smart-24391889-b23f-4977-8929-3eb070424ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736497356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3736497356
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1626248218
Short name T191
Test name
Test status
Simulation time 2539868533 ps
CPU time 10.16 seconds
Started Mar 12 01:12:17 PM PDT 24
Finished Mar 12 01:12:27 PM PDT 24
Peak memory 233224 kb
Host smart-9875f1d4-226a-4f65-88db-5c5350e32614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626248218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1626248218
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_intercept.599003075
Short name T655
Test name
Test status
Simulation time 3271334167 ps
CPU time 4.19 seconds
Started Mar 12 03:09:16 PM PDT 24
Finished Mar 12 03:09:21 PM PDT 24
Peak memory 233176 kb
Host smart-a2e422fd-b56b-44c4-92d1-dcdfb7d7a6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599003075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.599003075
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2900936899
Short name T1718
Test name
Test status
Simulation time 6755952200 ps
CPU time 22.51 seconds
Started Mar 12 01:12:16 PM PDT 24
Finished Mar 12 01:12:38 PM PDT 24
Peak memory 236012 kb
Host smart-6dbfa52c-c7a0-416b-bb7d-475624f2d30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900936899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2900936899
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.909734236
Short name T171
Test name
Test status
Simulation time 2196932185 ps
CPU time 13.03 seconds
Started Mar 12 03:09:15 PM PDT 24
Finished Mar 12 03:09:28 PM PDT 24
Peak memory 232372 kb
Host smart-2696ebcc-8f13-4903-bf40-e299471dc41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909734236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.909734236
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1838344204
Short name T577
Test name
Test status
Simulation time 1081073739 ps
CPU time 10.33 seconds
Started Mar 12 01:12:17 PM PDT 24
Finished Mar 12 01:12:27 PM PDT 24
Peak memory 217244 kb
Host smart-11d74137-4b45-460b-ba1e-a8f2649726d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838344204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1838344204
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.4071024728
Short name T528
Test name
Test status
Simulation time 165502109 ps
CPU time 2.59 seconds
Started Mar 12 03:09:19 PM PDT 24
Finished Mar 12 03:09:21 PM PDT 24
Peak memory 223752 kb
Host smart-011cf02e-cf80-4136-8d52-2303845232cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071024728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.4071024728
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1635965360
Short name T625
Test name
Test status
Simulation time 308469629 ps
CPU time 3.52 seconds
Started Mar 12 01:12:16 PM PDT 24
Finished Mar 12 01:12:20 PM PDT 24
Peak memory 224192 kb
Host smart-6b93f017-4ddf-441d-aca7-46a3d38de844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635965360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1635965360
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3629831195
Short name T1432
Test name
Test status
Simulation time 15467665532 ps
CPU time 19.62 seconds
Started Mar 12 03:09:19 PM PDT 24
Finished Mar 12 03:09:38 PM PDT 24
Peak memory 233352 kb
Host smart-b40433f9-ef66-4b9a-adb9-cd7b5287844b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629831195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3629831195
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1572406322
Short name T1485
Test name
Test status
Simulation time 1589731607 ps
CPU time 3.77 seconds
Started Mar 12 03:09:16 PM PDT 24
Finished Mar 12 03:09:20 PM PDT 24
Peak memory 216280 kb
Host smart-7f154fed-7ae7-4d38-bddb-137da0d2529e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1572406322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1572406322
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.492152417
Short name T988
Test name
Test status
Simulation time 13721991425 ps
CPU time 6.88 seconds
Started Mar 12 01:12:14 PM PDT 24
Finished Mar 12 01:12:21 PM PDT 24
Peak memory 221964 kb
Host smart-cce8de88-6484-496d-a4e2-ffa221b8b7fa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=492152417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.492152417
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1803668789
Short name T1118
Test name
Test status
Simulation time 60372519093 ps
CPU time 461.11 seconds
Started Mar 12 03:09:17 PM PDT 24
Finished Mar 12 03:16:58 PM PDT 24
Peak memory 265376 kb
Host smart-0dd115b2-d3c4-4a06-9329-537d044dfc9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803668789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1803668789
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3876182535
Short name T392
Test name
Test status
Simulation time 57037022 ps
CPU time 0.89 seconds
Started Mar 12 01:12:18 PM PDT 24
Finished Mar 12 01:12:19 PM PDT 24
Peak memory 205000 kb
Host smart-ab681fd5-3aa8-4495-8c1c-03d3009ed6a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876182535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3876182535
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1693506514
Short name T734
Test name
Test status
Simulation time 431428142 ps
CPU time 2.23 seconds
Started Mar 12 01:12:17 PM PDT 24
Finished Mar 12 01:12:20 PM PDT 24
Peak memory 216108 kb
Host smart-71f73538-7715-4801-98d4-929a6d4d398c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693506514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1693506514
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2462678424
Short name T1577
Test name
Test status
Simulation time 7120702575 ps
CPU time 23.44 seconds
Started Mar 12 03:09:06 PM PDT 24
Finished Mar 12 03:09:30 PM PDT 24
Peak memory 216136 kb
Host smart-ce391527-0f29-466d-839a-58fc7ccb6bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462678424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2462678424
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1400670289
Short name T1161
Test name
Test status
Simulation time 4838606211 ps
CPU time 17.47 seconds
Started Mar 12 03:09:12 PM PDT 24
Finished Mar 12 03:09:29 PM PDT 24
Peak memory 216756 kb
Host smart-dea8362e-90f4-4965-a73a-d4e9b9d18ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400670289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1400670289
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1733144342
Short name T1521
Test name
Test status
Simulation time 3727237961 ps
CPU time 5.1 seconds
Started Mar 12 01:12:16 PM PDT 24
Finished Mar 12 01:12:21 PM PDT 24
Peak memory 216120 kb
Host smart-6e531858-5731-443a-aa0d-4516ea38cff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733144342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1733144342
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3785419416
Short name T600
Test name
Test status
Simulation time 280131455 ps
CPU time 3 seconds
Started Mar 12 01:12:17 PM PDT 24
Finished Mar 12 01:12:20 PM PDT 24
Peak memory 216212 kb
Host smart-37fca2db-a8a2-4c79-8629-49b433ae64d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785419416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3785419416
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3840529042
Short name T416
Test name
Test status
Simulation time 2498401104 ps
CPU time 9.74 seconds
Started Mar 12 03:09:20 PM PDT 24
Finished Mar 12 03:09:31 PM PDT 24
Peak memory 217312 kb
Host smart-6d2d8b32-f068-4a38-adf7-fbb76a72ca62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840529042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3840529042
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.112237832
Short name T774
Test name
Test status
Simulation time 2297272030 ps
CPU time 1.11 seconds
Started Mar 12 01:12:17 PM PDT 24
Finished Mar 12 01:12:18 PM PDT 24
Peak memory 206308 kb
Host smart-437f5cc0-496b-44d4-848b-a2b6d4cd6419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112237832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.112237832
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.21234828
Short name T87
Test name
Test status
Simulation time 109491935 ps
CPU time 0.79 seconds
Started Mar 12 03:09:18 PM PDT 24
Finished Mar 12 03:09:19 PM PDT 24
Peak memory 205280 kb
Host smart-06b4b202-e976-41df-854b-2f4f9a18c477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21234828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.21234828
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.4068480049
Short name T206
Test name
Test status
Simulation time 301584259 ps
CPU time 5.65 seconds
Started Mar 12 03:09:21 PM PDT 24
Finished Mar 12 03:09:27 PM PDT 24
Peak memory 233480 kb
Host smart-8a103121-edce-401f-874e-e11a4aa18da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068480049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.4068480049
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_upload.920027292
Short name T196
Test name
Test status
Simulation time 10755139165 ps
CPU time 14.31 seconds
Started Mar 12 01:12:17 PM PDT 24
Finished Mar 12 01:12:31 PM PDT 24
Peak memory 248848 kb
Host smart-9af933f1-297c-45b4-8025-68c6e1ecf2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920027292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.920027292
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2959476340
Short name T605
Test name
Test status
Simulation time 61512606 ps
CPU time 0.69 seconds
Started Mar 12 01:12:14 PM PDT 24
Finished Mar 12 01:12:15 PM PDT 24
Peak memory 204828 kb
Host smart-5d946b0e-37b9-49cd-9f81-795fb3dfaca3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959476340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2959476340
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.659453401
Short name T326
Test name
Test status
Simulation time 13545759 ps
CPU time 0.71 seconds
Started Mar 12 03:09:19 PM PDT 24
Finished Mar 12 03:09:19 PM PDT 24
Peak memory 204792 kb
Host smart-b16e279c-3ba3-4f47-8d64-d1195757989c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659453401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.659453401
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.333800343
Short name T1189
Test name
Test status
Simulation time 100053797 ps
CPU time 2.27 seconds
Started Mar 12 01:12:16 PM PDT 24
Finished Mar 12 01:12:19 PM PDT 24
Peak memory 216072 kb
Host smart-a34d1f63-e96e-4df9-8118-8136764401dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333800343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.333800343
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.4020549623
Short name T1699
Test name
Test status
Simulation time 1545840084 ps
CPU time 3.59 seconds
Started Mar 12 03:09:20 PM PDT 24
Finished Mar 12 03:09:25 PM PDT 24
Peak memory 219028 kb
Host smart-d11aa449-871e-4de2-83f5-8b666f396fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020549623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.4020549623
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2015203631
Short name T1862
Test name
Test status
Simulation time 38880493 ps
CPU time 0.72 seconds
Started Mar 12 01:12:14 PM PDT 24
Finished Mar 12 01:12:14 PM PDT 24
Peak memory 204888 kb
Host smart-346256d8-c6d8-4988-88f4-9c3b66d09079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015203631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2015203631
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.4110047125
Short name T1607
Test name
Test status
Simulation time 41307694 ps
CPU time 0.76 seconds
Started Mar 12 03:09:21 PM PDT 24
Finished Mar 12 03:09:22 PM PDT 24
Peak memory 204912 kb
Host smart-77012fe2-b2b4-4f93-b6e2-cbf1ee2ce8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110047125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.4110047125
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3533114160
Short name T609
Test name
Test status
Simulation time 14814797190 ps
CPU time 107.58 seconds
Started Mar 12 03:09:29 PM PDT 24
Finished Mar 12 03:11:17 PM PDT 24
Peak memory 249244 kb
Host smart-d1c78965-6596-425e-93a7-e1fe35b49735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533114160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3533114160
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3771501941
Short name T1204
Test name
Test status
Simulation time 16435392288 ps
CPU time 53.69 seconds
Started Mar 12 01:12:14 PM PDT 24
Finished Mar 12 01:13:08 PM PDT 24
Peak memory 248868 kb
Host smart-0f04946c-5390-412e-ab84-837e7dba9a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771501941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3771501941
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1291316819
Short name T1156
Test name
Test status
Simulation time 14717981091 ps
CPU time 125.14 seconds
Started Mar 12 03:09:19 PM PDT 24
Finished Mar 12 03:11:25 PM PDT 24
Peak memory 265388 kb
Host smart-aa8132b5-cb6d-4cdd-b4f6-25106c2a91f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291316819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1291316819
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.4227697563
Short name T975
Test name
Test status
Simulation time 10011502322 ps
CPU time 108.22 seconds
Started Mar 12 01:12:17 PM PDT 24
Finished Mar 12 01:14:06 PM PDT 24
Peak memory 256440 kb
Host smart-5cc762a8-5e4e-4175-a0de-9fa935c3073d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227697563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.4227697563
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.950542051
Short name T1478
Test name
Test status
Simulation time 2667317544 ps
CPU time 41.78 seconds
Started Mar 12 01:12:19 PM PDT 24
Finished Mar 12 01:13:01 PM PDT 24
Peak memory 221700 kb
Host smart-d9a424a0-88df-4033-8327-d7166fc61e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950542051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle
.950542051
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.240396742
Short name T1627
Test name
Test status
Simulation time 715076851 ps
CPU time 9.95 seconds
Started Mar 12 03:09:16 PM PDT 24
Finished Mar 12 03:09:26 PM PDT 24
Peak memory 240560 kb
Host smart-121b5d04-60a2-43c4-8056-cf557abf0d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240396742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.240396742
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3248495372
Short name T1614
Test name
Test status
Simulation time 415664767 ps
CPU time 10.67 seconds
Started Mar 12 01:12:15 PM PDT 24
Finished Mar 12 01:12:26 PM PDT 24
Peak memory 248020 kb
Host smart-345bae1f-f597-4654-8cd9-661e398a0a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248495372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3248495372
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.281536793
Short name T759
Test name
Test status
Simulation time 415144802 ps
CPU time 2.72 seconds
Started Mar 12 03:09:19 PM PDT 24
Finished Mar 12 03:09:22 PM PDT 24
Peak memory 224052 kb
Host smart-9286ab76-9c93-4537-a6f4-cd4778329c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281536793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.281536793
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_intercept.4185573328
Short name T896
Test name
Test status
Simulation time 237784420 ps
CPU time 3.78 seconds
Started Mar 12 01:12:16 PM PDT 24
Finished Mar 12 01:12:20 PM PDT 24
Peak memory 218672 kb
Host smart-28aaa8c6-9376-416f-95f9-6609b4327a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185573328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.4185573328
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2096129008
Short name T1729
Test name
Test status
Simulation time 8937618052 ps
CPU time 17 seconds
Started Mar 12 01:12:13 PM PDT 24
Finished Mar 12 01:12:30 PM PDT 24
Peak memory 236288 kb
Host smart-29fbda7e-85dc-4071-9774-6be726e0c3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096129008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2096129008
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2320276124
Short name T592
Test name
Test status
Simulation time 1050092262 ps
CPU time 9.42 seconds
Started Mar 12 03:09:19 PM PDT 24
Finished Mar 12 03:09:29 PM PDT 24
Peak memory 233412 kb
Host smart-4056d8c5-0389-48b7-97ba-74ec3101ff05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320276124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2320276124
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2108929625
Short name T399
Test name
Test status
Simulation time 39827940741 ps
CPU time 51.85 seconds
Started Mar 12 01:12:17 PM PDT 24
Finished Mar 12 01:13:09 PM PDT 24
Peak memory 228060 kb
Host smart-f750b2a1-6566-4a34-beba-650b7a6abadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108929625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2108929625
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3735025601
Short name T289
Test name
Test status
Simulation time 16577965521 ps
CPU time 23.11 seconds
Started Mar 12 03:09:16 PM PDT 24
Finished Mar 12 03:09:39 PM PDT 24
Peak memory 234736 kb
Host smart-5070b56a-3015-4459-9a5e-b27a7417f108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735025601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3735025601
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3192430738
Short name T785
Test name
Test status
Simulation time 4471064382 ps
CPU time 15.08 seconds
Started Mar 12 03:09:24 PM PDT 24
Finished Mar 12 03:09:40 PM PDT 24
Peak memory 217132 kb
Host smart-8bc3508d-f77a-4e3b-97e1-230657b5d19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192430738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3192430738
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3785459427
Short name T1865
Test name
Test status
Simulation time 7757475185 ps
CPU time 14.6 seconds
Started Mar 12 01:12:14 PM PDT 24
Finished Mar 12 01:12:29 PM PDT 24
Peak memory 239352 kb
Host smart-f746b390-003b-466a-824e-bf46d4aeb137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785459427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3785459427
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1958184469
Short name T1183
Test name
Test status
Simulation time 4522823333 ps
CPU time 5.29 seconds
Started Mar 12 01:12:17 PM PDT 24
Finished Mar 12 01:12:22 PM PDT 24
Peak memory 218796 kb
Host smart-c6c01a6b-0069-4038-b2b0-8ccbd97bff5d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1958184469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1958184469
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.4062338206
Short name T1224
Test name
Test status
Simulation time 1433627218 ps
CPU time 6.56 seconds
Started Mar 12 03:09:17 PM PDT 24
Finished Mar 12 03:09:23 PM PDT 24
Peak memory 222412 kb
Host smart-a48be4e9-4b96-4ad8-8947-74de49890f31
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4062338206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.4062338206
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2705248534
Short name T83
Test name
Test status
Simulation time 13553997629 ps
CPU time 145.31 seconds
Started Mar 12 01:12:16 PM PDT 24
Finished Mar 12 01:14:42 PM PDT 24
Peak memory 248936 kb
Host smart-76312396-9c66-4d90-93a2-16a2253bd71a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705248534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2705248534
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.4084420627
Short name T1850
Test name
Test status
Simulation time 187680679696 ps
CPU time 359.39 seconds
Started Mar 12 03:09:19 PM PDT 24
Finished Mar 12 03:15:19 PM PDT 24
Peak memory 265356 kb
Host smart-d0f2ad8a-fde5-4820-9a96-c32af63c9d22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084420627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.4084420627
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1545963200
Short name T1565
Test name
Test status
Simulation time 1689013713 ps
CPU time 9.62 seconds
Started Mar 12 01:12:13 PM PDT 24
Finished Mar 12 01:12:23 PM PDT 24
Peak memory 216056 kb
Host smart-d9b58cbc-1cf5-4835-a79a-b1cc1dcd8a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545963200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1545963200
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2851509205
Short name T315
Test name
Test status
Simulation time 488923527 ps
CPU time 9.39 seconds
Started Mar 12 03:09:19 PM PDT 24
Finished Mar 12 03:09:29 PM PDT 24
Peak memory 216064 kb
Host smart-537ec08f-beda-4f28-8fbd-defaf9628b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851509205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2851509205
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2764027443
Short name T650
Test name
Test status
Simulation time 871739686 ps
CPU time 3.85 seconds
Started Mar 12 03:09:17 PM PDT 24
Finished Mar 12 03:09:21 PM PDT 24
Peak memory 216096 kb
Host smart-0e40f8de-198d-4e90-8756-5769e3b60445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764027443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2764027443
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3698516457
Short name T789
Test name
Test status
Simulation time 5015080585 ps
CPU time 7.41 seconds
Started Mar 12 01:12:15 PM PDT 24
Finished Mar 12 01:12:23 PM PDT 24
Peak memory 216252 kb
Host smart-f61770c5-2dc2-4f00-9f69-750929120b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698516457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3698516457
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2158569350
Short name T1025
Test name
Test status
Simulation time 1016580275 ps
CPU time 2.41 seconds
Started Mar 12 01:12:16 PM PDT 24
Finished Mar 12 01:12:19 PM PDT 24
Peak memory 216232 kb
Host smart-37455690-cec6-49c9-832d-08aa3123a07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158569350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2158569350
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2528110538
Short name T1715
Test name
Test status
Simulation time 49899351 ps
CPU time 0.91 seconds
Started Mar 12 03:09:19 PM PDT 24
Finished Mar 12 03:09:20 PM PDT 24
Peak memory 206388 kb
Host smart-89fcfca7-1b04-4b7e-9fee-d0cf127722cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528110538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2528110538
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.24042809
Short name T444
Test name
Test status
Simulation time 26923274 ps
CPU time 0.74 seconds
Started Mar 12 03:09:20 PM PDT 24
Finished Mar 12 03:09:22 PM PDT 24
Peak memory 205232 kb
Host smart-9bed37e8-f3b4-4aa5-b54c-6d1d2a4edc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24042809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.24042809
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.395457371
Short name T1347
Test name
Test status
Simulation time 42604844 ps
CPU time 0.81 seconds
Started Mar 12 01:12:17 PM PDT 24
Finished Mar 12 01:12:18 PM PDT 24
Peak memory 205216 kb
Host smart-82e0584b-0eb5-405f-9d60-4a7e1adb6fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395457371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.395457371
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.4032499734
Short name T1084
Test name
Test status
Simulation time 2931866363 ps
CPU time 12.49 seconds
Started Mar 12 03:09:18 PM PDT 24
Finished Mar 12 03:09:30 PM PDT 24
Peak memory 218348 kb
Host smart-588d82ca-c83e-44e6-b1fe-8b8b94224df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032499734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.4032499734
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_upload.955012059
Short name T1733
Test name
Test status
Simulation time 585411159 ps
CPU time 5.28 seconds
Started Mar 12 01:12:42 PM PDT 24
Finished Mar 12 01:12:47 PM PDT 24
Peak memory 217396 kb
Host smart-83f4bcb7-02bd-44ba-a41a-612b72306f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955012059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.955012059
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2233321741
Short name T907
Test name
Test status
Simulation time 14851140 ps
CPU time 0.71 seconds
Started Mar 12 03:09:41 PM PDT 24
Finished Mar 12 03:09:42 PM PDT 24
Peak memory 204772 kb
Host smart-19333c77-63df-49fa-a536-49eb1663accc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233321741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2233321741
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.915284262
Short name T810
Test name
Test status
Simulation time 22026701 ps
CPU time 0.66 seconds
Started Mar 12 01:12:31 PM PDT 24
Finished Mar 12 01:12:32 PM PDT 24
Peak memory 204736 kb
Host smart-7fd28180-781b-4d94-a82d-2b4960f3e135
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915284262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.915284262
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1546165501
Short name T1704
Test name
Test status
Simulation time 237167610 ps
CPU time 2.87 seconds
Started Mar 12 01:12:25 PM PDT 24
Finished Mar 12 01:12:28 PM PDT 24
Peak memory 216284 kb
Host smart-9b4d600f-f466-4d15-9cef-e017286d203c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546165501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1546165501
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.29985389
Short name T12
Test name
Test status
Simulation time 822645451 ps
CPU time 4.47 seconds
Started Mar 12 03:09:41 PM PDT 24
Finished Mar 12 03:09:46 PM PDT 24
Peak memory 224180 kb
Host smart-e52bf8c7-32c8-4266-b68d-4dc1155f5487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29985389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.29985389
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1857616877
Short name T494
Test name
Test status
Simulation time 15228111 ps
CPU time 0.78 seconds
Started Mar 12 03:09:19 PM PDT 24
Finished Mar 12 03:09:20 PM PDT 24
Peak memory 205940 kb
Host smart-32cee1bf-4e6e-4e1d-b579-3db4a1d6e947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857616877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1857616877
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.455707541
Short name T698
Test name
Test status
Simulation time 51626218 ps
CPU time 0.75 seconds
Started Mar 12 01:12:18 PM PDT 24
Finished Mar 12 01:12:19 PM PDT 24
Peak memory 205932 kb
Host smart-6d2ff5bf-4ac8-4b10-823c-57dbd08a9d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455707541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.455707541
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1577420343
Short name T1338
Test name
Test status
Simulation time 5961462429 ps
CPU time 46.42 seconds
Started Mar 12 03:09:42 PM PDT 24
Finished Mar 12 03:10:28 PM PDT 24
Peak memory 257012 kb
Host smart-ac0de2b7-0a95-4c4c-9351-09f6e2b85b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577420343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1577420343
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.878442033
Short name T296
Test name
Test status
Simulation time 83520697533 ps
CPU time 419.58 seconds
Started Mar 12 01:12:25 PM PDT 24
Finished Mar 12 01:19:25 PM PDT 24
Peak memory 258468 kb
Host smart-01c06727-d763-415f-b46d-564fe048a651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878442033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.878442033
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1363307534
Short name T1384
Test name
Test status
Simulation time 16010662876 ps
CPU time 89.39 seconds
Started Mar 12 03:09:40 PM PDT 24
Finished Mar 12 03:11:10 PM PDT 24
Peak memory 251096 kb
Host smart-75a2880e-73c5-4e49-87a8-bd1ea903cdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363307534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1363307534
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1584122244
Short name T24
Test name
Test status
Simulation time 42730593819 ps
CPU time 129.22 seconds
Started Mar 12 01:12:31 PM PDT 24
Finished Mar 12 01:14:41 PM PDT 24
Peak memory 237852 kb
Host smart-d789fd77-c21a-4c35-a4da-e5aa2654f59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584122244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1584122244
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1492512710
Short name T1015
Test name
Test status
Simulation time 5257533506 ps
CPU time 40.56 seconds
Started Mar 12 01:12:24 PM PDT 24
Finished Mar 12 01:13:05 PM PDT 24
Peak memory 224416 kb
Host smart-c0093cb1-2145-4d8d-b432-67bdde691e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492512710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1492512710
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1629672736
Short name T1933
Test name
Test status
Simulation time 2108577280 ps
CPU time 40.03 seconds
Started Mar 12 03:09:38 PM PDT 24
Finished Mar 12 03:10:19 PM PDT 24
Peak memory 253092 kb
Host smart-3ba11f26-91ef-489d-9513-4ac7ed256fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629672736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1629672736
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3686765411
Short name T673
Test name
Test status
Simulation time 4872512222 ps
CPU time 32.07 seconds
Started Mar 12 03:09:40 PM PDT 24
Finished Mar 12 03:10:12 PM PDT 24
Peak memory 248212 kb
Host smart-8ddeead1-7ae7-4669-8384-ee8bc1fb11b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686765411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3686765411
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3369751629
Short name T700
Test name
Test status
Simulation time 159974210 ps
CPU time 4.06 seconds
Started Mar 12 03:09:42 PM PDT 24
Finished Mar 12 03:09:47 PM PDT 24
Peak memory 233068 kb
Host smart-09ef219a-8462-4543-bf96-7c8dd44b2bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369751629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3369751629
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_intercept.4123783969
Short name T615
Test name
Test status
Simulation time 892105505 ps
CPU time 5.49 seconds
Started Mar 12 01:12:25 PM PDT 24
Finished Mar 12 01:12:30 PM PDT 24
Peak memory 234364 kb
Host smart-5bbbcf51-5a10-4fcc-becb-cf8d69f43866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123783969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.4123783969
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3745016141
Short name T1569
Test name
Test status
Simulation time 5368006386 ps
CPU time 16.98 seconds
Started Mar 12 03:09:40 PM PDT 24
Finished Mar 12 03:09:57 PM PDT 24
Peak memory 232464 kb
Host smart-0dffcf63-b40a-4c15-a990-d05053ddc1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745016141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3745016141
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3893312424
Short name T1659
Test name
Test status
Simulation time 1349637004 ps
CPU time 5.35 seconds
Started Mar 12 01:12:27 PM PDT 24
Finished Mar 12 01:12:33 PM PDT 24
Peak memory 222968 kb
Host smart-9bb23b23-8ac9-4120-9208-b4bf3d4a0940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893312424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3893312424
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3151025039
Short name T258
Test name
Test status
Simulation time 11054971963 ps
CPU time 25.91 seconds
Started Mar 12 03:09:40 PM PDT 24
Finished Mar 12 03:10:06 PM PDT 24
Peak memory 231864 kb
Host smart-8b929fc3-94a9-4399-b82d-d44c0f9a9feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151025039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3151025039
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.978974998
Short name T295
Test name
Test status
Simulation time 8644914269 ps
CPU time 6.42 seconds
Started Mar 12 01:12:26 PM PDT 24
Finished Mar 12 01:12:32 PM PDT 24
Peak memory 216348 kb
Host smart-ce4b4def-38ef-47e1-8bad-f99176d83863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978974998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.978974998
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2167911955
Short name T576
Test name
Test status
Simulation time 772989725 ps
CPU time 6.64 seconds
Started Mar 12 03:09:44 PM PDT 24
Finished Mar 12 03:09:51 PM PDT 24
Peak memory 233012 kb
Host smart-66c5503b-6c3b-4487-b849-42c14a98e873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167911955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2167911955
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2872477491
Short name T856
Test name
Test status
Simulation time 370343100 ps
CPU time 4.03 seconds
Started Mar 12 01:12:25 PM PDT 24
Finished Mar 12 01:12:29 PM PDT 24
Peak memory 233316 kb
Host smart-44f4df3d-7c8f-4bbe-ad04-f7bd5cfeb99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872477491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2872477491
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3816499850
Short name T901
Test name
Test status
Simulation time 1699326790 ps
CPU time 7.06 seconds
Started Mar 12 01:12:31 PM PDT 24
Finished Mar 12 01:12:38 PM PDT 24
Peak memory 219572 kb
Host smart-f7273d52-01e9-4a81-bd5a-76b41795144f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3816499850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3816499850
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.837365086
Short name T1072
Test name
Test status
Simulation time 3694309960 ps
CPU time 3.83 seconds
Started Mar 12 03:09:41 PM PDT 24
Finished Mar 12 03:09:45 PM PDT 24
Peak memory 218160 kb
Host smart-2cc3b9ff-8f87-421c-be67-34afc6b71ccd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=837365086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.837365086
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.304592587
Short name T723
Test name
Test status
Simulation time 423329020151 ps
CPU time 460.08 seconds
Started Mar 12 03:09:38 PM PDT 24
Finished Mar 12 03:17:19 PM PDT 24
Peak memory 266404 kb
Host smart-2c28542e-9817-4f6a-badb-788ac7a4dc4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304592587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stres
s_all.304592587
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3679023887
Short name T1153
Test name
Test status
Simulation time 123282476953 ps
CPU time 128.67 seconds
Started Mar 12 01:12:31 PM PDT 24
Finished Mar 12 01:14:40 PM PDT 24
Peak memory 280916 kb
Host smart-d0eccc80-3101-4f99-a724-d91aa666a251
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679023887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3679023887
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.231395125
Short name T1008
Test name
Test status
Simulation time 3612231207 ps
CPU time 28.39 seconds
Started Mar 12 03:09:18 PM PDT 24
Finished Mar 12 03:09:46 PM PDT 24
Peak memory 216136 kb
Host smart-b5ca31f1-d1e1-4bb6-b916-2a30d4a64505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231395125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.231395125
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.584961062
Short name T1594
Test name
Test status
Simulation time 6183282539 ps
CPU time 8.83 seconds
Started Mar 12 01:12:26 PM PDT 24
Finished Mar 12 01:12:35 PM PDT 24
Peak memory 216088 kb
Host smart-88861b09-c328-466a-a878-9e39c1f4461f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584961062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.584961062
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1183369489
Short name T675
Test name
Test status
Simulation time 7593472773 ps
CPU time 21.38 seconds
Started Mar 12 03:09:25 PM PDT 24
Finished Mar 12 03:09:46 PM PDT 24
Peak memory 216456 kb
Host smart-65290994-2c8c-4606-a3de-2988cccb7043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183369489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1183369489
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3964301876
Short name T718
Test name
Test status
Simulation time 4230869459 ps
CPU time 17.97 seconds
Started Mar 12 01:12:27 PM PDT 24
Finished Mar 12 01:12:45 PM PDT 24
Peak memory 216108 kb
Host smart-6f228f08-9911-4cf0-98dc-b95ec658891f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964301876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3964301876
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1497180338
Short name T1091
Test name
Test status
Simulation time 100683586 ps
CPU time 2.5 seconds
Started Mar 12 01:12:27 PM PDT 24
Finished Mar 12 01:12:30 PM PDT 24
Peak memory 216268 kb
Host smart-1ef35d05-5528-4e5c-b78f-7dfce823c46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497180338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1497180338
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3149539041
Short name T833
Test name
Test status
Simulation time 36769226 ps
CPU time 1.45 seconds
Started Mar 12 03:09:24 PM PDT 24
Finished Mar 12 03:09:25 PM PDT 24
Peak memory 216400 kb
Host smart-a01b118c-95b7-4f15-a07e-683ec06fff20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149539041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3149539041
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1914648480
Short name T1088
Test name
Test status
Simulation time 84369299 ps
CPU time 0.85 seconds
Started Mar 12 01:12:29 PM PDT 24
Finished Mar 12 01:12:30 PM PDT 24
Peak memory 205228 kb
Host smart-b8e3c693-328c-4e64-bc1d-e86fed0d53a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914648480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1914648480
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3485726529
Short name T740
Test name
Test status
Simulation time 136233069 ps
CPU time 0.96 seconds
Started Mar 12 03:09:21 PM PDT 24
Finished Mar 12 03:09:22 PM PDT 24
Peak memory 206264 kb
Host smart-f61c3dfd-ac16-4b11-b7cb-2a3fd3ba3380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485726529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3485726529
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2388407382
Short name T932
Test name
Test status
Simulation time 195103016 ps
CPU time 2.23 seconds
Started Mar 12 01:12:31 PM PDT 24
Finished Mar 12 01:12:33 PM PDT 24
Peak memory 216040 kb
Host smart-4a14b969-d4e4-409b-924a-b4978ea2277c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388407382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2388407382
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_upload.993418214
Short name T983
Test name
Test status
Simulation time 38586942827 ps
CPU time 32.36 seconds
Started Mar 12 03:09:47 PM PDT 24
Finished Mar 12 03:10:20 PM PDT 24
Peak memory 219284 kb
Host smart-7f238695-973c-4fee-b8e5-1001e0a8d092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993418214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.993418214
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3141920317
Short name T359
Test name
Test status
Simulation time 49045769 ps
CPU time 0.75 seconds
Started Mar 12 01:12:27 PM PDT 24
Finished Mar 12 01:12:28 PM PDT 24
Peak memory 204796 kb
Host smart-9d6f5489-e4b4-40bd-8e46-8a826b3d56e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141920317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3141920317
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.637442757
Short name T1705
Test name
Test status
Simulation time 36945285 ps
CPU time 0.69 seconds
Started Mar 12 03:09:41 PM PDT 24
Finished Mar 12 03:09:41 PM PDT 24
Peak memory 204780 kb
Host smart-6f19f639-f28c-413b-a849-3ace457ae897
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637442757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.637442757
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1626198241
Short name T1523
Test name
Test status
Simulation time 865503373 ps
CPU time 2.49 seconds
Started Mar 12 01:12:24 PM PDT 24
Finished Mar 12 01:12:27 PM PDT 24
Peak memory 216524 kb
Host smart-aac2ed18-0499-45e3-996b-85fbd5816b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626198241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1626198241
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.407786977
Short name T943
Test name
Test status
Simulation time 2328136768 ps
CPU time 8.4 seconds
Started Mar 12 03:09:40 PM PDT 24
Finished Mar 12 03:09:49 PM PDT 24
Peak memory 224204 kb
Host smart-06e519ce-d6b8-4bc1-97b5-b1eacf78308a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407786977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.407786977
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2045112025
Short name T329
Test name
Test status
Simulation time 139479708 ps
CPU time 0.74 seconds
Started Mar 12 01:12:28 PM PDT 24
Finished Mar 12 01:12:29 PM PDT 24
Peak memory 204884 kb
Host smart-3ac5870c-adf5-4aa4-89f3-22f42d292ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045112025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2045112025
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.740453436
Short name T910
Test name
Test status
Simulation time 91200259 ps
CPU time 0.78 seconds
Started Mar 12 03:09:38 PM PDT 24
Finished Mar 12 03:09:40 PM PDT 24
Peak memory 205952 kb
Host smart-0992ee55-63dc-441a-a4d6-a1b1c101bdab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740453436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.740453436
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1846939463
Short name T978
Test name
Test status
Simulation time 37099325341 ps
CPU time 185.71 seconds
Started Mar 12 03:09:41 PM PDT 24
Finished Mar 12 03:12:47 PM PDT 24
Peak memory 248824 kb
Host smart-bd52e906-0444-4b88-b2d7-1a13dd6532a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846939463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1846939463
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.377487831
Short name T11
Test name
Test status
Simulation time 15476033264 ps
CPU time 86.89 seconds
Started Mar 12 01:12:25 PM PDT 24
Finished Mar 12 01:13:52 PM PDT 24
Peak memory 254300 kb
Host smart-5ab14a06-44a4-4807-8560-4ce137fcae42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377487831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.377487831
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1129157037
Short name T813
Test name
Test status
Simulation time 18145266071 ps
CPU time 74.82 seconds
Started Mar 12 01:12:26 PM PDT 24
Finished Mar 12 01:13:47 PM PDT 24
Peak memory 239264 kb
Host smart-f2a5e7a7-4f0a-4231-ad6f-d48ab8c2a6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129157037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1129157037
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1907404046
Short name T136
Test name
Test status
Simulation time 6868581875 ps
CPU time 52.16 seconds
Started Mar 12 03:09:41 PM PDT 24
Finished Mar 12 03:10:33 PM PDT 24
Peak memory 251728 kb
Host smart-178f45d3-e277-4cde-bd85-b8dd6e87a2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907404046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1907404046
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2141354545
Short name T319
Test name
Test status
Simulation time 8612682235 ps
CPU time 59.58 seconds
Started Mar 12 01:12:31 PM PDT 24
Finished Mar 12 01:13:31 PM PDT 24
Peak memory 232680 kb
Host smart-dfec6435-ff79-452f-aaa9-910fc077e599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141354545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2141354545
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2720916055
Short name T1075
Test name
Test status
Simulation time 382016762054 ps
CPU time 359.53 seconds
Started Mar 12 03:09:41 PM PDT 24
Finished Mar 12 03:15:41 PM PDT 24
Peak memory 252108 kb
Host smart-a9f92dfc-471c-4123-8d49-bce0e069e7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720916055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2720916055
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2195819713
Short name T804
Test name
Test status
Simulation time 1897739254 ps
CPU time 26.03 seconds
Started Mar 12 01:12:26 PM PDT 24
Finished Mar 12 01:12:53 PM PDT 24
Peak memory 232600 kb
Host smart-e0817b5e-0567-4fac-9825-47fd3a644f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195819713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2195819713
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.579611109
Short name T913
Test name
Test status
Simulation time 10986023501 ps
CPU time 30.77 seconds
Started Mar 12 03:09:42 PM PDT 24
Finished Mar 12 03:10:13 PM PDT 24
Peak memory 232464 kb
Host smart-704aea15-09c4-49ac-8411-23bff48845fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579611109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.579611109
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1755764521
Short name T1082
Test name
Test status
Simulation time 300276593 ps
CPU time 3.53 seconds
Started Mar 12 03:09:37 PM PDT 24
Finished Mar 12 03:09:40 PM PDT 24
Peak memory 217620 kb
Host smart-648b6dc4-a5a8-4653-bf8c-d136802aa8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755764521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1755764521
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3144133152
Short name T203
Test name
Test status
Simulation time 464066110 ps
CPU time 4.65 seconds
Started Mar 12 01:12:33 PM PDT 24
Finished Mar 12 01:12:38 PM PDT 24
Peak memory 217668 kb
Host smart-f005601a-74c0-4ed9-a175-3276fe71f96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144133152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3144133152
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.2153983008
Short name T248
Test name
Test status
Simulation time 1207265962 ps
CPU time 5.78 seconds
Started Mar 12 03:09:41 PM PDT 24
Finished Mar 12 03:09:47 PM PDT 24
Peak memory 224180 kb
Host smart-61d78578-c370-4b72-940a-a5f2ee5c153d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153983008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2153983008
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3174153450
Short name T743
Test name
Test status
Simulation time 75822300903 ps
CPU time 45.68 seconds
Started Mar 12 01:12:33 PM PDT 24
Finished Mar 12 01:13:19 PM PDT 24
Peak memory 250120 kb
Host smart-05bcf887-fd15-41d5-a11b-c44d0ffd38d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174153450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3174153450
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3585661719
Short name T1005
Test name
Test status
Simulation time 42787272415 ps
CPU time 11.26 seconds
Started Mar 12 03:09:40 PM PDT 24
Finished Mar 12 03:09:52 PM PDT 24
Peak memory 232988 kb
Host smart-5e876c36-009f-4a3e-9ed1-5d9bfad508de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585661719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3585661719
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.690760643
Short name T1434
Test name
Test status
Simulation time 3718885519 ps
CPU time 10.57 seconds
Started Mar 12 01:12:29 PM PDT 24
Finished Mar 12 01:12:40 PM PDT 24
Peak memory 218948 kb
Host smart-0dc403da-2bd9-43fe-8445-2cedc45e76c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690760643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.690760643
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1276640053
Short name T819
Test name
Test status
Simulation time 911023729 ps
CPU time 7.27 seconds
Started Mar 12 01:12:28 PM PDT 24
Finished Mar 12 01:12:36 PM PDT 24
Peak memory 232892 kb
Host smart-0d8b5c65-8a11-4014-802a-565bdf3008b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276640053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1276640053
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3492607886
Short name T1069
Test name
Test status
Simulation time 306231408 ps
CPU time 2.88 seconds
Started Mar 12 03:09:40 PM PDT 24
Finished Mar 12 03:09:43 PM PDT 24
Peak memory 233144 kb
Host smart-6a5c5ee6-58e2-46c4-a683-bc1230e79e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492607886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3492607886
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.305630345
Short name T828
Test name
Test status
Simulation time 1222250288 ps
CPU time 6.13 seconds
Started Mar 12 03:09:42 PM PDT 24
Finished Mar 12 03:09:48 PM PDT 24
Peak memory 222324 kb
Host smart-69cd155d-f5fd-445b-9494-53893e5e0d34
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=305630345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.305630345
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3246470267
Short name T1254
Test name
Test status
Simulation time 1067892856 ps
CPU time 3.87 seconds
Started Mar 12 01:12:28 PM PDT 24
Finished Mar 12 01:12:32 PM PDT 24
Peak memory 216100 kb
Host smart-16aaded4-e01c-4238-9cac-9883607e8314
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3246470267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3246470267
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.211898615
Short name T481
Test name
Test status
Simulation time 19302167466 ps
CPU time 215.44 seconds
Started Mar 12 01:12:27 PM PDT 24
Finished Mar 12 01:16:03 PM PDT 24
Peak memory 265156 kb
Host smart-794b0870-0dcf-463c-9ead-5520bc033c15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211898615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.211898615
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3553331478
Short name T218
Test name
Test status
Simulation time 44521241653 ps
CPU time 207.45 seconds
Started Mar 12 03:09:40 PM PDT 24
Finished Mar 12 03:13:08 PM PDT 24
Peak memory 251024 kb
Host smart-c6b5a28f-67d9-4ced-b19d-4aca5cad3685
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553331478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3553331478
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1596766947
Short name T1826
Test name
Test status
Simulation time 6772597559 ps
CPU time 34.17 seconds
Started Mar 12 03:09:44 PM PDT 24
Finished Mar 12 03:10:18 PM PDT 24
Peak memory 216164 kb
Host smart-917b3396-557a-4080-9d40-909c5cddf2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596766947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1596766947
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.4238874957
Short name T976
Test name
Test status
Simulation time 1407162424 ps
CPU time 4.96 seconds
Started Mar 12 01:12:27 PM PDT 24
Finished Mar 12 01:12:32 PM PDT 24
Peak memory 215944 kb
Host smart-71fbd369-8fbd-455f-9f67-9d04b1844c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238874957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.4238874957
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.303928339
Short name T1283
Test name
Test status
Simulation time 3150445964 ps
CPU time 2.97 seconds
Started Mar 12 01:12:26 PM PDT 24
Finished Mar 12 01:12:30 PM PDT 24
Peak memory 215956 kb
Host smart-792cd1ce-cff2-4365-97c5-9eb15bccc214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303928339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.303928339
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.540519678
Short name T362
Test name
Test status
Simulation time 54071037154 ps
CPU time 37.88 seconds
Started Mar 12 03:09:40 PM PDT 24
Finished Mar 12 03:10:18 PM PDT 24
Peak memory 216128 kb
Host smart-7f75c0b8-ee4c-417e-aed6-b79d27f9161b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540519678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.540519678
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3672033664
Short name T1223
Test name
Test status
Simulation time 188941719 ps
CPU time 2.25 seconds
Started Mar 12 01:12:29 PM PDT 24
Finished Mar 12 01:12:32 PM PDT 24
Peak memory 216064 kb
Host smart-796c3bba-a55e-46e9-b746-8f0fc0b51796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672033664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3672033664
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3924408696
Short name T970
Test name
Test status
Simulation time 207726644 ps
CPU time 1.32 seconds
Started Mar 12 03:09:40 PM PDT 24
Finished Mar 12 03:09:42 PM PDT 24
Peak memory 216092 kb
Host smart-22e6e3e6-9ff8-4a11-af13-77da203ad2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924408696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3924408696
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1320442206
Short name T1227
Test name
Test status
Simulation time 142139266 ps
CPU time 0.92 seconds
Started Mar 12 03:09:41 PM PDT 24
Finished Mar 12 03:09:42 PM PDT 24
Peak memory 206292 kb
Host smart-730d7d11-7e25-49b3-9b54-fe8d546b0776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320442206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1320442206
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.525359683
Short name T1868
Test name
Test status
Simulation time 155066367 ps
CPU time 0.71 seconds
Started Mar 12 01:12:24 PM PDT 24
Finished Mar 12 01:12:25 PM PDT 24
Peak memory 205252 kb
Host smart-3c720cb4-bebf-4967-a61d-6710a64c3aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525359683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.525359683
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.259000916
Short name T418
Test name
Test status
Simulation time 688489470 ps
CPU time 5.12 seconds
Started Mar 12 01:12:28 PM PDT 24
Finished Mar 12 01:12:34 PM PDT 24
Peak memory 218216 kb
Host smart-3fb8720f-5965-4251-b409-e830adcd0841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259000916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.259000916
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_upload.338435310
Short name T729
Test name
Test status
Simulation time 605119584 ps
CPU time 8.66 seconds
Started Mar 12 03:09:39 PM PDT 24
Finished Mar 12 03:09:48 PM PDT 24
Peak memory 238252 kb
Host smart-2c9cc79d-0701-4f59-90b7-de97542eceb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338435310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.338435310
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2811195725
Short name T427
Test name
Test status
Simulation time 62967106 ps
CPU time 0.72 seconds
Started Mar 12 01:12:28 PM PDT 24
Finished Mar 12 01:12:29 PM PDT 24
Peak memory 205124 kb
Host smart-b09bf1b0-d329-49b6-a33e-2b4c47c904de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811195725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2811195725
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3433769185
Short name T445
Test name
Test status
Simulation time 11281564 ps
CPU time 0.7 seconds
Started Mar 12 03:09:57 PM PDT 24
Finished Mar 12 03:09:58 PM PDT 24
Peak memory 204828 kb
Host smart-2281c576-1f9e-4770-985b-80f5289e9fea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433769185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3433769185
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3239386556
Short name T1378
Test name
Test status
Simulation time 37140472 ps
CPU time 2.56 seconds
Started Mar 12 03:09:57 PM PDT 24
Finished Mar 12 03:10:00 PM PDT 24
Peak memory 233484 kb
Host smart-aff870cd-02e8-473c-adc5-9bbbcb92cd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239386556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3239386556
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.4272373873
Short name T1363
Test name
Test status
Simulation time 469558607 ps
CPU time 2.39 seconds
Started Mar 12 01:12:29 PM PDT 24
Finished Mar 12 01:12:32 PM PDT 24
Peak memory 216436 kb
Host smart-da616b27-11b1-4366-9a08-ec798feb5868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272373873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.4272373873
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2796217201
Short name T797
Test name
Test status
Simulation time 34338874 ps
CPU time 0.73 seconds
Started Mar 12 01:12:25 PM PDT 24
Finished Mar 12 01:12:26 PM PDT 24
Peak memory 204900 kb
Host smart-2426877a-cf2b-403d-905c-675eb67c1095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796217201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2796217201
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.4016500446
Short name T1681
Test name
Test status
Simulation time 48896943 ps
CPU time 0.79 seconds
Started Mar 12 03:09:44 PM PDT 24
Finished Mar 12 03:09:44 PM PDT 24
Peak memory 205984 kb
Host smart-f2249fdc-e85d-4bcf-ac58-2f5368bd8701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016500446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.4016500446
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2369973876
Short name T1900
Test name
Test status
Simulation time 3556130895 ps
CPU time 56.02 seconds
Started Mar 12 01:12:30 PM PDT 24
Finished Mar 12 01:13:27 PM PDT 24
Peak memory 257020 kb
Host smart-fb28c9b5-778f-4f10-a4bd-5df6644315ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369973876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2369973876
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2781316428
Short name T1004
Test name
Test status
Simulation time 13316432355 ps
CPU time 129.83 seconds
Started Mar 12 03:09:54 PM PDT 24
Finished Mar 12 03:12:04 PM PDT 24
Peak memory 252912 kb
Host smart-7ae949fe-0932-4312-a293-47187e3d3d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781316428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2781316428
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1996822353
Short name T1624
Test name
Test status
Simulation time 9992936082 ps
CPU time 69 seconds
Started Mar 12 03:09:55 PM PDT 24
Finished Mar 12 03:11:04 PM PDT 24
Peak memory 265380 kb
Host smart-0b5b63c6-bc95-4cbf-bbca-9449cd1196f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996822353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1996822353
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2342369026
Short name T899
Test name
Test status
Simulation time 3431415592 ps
CPU time 68.57 seconds
Started Mar 12 01:12:27 PM PDT 24
Finished Mar 12 01:13:36 PM PDT 24
Peak memory 253820 kb
Host smart-df2235ca-f399-4017-987b-78b4da18ef1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342369026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2342369026
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.167795994
Short name T226
Test name
Test status
Simulation time 16807405770 ps
CPU time 142.54 seconds
Started Mar 12 01:12:30 PM PDT 24
Finished Mar 12 01:14:52 PM PDT 24
Peak memory 249984 kb
Host smart-434cfadc-060c-4922-b7fe-f1a2145679c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167795994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle
.167795994
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2833544643
Short name T310
Test name
Test status
Simulation time 27286760236 ps
CPU time 52.56 seconds
Started Mar 12 03:09:56 PM PDT 24
Finished Mar 12 03:10:49 PM PDT 24
Peak memory 232600 kb
Host smart-3acb4f74-2039-404c-b35e-ae6201be7c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833544643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2833544643
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1283565400
Short name T1
Test name
Test status
Simulation time 4688330152 ps
CPU time 15.53 seconds
Started Mar 12 03:09:54 PM PDT 24
Finished Mar 12 03:10:09 PM PDT 24
Peak memory 245484 kb
Host smart-37527819-7d90-45dc-86ad-85df0eed8965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283565400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1283565400
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1791590551
Short name T1018
Test name
Test status
Simulation time 12151701221 ps
CPU time 18.49 seconds
Started Mar 12 01:12:28 PM PDT 24
Finished Mar 12 01:12:47 PM PDT 24
Peak memory 229828 kb
Host smart-12013d76-3f9e-469e-8b14-6729f00b5019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791590551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1791590551
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.551440047
Short name T1777
Test name
Test status
Simulation time 244174782 ps
CPU time 3.21 seconds
Started Mar 12 01:12:25 PM PDT 24
Finished Mar 12 01:12:29 PM PDT 24
Peak memory 217536 kb
Host smart-941decfb-217c-473d-878e-fed772d778df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551440047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.551440047
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_intercept.963098156
Short name T220
Test name
Test status
Simulation time 66458027 ps
CPU time 2.95 seconds
Started Mar 12 03:09:56 PM PDT 24
Finished Mar 12 03:09:59 PM PDT 24
Peak memory 233384 kb
Host smart-51bf8cc4-24fc-4287-a2c2-9cccaac5343b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963098156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.963098156
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1121779950
Short name T757
Test name
Test status
Simulation time 223755859 ps
CPU time 2.74 seconds
Started Mar 12 01:12:29 PM PDT 24
Finished Mar 12 01:12:32 PM PDT 24
Peak memory 233032 kb
Host smart-4b0e4920-a6f3-40de-adaa-d6eb5a571c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121779950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1121779950
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.695191305
Short name T1922
Test name
Test status
Simulation time 19677640654 ps
CPU time 22.83 seconds
Started Mar 12 03:09:59 PM PDT 24
Finished Mar 12 03:10:22 PM PDT 24
Peak memory 235356 kb
Host smart-6d8ff48d-6340-48a8-9045-e4bc7ca7869b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695191305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.695191305
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1994520394
Short name T1388
Test name
Test status
Simulation time 12216640211 ps
CPU time 19.35 seconds
Started Mar 12 01:12:31 PM PDT 24
Finished Mar 12 01:12:51 PM PDT 24
Peak memory 239136 kb
Host smart-c56174cc-3efd-4fb9-afca-177fa628def7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994520394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1994520394
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2233432834
Short name T1157
Test name
Test status
Simulation time 5564596926 ps
CPU time 6.68 seconds
Started Mar 12 03:09:54 PM PDT 24
Finished Mar 12 03:10:01 PM PDT 24
Peak memory 218260 kb
Host smart-c241b8bd-e32d-4354-9738-2ae53635bf5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233432834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2233432834
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2276517180
Short name T677
Test name
Test status
Simulation time 1930103203 ps
CPU time 6.27 seconds
Started Mar 12 03:09:55 PM PDT 24
Finished Mar 12 03:10:01 PM PDT 24
Peak memory 233564 kb
Host smart-076c1823-4530-45ce-b0f0-c49f62742efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276517180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2276517180
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2993142962
Short name T244
Test name
Test status
Simulation time 10939315861 ps
CPU time 20.45 seconds
Started Mar 12 01:12:24 PM PDT 24
Finished Mar 12 01:12:45 PM PDT 24
Peak memory 239376 kb
Host smart-a1b4dbde-f693-40bd-92c6-8a8668802827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993142962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2993142962
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2071390586
Short name T1098
Test name
Test status
Simulation time 149573589 ps
CPU time 3.28 seconds
Started Mar 12 01:12:28 PM PDT 24
Finished Mar 12 01:12:31 PM PDT 24
Peak memory 222204 kb
Host smart-385c170b-577e-44d2-b2aa-4a38b3f43e91
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2071390586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2071390586
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.4081627424
Short name T1196
Test name
Test status
Simulation time 1141877107 ps
CPU time 5.47 seconds
Started Mar 12 03:09:56 PM PDT 24
Finished Mar 12 03:10:02 PM PDT 24
Peak memory 218276 kb
Host smart-ef435ff4-94bb-4320-96ec-a68a40f8b2b0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4081627424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.4081627424
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2492744028
Short name T716
Test name
Test status
Simulation time 60156684785 ps
CPU time 115.62 seconds
Started Mar 12 01:12:30 PM PDT 24
Finished Mar 12 01:14:26 PM PDT 24
Peak memory 248968 kb
Host smart-135082f3-1af4-45a1-b018-be075df23ad5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492744028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2492744028
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3734556811
Short name T270
Test name
Test status
Simulation time 77135757332 ps
CPU time 229.4 seconds
Started Mar 12 03:09:57 PM PDT 24
Finished Mar 12 03:13:46 PM PDT 24
Peak memory 267952 kb
Host smart-49c23a6c-b0d3-4956-ada2-aada60fcfaa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734556811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3734556811
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1389935431
Short name T86
Test name
Test status
Simulation time 2570577243 ps
CPU time 33.8 seconds
Started Mar 12 01:12:30 PM PDT 24
Finished Mar 12 01:13:04 PM PDT 24
Peak memory 216052 kb
Host smart-2edfedc1-416c-4232-a93f-3972794e7afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389935431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1389935431
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.406857162
Short name T368
Test name
Test status
Simulation time 12178905019 ps
CPU time 62.93 seconds
Started Mar 12 03:09:42 PM PDT 24
Finished Mar 12 03:10:45 PM PDT 24
Peak memory 216040 kb
Host smart-c37aa8fe-e633-4d3d-8b7f-79886c57a26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406857162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.406857162
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1021323876
Short name T566
Test name
Test status
Simulation time 8071171146 ps
CPU time 13.01 seconds
Started Mar 12 03:09:39 PM PDT 24
Finished Mar 12 03:09:53 PM PDT 24
Peak memory 216148 kb
Host smart-7146c91a-c005-4b78-9607-91bea031cb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021323876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1021323876
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3887629273
Short name T1337
Test name
Test status
Simulation time 1106814492 ps
CPU time 7.71 seconds
Started Mar 12 01:12:30 PM PDT 24
Finished Mar 12 01:12:38 PM PDT 24
Peak memory 207928 kb
Host smart-1698637c-85cc-4709-b54c-a93c2017a51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887629273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3887629273
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1213511237
Short name T332
Test name
Test status
Simulation time 21439720 ps
CPU time 0.72 seconds
Started Mar 12 03:09:54 PM PDT 24
Finished Mar 12 03:09:55 PM PDT 24
Peak memory 205220 kb
Host smart-eeb24aa0-0dd6-4c69-859a-9bf6401c1cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213511237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1213511237
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3945131829
Short name T1847
Test name
Test status
Simulation time 46557235 ps
CPU time 1.06 seconds
Started Mar 12 01:12:27 PM PDT 24
Finished Mar 12 01:12:28 PM PDT 24
Peak memory 207672 kb
Host smart-ed2ce3ce-c952-4a8a-a671-10ae38f57f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945131829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3945131829
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2765639282
Short name T1109
Test name
Test status
Simulation time 32635446 ps
CPU time 0.78 seconds
Started Mar 12 01:12:25 PM PDT 24
Finished Mar 12 01:12:26 PM PDT 24
Peak memory 205256 kb
Host smart-b925870b-3370-4934-8079-a70001178255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765639282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2765639282
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.620666452
Short name T1755
Test name
Test status
Simulation time 264566670 ps
CPU time 1.03 seconds
Started Mar 12 03:09:57 PM PDT 24
Finished Mar 12 03:09:58 PM PDT 24
Peak memory 206252 kb
Host smart-ed7fe5ea-e98a-4173-a560-ad8954924705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620666452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.620666452
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.4131849009
Short name T1488
Test name
Test status
Simulation time 9971018382 ps
CPU time 19.91 seconds
Started Mar 12 01:12:29 PM PDT 24
Finished Mar 12 01:12:49 PM PDT 24
Peak memory 234924 kb
Host smart-3efc53cb-7f42-4287-9862-893010563212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131849009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.4131849009
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_upload.948712345
Short name T1836
Test name
Test status
Simulation time 1789965600 ps
CPU time 8.84 seconds
Started Mar 12 03:09:55 PM PDT 24
Finished Mar 12 03:10:04 PM PDT 24
Peak memory 232404 kb
Host smart-f6c7fdd0-51a3-49c1-a6f2-7b8c2134724c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948712345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.948712345
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.134424104
Short name T610
Test name
Test status
Simulation time 48334441 ps
CPU time 0.71 seconds
Started Mar 12 01:12:30 PM PDT 24
Finished Mar 12 01:12:31 PM PDT 24
Peak memory 204164 kb
Host smart-abfeac03-11bd-4234-944a-b28df81ea2d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134424104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.134424104
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.337268133
Short name T1828
Test name
Test status
Simulation time 16047856 ps
CPU time 0.72 seconds
Started Mar 12 03:09:59 PM PDT 24
Finished Mar 12 03:09:59 PM PDT 24
Peak memory 204220 kb
Host smart-8f8dc752-71d2-43ae-8c7f-bc22bdf4f84b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337268133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.337268133
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.37219703
Short name T1817
Test name
Test status
Simulation time 9295730676 ps
CPU time 8.05 seconds
Started Mar 12 03:09:57 PM PDT 24
Finished Mar 12 03:10:05 PM PDT 24
Peak memory 224228 kb
Host smart-78c4a726-ec67-41d4-91c4-ec748f26e8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37219703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.37219703
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.460693117
Short name T550
Test name
Test status
Simulation time 335826481 ps
CPU time 2.63 seconds
Started Mar 12 01:12:26 PM PDT 24
Finished Mar 12 01:12:29 PM PDT 24
Peak memory 233304 kb
Host smart-61afdf8c-3675-402c-b778-b77cffa4ae57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460693117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.460693117
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1019510004
Short name T1510
Test name
Test status
Simulation time 16939196 ps
CPU time 0.73 seconds
Started Mar 12 01:12:27 PM PDT 24
Finished Mar 12 01:12:28 PM PDT 24
Peak memory 205216 kb
Host smart-7725bec0-77da-48c4-8666-ea734a810ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019510004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1019510004
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1362315292
Short name T328
Test name
Test status
Simulation time 36975526 ps
CPU time 0.82 seconds
Started Mar 12 03:09:57 PM PDT 24
Finished Mar 12 03:09:58 PM PDT 24
Peak memory 206252 kb
Host smart-af24d7d0-8d6f-4032-a89b-3ad5088ec1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362315292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1362315292
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1926692035
Short name T1726
Test name
Test status
Simulation time 13616051105 ps
CPU time 53.91 seconds
Started Mar 12 01:12:29 PM PDT 24
Finished Mar 12 01:13:23 PM PDT 24
Peak memory 249132 kb
Host smart-3099dadc-d9bd-4c36-bcf3-f7fa71950b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926692035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1926692035
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.2048585901
Short name T1349
Test name
Test status
Simulation time 1871977779 ps
CPU time 17.39 seconds
Started Mar 12 03:09:58 PM PDT 24
Finished Mar 12 03:10:15 PM PDT 24
Peak memory 239816 kb
Host smart-e70d7bd1-cb23-4c62-a4b5-9ac8bc98452a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048585901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.2048585901
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3687777529
Short name T1443
Test name
Test status
Simulation time 1027538356453 ps
CPU time 718.71 seconds
Started Mar 12 01:12:31 PM PDT 24
Finished Mar 12 01:24:30 PM PDT 24
Peak memory 273324 kb
Host smart-2c7fd470-c76b-477b-b93f-7487f968746f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687777529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3687777529
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.996062138
Short name T702
Test name
Test status
Simulation time 4555660423 ps
CPU time 52.29 seconds
Started Mar 12 03:10:02 PM PDT 24
Finished Mar 12 03:10:55 PM PDT 24
Peak memory 236256 kb
Host smart-a9107ffd-d925-47b9-a57a-ad0d085a91cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996062138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.996062138
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2776021325
Short name T826
Test name
Test status
Simulation time 102767763211 ps
CPU time 178.03 seconds
Started Mar 12 03:09:57 PM PDT 24
Finished Mar 12 03:12:55 PM PDT 24
Peak memory 239140 kb
Host smart-d42d6d45-a78c-4efb-80f1-be30749e9fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776021325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2776021325
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.4251858761
Short name T278
Test name
Test status
Simulation time 8948485741 ps
CPU time 65.9 seconds
Started Mar 12 01:12:28 PM PDT 24
Finished Mar 12 01:13:34 PM PDT 24
Peak memory 250036 kb
Host smart-91cbb514-ddbc-442a-981f-23faa0529674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251858761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.4251858761
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3306723104
Short name T146
Test name
Test status
Simulation time 881286092 ps
CPU time 9.83 seconds
Started Mar 12 03:09:57 PM PDT 24
Finished Mar 12 03:10:07 PM PDT 24
Peak memory 232400 kb
Host smart-71f990c7-91bc-45fd-a6b6-337d1c81df15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306723104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3306723104
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.4001874152
Short name T1369
Test name
Test status
Simulation time 41352604218 ps
CPU time 40.71 seconds
Started Mar 12 01:12:33 PM PDT 24
Finished Mar 12 01:13:14 PM PDT 24
Peak memory 255784 kb
Host smart-c114b952-69f8-4990-9e9c-fd45b72f41f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001874152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.4001874152
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1831413411
Short name T441
Test name
Test status
Simulation time 1632794710 ps
CPU time 4.44 seconds
Started Mar 12 01:12:27 PM PDT 24
Finished Mar 12 01:12:32 PM PDT 24
Peak memory 217072 kb
Host smart-0785721b-dcf8-46d4-a7fe-705e7f89165c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831413411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1831413411
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3289872490
Short name T212
Test name
Test status
Simulation time 614291518 ps
CPU time 5.07 seconds
Started Mar 12 03:09:54 PM PDT 24
Finished Mar 12 03:10:00 PM PDT 24
Peak memory 217900 kb
Host smart-dba2af5e-fb88-4676-8921-8d6f00159c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289872490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3289872490
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1023829492
Short name T1585
Test name
Test status
Simulation time 422369263 ps
CPU time 7.1 seconds
Started Mar 12 01:12:30 PM PDT 24
Finished Mar 12 01:12:37 PM PDT 24
Peak memory 236344 kb
Host smart-3aaff2d5-6f33-4cee-b97d-6cb50ab5f74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023829492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1023829492
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.2406083922
Short name T1247
Test name
Test status
Simulation time 6534777417 ps
CPU time 11.43 seconds
Started Mar 12 03:09:57 PM PDT 24
Finished Mar 12 03:10:08 PM PDT 24
Peak memory 240464 kb
Host smart-2ea24ffb-9c76-4731-a0d1-54685ff9e832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406083922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2406083922
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1716931453
Short name T1676
Test name
Test status
Simulation time 307703186 ps
CPU time 2.58 seconds
Started Mar 12 03:09:57 PM PDT 24
Finished Mar 12 03:09:59 PM PDT 24
Peak memory 232876 kb
Host smart-c6ae6eb7-93cf-462b-9ccb-b2baa50afadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716931453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1716931453
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2661835370
Short name T1151
Test name
Test status
Simulation time 1320593309 ps
CPU time 6.54 seconds
Started Mar 12 01:12:28 PM PDT 24
Finished Mar 12 01:12:35 PM PDT 24
Peak memory 237744 kb
Host smart-72d118db-0663-4197-bd94-579975a0f587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661835370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2661835370
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1663352302
Short name T662
Test name
Test status
Simulation time 3112821295 ps
CPU time 13.29 seconds
Started Mar 12 01:12:31 PM PDT 24
Finished Mar 12 01:12:44 PM PDT 24
Peak memory 226272 kb
Host smart-3a24001f-c647-4f1c-9a9a-0339b8fe61be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663352302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1663352302
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2637527064
Short name T1551
Test name
Test status
Simulation time 2345677186 ps
CPU time 4.7 seconds
Started Mar 12 03:10:00 PM PDT 24
Finished Mar 12 03:10:06 PM PDT 24
Peak memory 233288 kb
Host smart-6bf1612e-ceaf-4bd6-abfe-b486407db794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637527064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2637527064
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2010471682
Short name T1216
Test name
Test status
Simulation time 340807465 ps
CPU time 3.53 seconds
Started Mar 12 01:12:27 PM PDT 24
Finished Mar 12 01:12:31 PM PDT 24
Peak memory 219996 kb
Host smart-aafcae94-d039-42ed-8192-e55a0e832c28
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2010471682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2010471682
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.622938585
Short name T1092
Test name
Test status
Simulation time 2279922132 ps
CPU time 6.41 seconds
Started Mar 12 03:10:09 PM PDT 24
Finished Mar 12 03:10:20 PM PDT 24
Peak memory 222344 kb
Host smart-3cd9bbb7-6e88-44dd-91e8-1fc3462dd7e7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=622938585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.622938585
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.4233377557
Short name T624
Test name
Test status
Simulation time 57858433 ps
CPU time 1.1 seconds
Started Mar 12 01:12:30 PM PDT 24
Finished Mar 12 01:12:31 PM PDT 24
Peak memory 206372 kb
Host smart-84529e50-8a79-4549-bfc9-1c7df17b478d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233377557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.4233377557
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1439563092
Short name T1788
Test name
Test status
Simulation time 7550793106 ps
CPU time 21.3 seconds
Started Mar 12 01:12:27 PM PDT 24
Finished Mar 12 01:12:48 PM PDT 24
Peak memory 216036 kb
Host smart-c5952821-4dce-40dd-97b6-127ac2246ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439563092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1439563092
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1601762763
Short name T796
Test name
Test status
Simulation time 2764948298 ps
CPU time 8.2 seconds
Started Mar 12 03:09:57 PM PDT 24
Finished Mar 12 03:10:05 PM PDT 24
Peak memory 216056 kb
Host smart-b44d126c-4d73-404e-99e7-a28bf88994be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601762763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1601762763
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1573726514
Short name T767
Test name
Test status
Simulation time 124133090050 ps
CPU time 22.15 seconds
Started Mar 12 03:09:57 PM PDT 24
Finished Mar 12 03:10:19 PM PDT 24
Peak memory 215652 kb
Host smart-8a613359-81f1-468d-b3fc-fc8d4d097406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573726514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1573726514
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.581064030
Short name T522
Test name
Test status
Simulation time 998647986 ps
CPU time 2.25 seconds
Started Mar 12 01:12:28 PM PDT 24
Finished Mar 12 01:12:30 PM PDT 24
Peak memory 207680 kb
Host smart-cc0302c6-9633-4c19-9963-b942cb7609d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581064030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.581064030
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1894496430
Short name T645
Test name
Test status
Simulation time 290556929 ps
CPU time 3.56 seconds
Started Mar 12 01:12:31 PM PDT 24
Finished Mar 12 01:12:35 PM PDT 24
Peak memory 216136 kb
Host smart-72de714a-1893-4886-85ae-50d57f75168c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894496430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1894496430
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.89613362
Short name T1366
Test name
Test status
Simulation time 260188839 ps
CPU time 3.19 seconds
Started Mar 12 03:09:55 PM PDT 24
Finished Mar 12 03:09:59 PM PDT 24
Peak memory 207940 kb
Host smart-ea5343e9-256f-44d6-8cfd-cfd419b0a11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89613362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.89613362
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1486380455
Short name T1736
Test name
Test status
Simulation time 38637086 ps
CPU time 0.72 seconds
Started Mar 12 01:12:26 PM PDT 24
Finished Mar 12 01:12:27 PM PDT 24
Peak memory 205216 kb
Host smart-2b1941cc-57d7-4f93-a6e8-892a32a3323e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486380455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1486380455
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2069935120
Short name T401
Test name
Test status
Simulation time 239134940 ps
CPU time 0.99 seconds
Started Mar 12 03:10:00 PM PDT 24
Finished Mar 12 03:10:02 PM PDT 24
Peak memory 206252 kb
Host smart-bf563ad3-6c71-4065-b2a0-c297a0f18cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069935120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2069935120
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.1175977255
Short name T511
Test name
Test status
Simulation time 1543384905 ps
CPU time 4.43 seconds
Started Mar 12 01:12:31 PM PDT 24
Finished Mar 12 01:12:36 PM PDT 24
Peak memory 218476 kb
Host smart-c7587a74-4bdc-43b0-9b2e-40669aa73cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175977255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1175977255
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_upload.679626595
Short name T608
Test name
Test status
Simulation time 5035167730 ps
CPU time 17.07 seconds
Started Mar 12 03:09:57 PM PDT 24
Finished Mar 12 03:10:14 PM PDT 24
Peak memory 232344 kb
Host smart-4fc40291-032a-42b4-98a8-6ebf3126cf94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679626595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.679626595
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1220400357
Short name T350
Test name
Test status
Simulation time 20900880 ps
CPU time 0.69 seconds
Started Mar 12 01:12:39 PM PDT 24
Finished Mar 12 01:12:40 PM PDT 24
Peak memory 204812 kb
Host smart-18528009-fd46-466e-94e6-e1059b47f9a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220400357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1220400357
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1835104622
Short name T652
Test name
Test status
Simulation time 13969539 ps
CPU time 0.71 seconds
Started Mar 12 03:09:57 PM PDT 24
Finished Mar 12 03:09:58 PM PDT 24
Peak memory 204820 kb
Host smart-39d80f69-cd16-4119-a2a1-c38df1027a29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835104622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1835104622
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1292409992
Short name T1644
Test name
Test status
Simulation time 777465173 ps
CPU time 3.77 seconds
Started Mar 12 03:09:59 PM PDT 24
Finished Mar 12 03:10:03 PM PDT 24
Peak memory 233340 kb
Host smart-816be03e-ce77-408e-8cc1-340c198cc473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292409992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1292409992
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.4236955944
Short name T1549
Test name
Test status
Simulation time 518562122 ps
CPU time 3.67 seconds
Started Mar 12 01:12:46 PM PDT 24
Finished Mar 12 01:12:50 PM PDT 24
Peak memory 218540 kb
Host smart-dfef37fe-52b7-4e25-a57b-499dba6179b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236955944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.4236955944
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2051139807
Short name T654
Test name
Test status
Simulation time 71911646 ps
CPU time 0.73 seconds
Started Mar 12 03:09:56 PM PDT 24
Finished Mar 12 03:09:56 PM PDT 24
Peak memory 205924 kb
Host smart-5a203dbe-2d13-43fe-b14a-658ccbc70289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051139807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2051139807
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.4038211169
Short name T870
Test name
Test status
Simulation time 25338613 ps
CPU time 0.75 seconds
Started Mar 12 01:12:31 PM PDT 24
Finished Mar 12 01:12:32 PM PDT 24
Peak memory 205204 kb
Host smart-8b5f87ca-d544-4d5a-9711-2b2cc5a85fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038211169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.4038211169
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3978881544
Short name T292
Test name
Test status
Simulation time 226531842448 ps
CPU time 269.13 seconds
Started Mar 12 01:12:39 PM PDT 24
Finished Mar 12 01:17:08 PM PDT 24
Peak memory 248952 kb
Host smart-4f9db995-9860-4ab4-a3ec-f740d6cbcc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978881544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3978881544
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.4038141495
Short name T1213
Test name
Test status
Simulation time 30157629825 ps
CPU time 115.36 seconds
Started Mar 12 03:09:57 PM PDT 24
Finished Mar 12 03:11:52 PM PDT 24
Peak memory 256968 kb
Host smart-44971318-0d18-48d9-b601-17ae47fa77dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038141495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.4038141495
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3229903966
Short name T1563
Test name
Test status
Simulation time 13364057695 ps
CPU time 67.45 seconds
Started Mar 12 01:12:48 PM PDT 24
Finished Mar 12 01:13:56 PM PDT 24
Peak memory 239808 kb
Host smart-2191002b-a90e-4efe-a58c-ebce14260693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229903966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3229903966
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1200831988
Short name T1271
Test name
Test status
Simulation time 95144199411 ps
CPU time 344.42 seconds
Started Mar 12 03:10:02 PM PDT 24
Finished Mar 12 03:15:47 PM PDT 24
Peak memory 255664 kb
Host smart-e8ec6f33-54fd-49e6-a8c3-ab41c44b57f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200831988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1200831988
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2998815063
Short name T1674
Test name
Test status
Simulation time 86400645961 ps
CPU time 193.89 seconds
Started Mar 12 01:12:35 PM PDT 24
Finished Mar 12 01:15:49 PM PDT 24
Peak memory 250160 kb
Host smart-b9f53eef-851c-4188-8e9e-9b25195af968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998815063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2998815063
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1576657532
Short name T465
Test name
Test status
Simulation time 447783530 ps
CPU time 15.3 seconds
Started Mar 12 01:12:34 PM PDT 24
Finished Mar 12 01:12:49 PM PDT 24
Peak memory 224180 kb
Host smart-05815bd2-2848-4c97-a7cd-3d0639bf3bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576657532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1576657532
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2707269000
Short name T546
Test name
Test status
Simulation time 2471447138 ps
CPU time 11.46 seconds
Started Mar 12 03:09:59 PM PDT 24
Finished Mar 12 03:10:11 PM PDT 24
Peak memory 222280 kb
Host smart-f1e97e20-7e89-4882-81c1-3182c21f0840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707269000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2707269000
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.576721314
Short name T1168
Test name
Test status
Simulation time 2857688354 ps
CPU time 4.93 seconds
Started Mar 12 03:09:59 PM PDT 24
Finished Mar 12 03:10:05 PM PDT 24
Peak memory 224244 kb
Host smart-2b4dd976-2abe-4f5e-931a-6f4df475ae53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576721314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.576721314
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_intercept.766170483
Short name T1667
Test name
Test status
Simulation time 8677934144 ps
CPU time 9.05 seconds
Started Mar 12 01:12:31 PM PDT 24
Finished Mar 12 01:12:41 PM PDT 24
Peak memory 217104 kb
Host smart-1b6d392b-c65c-45fb-bf08-850c5b851917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766170483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.766170483
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3194031045
Short name T1734
Test name
Test status
Simulation time 7830516980 ps
CPU time 11.23 seconds
Started Mar 12 03:10:00 PM PDT 24
Finished Mar 12 03:10:11 PM PDT 24
Peak memory 224228 kb
Host smart-9ae1b579-3e96-4e14-afe2-a4075602703a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194031045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3194031045
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3403793934
Short name T889
Test name
Test status
Simulation time 12135500045 ps
CPU time 15.06 seconds
Started Mar 12 01:12:46 PM PDT 24
Finished Mar 12 01:13:01 PM PDT 24
Peak memory 234768 kb
Host smart-f364c8a7-21a0-4a77-b6c5-a07c32fdb200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403793934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3403793934
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1832723897
Short name T267
Test name
Test status
Simulation time 134426677 ps
CPU time 2.76 seconds
Started Mar 12 03:09:59 PM PDT 24
Finished Mar 12 03:10:02 PM PDT 24
Peak memory 232648 kb
Host smart-6e14d82a-cb06-4046-b23e-2a942bd8f14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832723897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1832723897
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.975935818
Short name T1343
Test name
Test status
Simulation time 43505548387 ps
CPU time 20.12 seconds
Started Mar 12 01:12:30 PM PDT 24
Finished Mar 12 01:12:50 PM PDT 24
Peak memory 231536 kb
Host smart-a4427572-3e5d-42ac-b286-83a3eedb56cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975935818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.975935818
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2192664101
Short name T232
Test name
Test status
Simulation time 22287937306 ps
CPU time 8.16 seconds
Started Mar 12 03:09:58 PM PDT 24
Finished Mar 12 03:10:06 PM PDT 24
Peak memory 232540 kb
Host smart-03d7d39b-fefb-46a7-9a0b-9b52715fc717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192664101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2192664101
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.367254060
Short name T581
Test name
Test status
Simulation time 2351739913 ps
CPU time 10.26 seconds
Started Mar 12 01:12:31 PM PDT 24
Finished Mar 12 01:12:41 PM PDT 24
Peak memory 232480 kb
Host smart-f529601b-a7ec-4223-8091-7dce25d0f1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367254060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.367254060
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1838258585
Short name T1445
Test name
Test status
Simulation time 261723456 ps
CPU time 3.48 seconds
Started Mar 12 03:09:59 PM PDT 24
Finished Mar 12 03:10:03 PM PDT 24
Peak memory 221776 kb
Host smart-db4cdc03-a63f-4585-a855-cc3c02a2d179
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1838258585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1838258585
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.934755829
Short name T1716
Test name
Test status
Simulation time 1472716769 ps
CPU time 3.72 seconds
Started Mar 12 01:12:36 PM PDT 24
Finished Mar 12 01:12:39 PM PDT 24
Peak memory 216308 kb
Host smart-0c920e94-b6ed-4759-82a4-2af40c383f44
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=934755829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.934755829
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2193776083
Short name T1248
Test name
Test status
Simulation time 69524179442 ps
CPU time 179.89 seconds
Started Mar 12 03:09:58 PM PDT 24
Finished Mar 12 03:12:58 PM PDT 24
Peak memory 265564 kb
Host smart-ae0dc065-6eae-4dd0-b64a-0b573edb994a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193776083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2193776083
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2692225453
Short name T155
Test name
Test status
Simulation time 71494261 ps
CPU time 1.11 seconds
Started Mar 12 01:12:46 PM PDT 24
Finished Mar 12 01:12:47 PM PDT 24
Peak memory 206512 kb
Host smart-707e172a-c97b-43fb-8952-fb6837fe6916
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692225453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2692225453
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3794595860
Short name T562
Test name
Test status
Simulation time 13644248536 ps
CPU time 43.2 seconds
Started Mar 12 03:10:01 PM PDT 24
Finished Mar 12 03:10:45 PM PDT 24
Peak memory 216164 kb
Host smart-aa11e50a-41e4-41eb-9952-3e1f3da8cda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794595860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3794595860
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.48246847
Short name T1697
Test name
Test status
Simulation time 2841648447 ps
CPU time 24.81 seconds
Started Mar 12 01:12:30 PM PDT 24
Finished Mar 12 01:12:55 PM PDT 24
Peak memory 216080 kb
Host smart-0bb176c8-e5b0-4f91-9be1-0e7125ef8496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48246847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.48246847
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3320777435
Short name T1625
Test name
Test status
Simulation time 13502924172 ps
CPU time 29.51 seconds
Started Mar 12 03:09:59 PM PDT 24
Finished Mar 12 03:10:29 PM PDT 24
Peak memory 216108 kb
Host smart-6a29bec1-1aa2-4064-a814-d148f1a7053f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320777435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3320777435
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.893827820
Short name T793
Test name
Test status
Simulation time 2432499587 ps
CPU time 4.23 seconds
Started Mar 12 01:12:29 PM PDT 24
Finished Mar 12 01:12:33 PM PDT 24
Peak memory 216120 kb
Host smart-4e585710-0b27-4742-8ed7-586e8f62a087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893827820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.893827820
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1672533657
Short name T619
Test name
Test status
Simulation time 24002376 ps
CPU time 0.76 seconds
Started Mar 12 03:10:01 PM PDT 24
Finished Mar 12 03:10:02 PM PDT 24
Peak memory 205260 kb
Host smart-bffc090a-929b-4697-a777-019d0c28c02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672533657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1672533657
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3437866715
Short name T939
Test name
Test status
Simulation time 704876653 ps
CPU time 1.45 seconds
Started Mar 12 01:12:30 PM PDT 24
Finished Mar 12 01:12:32 PM PDT 24
Peak memory 207896 kb
Host smart-124815d7-8d1e-4532-ad0f-2adfc4fdeb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437866715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3437866715
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2368365063
Short name T346
Test name
Test status
Simulation time 282079025 ps
CPU time 1.14 seconds
Started Mar 12 01:12:31 PM PDT 24
Finished Mar 12 01:12:33 PM PDT 24
Peak memory 206288 kb
Host smart-a3db0b47-3349-47a5-9be8-0d4d7a9525e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368365063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2368365063
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.721618453
Short name T1517
Test name
Test status
Simulation time 170524657 ps
CPU time 0.98 seconds
Started Mar 12 03:09:58 PM PDT 24
Finished Mar 12 03:09:59 PM PDT 24
Peak memory 206256 kb
Host smart-e7346ebd-07e9-4966-8b15-46d8e76951b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721618453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.721618453
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2019480452
Short name T1361
Test name
Test status
Simulation time 13215910919 ps
CPU time 11.93 seconds
Started Mar 12 03:09:58 PM PDT 24
Finished Mar 12 03:10:11 PM PDT 24
Peak memory 217104 kb
Host smart-e2665a42-4d17-4797-9727-8daeca9f0d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019480452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2019480452
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_upload.3286648474
Short name T1367
Test name
Test status
Simulation time 1199181181 ps
CPU time 5.02 seconds
Started Mar 12 01:12:45 PM PDT 24
Finished Mar 12 01:12:51 PM PDT 24
Peak memory 233456 kb
Host smart-6dfbaf11-d496-417d-96a4-5c8a40635dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286648474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3286648474
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.177712148
Short name T538
Test name
Test status
Simulation time 15596521 ps
CPU time 0.73 seconds
Started Mar 12 01:12:36 PM PDT 24
Finished Mar 12 01:12:36 PM PDT 24
Peak memory 204644 kb
Host smart-18ddb9cb-4fee-429e-9331-12d6cf476265
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177712148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.177712148
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2973678636
Short name T837
Test name
Test status
Simulation time 14200879 ps
CPU time 0.71 seconds
Started Mar 12 03:10:10 PM PDT 24
Finished Mar 12 03:10:14 PM PDT 24
Peak memory 204808 kb
Host smart-60700346-45f9-4da3-b328-ed62c9228b4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973678636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2973678636
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2903092277
Short name T1630
Test name
Test status
Simulation time 157705543 ps
CPU time 3.03 seconds
Started Mar 12 03:10:01 PM PDT 24
Finished Mar 12 03:10:05 PM PDT 24
Peak memory 233372 kb
Host smart-09d4a389-71f9-4393-a8a5-4ddd2b287f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903092277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2903092277
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3639085036
Short name T1226
Test name
Test status
Simulation time 2072946143 ps
CPU time 6.62 seconds
Started Mar 12 01:12:34 PM PDT 24
Finished Mar 12 01:12:41 PM PDT 24
Peak memory 218792 kb
Host smart-36b22d89-210e-493c-9d58-d6c0ea15cad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639085036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3639085036
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.17301204
Short name T366
Test name
Test status
Simulation time 56786256 ps
CPU time 0.76 seconds
Started Mar 12 03:09:57 PM PDT 24
Finished Mar 12 03:09:58 PM PDT 24
Peak memory 204916 kb
Host smart-3dd786e0-8a05-413f-a821-65601e5842a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17301204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.17301204
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2842513562
Short name T680
Test name
Test status
Simulation time 65612659 ps
CPU time 0.76 seconds
Started Mar 12 01:12:46 PM PDT 24
Finished Mar 12 01:12:47 PM PDT 24
Peak memory 205932 kb
Host smart-afb1afcd-9558-4208-8892-ebe342c9c3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842513562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2842513562
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1275000991
Short name T1775
Test name
Test status
Simulation time 9237642082 ps
CPU time 46.04 seconds
Started Mar 12 01:12:35 PM PDT 24
Finished Mar 12 01:13:21 PM PDT 24
Peak memory 250924 kb
Host smart-53b326e8-f25b-4e89-80f4-3b700fbda9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275000991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1275000991
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1594408026
Short name T396
Test name
Test status
Simulation time 16010708727 ps
CPU time 78.52 seconds
Started Mar 12 03:10:12 PM PDT 24
Finished Mar 12 03:11:33 PM PDT 24
Peak memory 240636 kb
Host smart-96f49201-7c0a-416f-9354-710d78cbf856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594408026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1594408026
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2557974498
Short name T1364
Test name
Test status
Simulation time 22149615998 ps
CPU time 49.95 seconds
Started Mar 12 01:12:46 PM PDT 24
Finished Mar 12 01:13:36 PM PDT 24
Peak memory 248948 kb
Host smart-05f0ead7-d931-4efb-9ce4-15b4dfd24e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557974498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2557974498
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.995575996
Short name T904
Test name
Test status
Simulation time 11149504237 ps
CPU time 46.72 seconds
Started Mar 12 03:10:08 PM PDT 24
Finished Mar 12 03:10:56 PM PDT 24
Peak memory 238932 kb
Host smart-13d1fe83-f5e8-4534-83ad-61fa105f6990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995575996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.995575996
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2736031611
Short name T221
Test name
Test status
Simulation time 78294089949 ps
CPU time 519.43 seconds
Started Mar 12 03:10:10 PM PDT 24
Finished Mar 12 03:18:53 PM PDT 24
Peak memory 265128 kb
Host smart-7a40d74e-485f-4057-8bf7-76a14f74512c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736031611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2736031611
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.73772755
Short name T1799
Test name
Test status
Simulation time 97088219143 ps
CPU time 196.29 seconds
Started Mar 12 01:12:36 PM PDT 24
Finished Mar 12 01:15:53 PM PDT 24
Peak memory 250220 kb
Host smart-e6edaae1-b3a4-4aac-a165-7414295e9d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73772755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle.73772755
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2380753573
Short name T314
Test name
Test status
Simulation time 3288527303 ps
CPU time 11.03 seconds
Started Mar 12 01:12:34 PM PDT 24
Finished Mar 12 01:12:45 PM PDT 24
Peak memory 234008 kb
Host smart-033731b7-37f1-43fc-a16c-87990e32b778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380753573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2380753573
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2974960812
Short name T1912
Test name
Test status
Simulation time 797659650 ps
CPU time 16.65 seconds
Started Mar 12 03:10:01 PM PDT 24
Finished Mar 12 03:10:18 PM PDT 24
Peak memory 251200 kb
Host smart-0bd41c57-5e6a-41c8-beea-ffaccf127516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974960812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2974960812
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1949715980
Short name T950
Test name
Test status
Simulation time 34774707302 ps
CPU time 8.21 seconds
Started Mar 12 01:12:47 PM PDT 24
Finished Mar 12 01:12:56 PM PDT 24
Peak memory 233880 kb
Host smart-d27c4a42-73c0-4cb8-a2cb-aac729045453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949715980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1949715980
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3793728880
Short name T1131
Test name
Test status
Simulation time 2356345850 ps
CPU time 9.05 seconds
Started Mar 12 03:09:58 PM PDT 24
Finished Mar 12 03:10:07 PM PDT 24
Peak memory 224260 kb
Host smart-95dc4251-00e3-4ba2-b438-1741fcdbf4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793728880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3793728880
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3419076316
Short name T1490
Test name
Test status
Simulation time 25845604280 ps
CPU time 24.71 seconds
Started Mar 12 01:12:35 PM PDT 24
Finished Mar 12 01:13:00 PM PDT 24
Peak memory 248816 kb
Host smart-84610270-30b6-4523-8320-5e22e3f463c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419076316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3419076316
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.4128332890
Short name T726
Test name
Test status
Simulation time 1954796550 ps
CPU time 9 seconds
Started Mar 12 03:09:59 PM PDT 24
Finished Mar 12 03:10:08 PM PDT 24
Peak memory 232672 kb
Host smart-2a9a8b6a-72a2-43dc-9fce-79b3000862f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128332890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.4128332890
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3091965695
Short name T1760
Test name
Test status
Simulation time 5216224094 ps
CPU time 9.66 seconds
Started Mar 12 03:10:02 PM PDT 24
Finished Mar 12 03:10:12 PM PDT 24
Peak memory 240540 kb
Host smart-4601b5ee-4d83-4edd-9fc9-4a3b4c7810cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091965695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3091965695
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.440949951
Short name T648
Test name
Test status
Simulation time 1179087439 ps
CPU time 8.16 seconds
Started Mar 12 01:12:34 PM PDT 24
Finished Mar 12 01:12:43 PM PDT 24
Peak memory 224144 kb
Host smart-745bc7fc-4b2d-42ce-b06e-ba90b9e1e197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440949951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.440949951
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2674310961
Short name T254
Test name
Test status
Simulation time 1490078538 ps
CPU time 4.56 seconds
Started Mar 12 01:12:33 PM PDT 24
Finished Mar 12 01:12:37 PM PDT 24
Peak memory 216432 kb
Host smart-1239abd2-3858-407b-a97a-1f6e56e2e60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674310961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2674310961
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3981835956
Short name T476
Test name
Test status
Simulation time 735883010 ps
CPU time 4.16 seconds
Started Mar 12 03:09:59 PM PDT 24
Finished Mar 12 03:10:04 PM PDT 24
Peak memory 224176 kb
Host smart-d4cba0b2-fd5f-43d1-ae8f-acd4116930dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981835956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3981835956
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.415653474
Short name T599
Test name
Test status
Simulation time 216234743 ps
CPU time 3.8 seconds
Started Mar 12 01:12:34 PM PDT 24
Finished Mar 12 01:12:38 PM PDT 24
Peak memory 216156 kb
Host smart-8391d9bd-6bc4-436e-91ef-c2ddc5967e0c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=415653474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.415653474
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.994679611
Short name T1431
Test name
Test status
Simulation time 4810894567 ps
CPU time 6.19 seconds
Started Mar 12 03:10:14 PM PDT 24
Finished Mar 12 03:10:21 PM PDT 24
Peak memory 219680 kb
Host smart-94c35d3c-d0bb-43dc-8336-be489f9b2b7c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=994679611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.994679611
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2725234920
Short name T783
Test name
Test status
Simulation time 341059052 ps
CPU time 1.04 seconds
Started Mar 12 01:12:42 PM PDT 24
Finished Mar 12 01:12:43 PM PDT 24
Peak memory 206396 kb
Host smart-ae0a39e4-d975-4c9a-8bbb-cd0b10b9876f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725234920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2725234920
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.4041693314
Short name T62
Test name
Test status
Simulation time 2935132634 ps
CPU time 52.65 seconds
Started Mar 12 03:10:10 PM PDT 24
Finished Mar 12 03:11:06 PM PDT 24
Peak memory 248992 kb
Host smart-bcc6711f-5349-4c3b-84fd-1d50c3efd1eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041693314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.4041693314
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3416085475
Short name T1236
Test name
Test status
Simulation time 15106300342 ps
CPU time 13.46 seconds
Started Mar 12 01:12:46 PM PDT 24
Finished Mar 12 01:12:59 PM PDT 24
Peak memory 216160 kb
Host smart-715aeffa-4162-454f-a3d4-a0c03af743a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416085475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3416085475
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.532323245
Short name T1580
Test name
Test status
Simulation time 3230450455 ps
CPU time 18.79 seconds
Started Mar 12 03:10:00 PM PDT 24
Finished Mar 12 03:10:20 PM PDT 24
Peak memory 216132 kb
Host smart-8eea62ff-f34a-435a-9726-bd58324ede68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532323245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.532323245
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1478660540
Short name T1875
Test name
Test status
Simulation time 586969857 ps
CPU time 2.5 seconds
Started Mar 12 01:12:36 PM PDT 24
Finished Mar 12 01:12:38 PM PDT 24
Peak memory 207900 kb
Host smart-a123db72-ba8a-4c9d-90ef-89fd0dd73312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478660540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1478660540
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1531988388
Short name T575
Test name
Test status
Simulation time 3904856262 ps
CPU time 11.49 seconds
Started Mar 12 03:09:59 PM PDT 24
Finished Mar 12 03:10:11 PM PDT 24
Peak memory 216124 kb
Host smart-002ad72a-fcb8-410e-9b35-226a98355348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531988388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1531988388
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2379125623
Short name T341
Test name
Test status
Simulation time 360715669 ps
CPU time 5.46 seconds
Started Mar 12 03:10:02 PM PDT 24
Finished Mar 12 03:10:08 PM PDT 24
Peak memory 216204 kb
Host smart-026f5157-dd9a-4d67-99f0-aeb01b091ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379125623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2379125623
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.361446245
Short name T1553
Test name
Test status
Simulation time 49870153 ps
CPU time 1.57 seconds
Started Mar 12 01:12:38 PM PDT 24
Finished Mar 12 01:12:39 PM PDT 24
Peak memory 216388 kb
Host smart-67e1ed05-f42f-4e43-8676-41424f4324c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361446245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.361446245
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2179591630
Short name T695
Test name
Test status
Simulation time 92866240 ps
CPU time 0.78 seconds
Started Mar 12 03:09:58 PM PDT 24
Finished Mar 12 03:09:59 PM PDT 24
Peak memory 205256 kb
Host smart-768628de-4573-47fc-a3c3-e4ddf55aebb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179591630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2179591630
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3203209766
Short name T773
Test name
Test status
Simulation time 44041888 ps
CPU time 0.87 seconds
Started Mar 12 01:12:46 PM PDT 24
Finished Mar 12 01:12:47 PM PDT 24
Peak memory 206296 kb
Host smart-141875a3-148d-488d-8697-711959cbd96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203209766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3203209766
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1523409864
Short name T229
Test name
Test status
Simulation time 251999313 ps
CPU time 3.82 seconds
Started Mar 12 03:10:02 PM PDT 24
Finished Mar 12 03:10:07 PM PDT 24
Peak memory 232376 kb
Host smart-a1fd2e0d-6581-440c-9253-0cb8d014bff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523409864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1523409864
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_upload.2566303526
Short name T1908
Test name
Test status
Simulation time 3685311108 ps
CPU time 4.67 seconds
Started Mar 12 01:12:36 PM PDT 24
Finished Mar 12 01:12:41 PM PDT 24
Peak memory 218328 kb
Host smart-7e802b9e-b723-40b6-acb3-3cbb7f2fa23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566303526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2566303526
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1690247957
Short name T166
Test name
Test status
Simulation time 13508138 ps
CPU time 0.7 seconds
Started Mar 12 01:10:47 PM PDT 24
Finished Mar 12 01:10:48 PM PDT 24
Peak memory 204768 kb
Host smart-9add0c0c-b6fa-403d-bd2b-5bdd9f02f5b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690247957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
690247957
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3198633038
Short name T696
Test name
Test status
Simulation time 35967666 ps
CPU time 0.71 seconds
Started Mar 12 03:05:49 PM PDT 24
Finished Mar 12 03:05:50 PM PDT 24
Peak memory 204620 kb
Host smart-f915b28c-6ca6-4df6-a7ff-3fdf6b3eeda9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198633038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
198633038
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3908988714
Short name T231
Test name
Test status
Simulation time 1200289760 ps
CPU time 6 seconds
Started Mar 12 03:05:38 PM PDT 24
Finished Mar 12 03:05:44 PM PDT 24
Peak memory 233448 kb
Host smart-fdc5f7c4-b7f9-48b3-83df-e49d5ac15094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908988714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3908988714
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.647935576
Short name T787
Test name
Test status
Simulation time 84823193 ps
CPU time 2.38 seconds
Started Mar 12 01:10:42 PM PDT 24
Finished Mar 12 01:10:45 PM PDT 24
Peak memory 233292 kb
Host smart-b3168c14-ca31-4b70-a410-bdad8741dc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647935576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.647935576
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1453259213
Short name T1237
Test name
Test status
Simulation time 17717727 ps
CPU time 0.76 seconds
Started Mar 12 03:05:37 PM PDT 24
Finished Mar 12 03:05:39 PM PDT 24
Peak memory 204932 kb
Host smart-c3f78ffe-134d-4034-a16d-3c2004898039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453259213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1453259213
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2244218796
Short name T1043
Test name
Test status
Simulation time 29405496 ps
CPU time 0.71 seconds
Started Mar 12 01:10:27 PM PDT 24
Finished Mar 12 01:10:28 PM PDT 24
Peak memory 204788 kb
Host smart-665276cb-cf4d-40ac-94f1-3deb60614202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244218796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2244218796
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.2331506485
Short name T1357
Test name
Test status
Simulation time 64951393219 ps
CPU time 86.28 seconds
Started Mar 12 01:10:48 PM PDT 24
Finished Mar 12 01:12:14 PM PDT 24
Peak memory 240640 kb
Host smart-d5a6e714-e367-4317-bc69-a233439758dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331506485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2331506485
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.83204140
Short name T1840
Test name
Test status
Simulation time 3627973875 ps
CPU time 22.59 seconds
Started Mar 12 03:05:38 PM PDT 24
Finished Mar 12 03:06:01 PM PDT 24
Peak memory 248336 kb
Host smart-3dd5dc38-b703-44aa-82fe-018bc816ed2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83204140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.83204140
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1275341590
Short name T881
Test name
Test status
Simulation time 36860571832 ps
CPU time 125.95 seconds
Started Mar 12 03:05:50 PM PDT 24
Finished Mar 12 03:07:56 PM PDT 24
Peak memory 233816 kb
Host smart-8bbf298b-3f07-4e1e-b67f-2b677872e0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275341590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1275341590
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.248093924
Short name T1706
Test name
Test status
Simulation time 371121731915 ps
CPU time 257.16 seconds
Started Mar 12 01:10:46 PM PDT 24
Finished Mar 12 01:15:03 PM PDT 24
Peak memory 257164 kb
Host smart-82779ac2-339f-4d83-9ff5-c52c2cfdf591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248093924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.248093924
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.300056105
Short name T1012
Test name
Test status
Simulation time 136224502005 ps
CPU time 157.57 seconds
Started Mar 12 01:10:39 PM PDT 24
Finished Mar 12 01:13:17 PM PDT 24
Peak memory 261680 kb
Host smart-dcadda8d-8c14-4293-b050-d52432661c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300056105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
300056105
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.520974079
Short name T1825
Test name
Test status
Simulation time 6979979782 ps
CPU time 101.89 seconds
Started Mar 12 03:05:50 PM PDT 24
Finished Mar 12 03:07:32 PM PDT 24
Peak memory 248996 kb
Host smart-107b1641-ff24-471c-9d23-81e0d9829c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520974079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
520974079
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1584557004
Short name T1054
Test name
Test status
Simulation time 1028953934 ps
CPU time 6.95 seconds
Started Mar 12 01:10:45 PM PDT 24
Finished Mar 12 01:10:52 PM PDT 24
Peak memory 240360 kb
Host smart-1f6d4367-0bb1-4e08-bdf0-85d0cd1663a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584557004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1584557004
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3429689176
Short name T557
Test name
Test status
Simulation time 1628126750 ps
CPU time 13.93 seconds
Started Mar 12 03:05:37 PM PDT 24
Finished Mar 12 03:05:52 PM PDT 24
Peak memory 239568 kb
Host smart-fb54dfff-323e-4623-8510-4451237bae87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429689176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3429689176
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3579246059
Short name T561
Test name
Test status
Simulation time 2333713448 ps
CPU time 3.3 seconds
Started Mar 12 01:10:28 PM PDT 24
Finished Mar 12 01:10:31 PM PDT 24
Peak memory 224112 kb
Host smart-d39ffc7b-960c-4733-b62d-3fe19f9fab9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579246059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3579246059
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_intercept.609410692
Short name T1513
Test name
Test status
Simulation time 3311907838 ps
CPU time 6.91 seconds
Started Mar 12 03:05:35 PM PDT 24
Finished Mar 12 03:05:42 PM PDT 24
Peak memory 235016 kb
Host smart-35591e19-6450-4228-ab4b-ee35c0fc98ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609410692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.609410692
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2166233637
Short name T1851
Test name
Test status
Simulation time 12659027507 ps
CPU time 34.34 seconds
Started Mar 12 03:05:37 PM PDT 24
Finished Mar 12 03:06:12 PM PDT 24
Peak memory 240632 kb
Host smart-bd5f3e94-fec8-49b3-a6f2-cb283afdf645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166233637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2166233637
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.970957656
Short name T1783
Test name
Test status
Simulation time 3402205375 ps
CPU time 9.37 seconds
Started Mar 12 01:10:49 PM PDT 24
Finished Mar 12 01:10:59 PM PDT 24
Peak memory 232384 kb
Host smart-07876fd2-787d-4b6b-b647-080faee7f9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970957656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.970957656
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.1905355517
Short name T1757
Test name
Test status
Simulation time 27477133 ps
CPU time 1.05 seconds
Started Mar 12 01:10:30 PM PDT 24
Finished Mar 12 01:10:31 PM PDT 24
Peak memory 216340 kb
Host smart-0c1bd6ae-5374-4816-848c-02f2eb855a64
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905355517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.1905355517
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.458774345
Short name T968
Test name
Test status
Simulation time 129564567 ps
CPU time 1.12 seconds
Started Mar 12 03:05:36 PM PDT 24
Finished Mar 12 03:05:38 PM PDT 24
Peak memory 216344 kb
Host smart-8769a88e-f620-4ad3-83b9-752030f6c341
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458774345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.spi_device_mem_parity.458774345
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.181509280
Short name T1171
Test name
Test status
Simulation time 1488843767 ps
CPU time 4.6 seconds
Started Mar 12 03:05:38 PM PDT 24
Finished Mar 12 03:05:43 PM PDT 24
Peak memory 233148 kb
Host smart-f0e4e7d7-5540-4c7a-b340-85f017ed89f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181509280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
181509280
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.4038543759
Short name T556
Test name
Test status
Simulation time 6932088190 ps
CPU time 13.8 seconds
Started Mar 12 01:10:27 PM PDT 24
Finished Mar 12 01:10:41 PM PDT 24
Peak memory 232748 kb
Host smart-8d666377-7e02-487d-953c-6222d49d2ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038543759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.4038543759
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.1994500082
Short name T821
Test name
Test status
Simulation time 3785810253 ps
CPU time 13.18 seconds
Started Mar 12 03:05:42 PM PDT 24
Finished Mar 12 03:05:55 PM PDT 24
Peak memory 233324 kb
Host smart-c25b2510-9a20-438b-b13b-8cc01364f115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994500082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1994500082
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3777017385
Short name T697
Test name
Test status
Simulation time 46393199200 ps
CPU time 35.99 seconds
Started Mar 12 01:10:29 PM PDT 24
Finished Mar 12 01:11:05 PM PDT 24
Peak memory 238352 kb
Host smart-7f9567dc-f937-4464-9769-5a4e7b7052ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777017385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3777017385
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.2261634448
Short name T578
Test name
Test status
Simulation time 24881826 ps
CPU time 0.79 seconds
Started Mar 12 03:05:59 PM PDT 24
Finished Mar 12 03:06:02 PM PDT 24
Peak memory 215752 kb
Host smart-e0e87e7a-bb17-4bb4-89e6-919b66c12440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261634448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.2261634448
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.822364062
Short name T1269
Test name
Test status
Simulation time 29464318 ps
CPU time 0.7 seconds
Started Mar 12 01:10:29 PM PDT 24
Finished Mar 12 01:10:30 PM PDT 24
Peak memory 215972 kb
Host smart-7fb72f98-2bb4-4669-97c1-c8ef6ec84d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822364062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.822364062
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2033672524
Short name T806
Test name
Test status
Simulation time 1057369463 ps
CPU time 4.55 seconds
Started Mar 12 01:10:43 PM PDT 24
Finished Mar 12 01:10:48 PM PDT 24
Peak memory 218072 kb
Host smart-886b1ac6-c711-46ef-b697-6284edef3e54
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2033672524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2033672524
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2280715561
Short name T1663
Test name
Test status
Simulation time 909608030 ps
CPU time 4.55 seconds
Started Mar 12 03:05:37 PM PDT 24
Finished Mar 12 03:05:42 PM PDT 24
Peak memory 221840 kb
Host smart-e8296a7f-de3a-4e1b-b0f9-0152540d2329
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2280715561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2280715561
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3902706612
Short name T72
Test name
Test status
Simulation time 35185228 ps
CPU time 0.98 seconds
Started Mar 12 01:10:43 PM PDT 24
Finished Mar 12 01:10:44 PM PDT 24
Peak memory 234200 kb
Host smart-11745798-99f2-4680-8b38-6e571755c1aa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902706612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3902706612
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.4211899633
Short name T66
Test name
Test status
Simulation time 332543803 ps
CPU time 1.12 seconds
Started Mar 12 03:05:49 PM PDT 24
Finished Mar 12 03:05:50 PM PDT 24
Peak memory 235196 kb
Host smart-ea0fb6f4-ca00-41b4-b8eb-c477a802054b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211899633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.4211899633
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1064709415
Short name T1145
Test name
Test status
Simulation time 82957604001 ps
CPU time 173.18 seconds
Started Mar 12 03:05:50 PM PDT 24
Finished Mar 12 03:08:43 PM PDT 24
Peak memory 270560 kb
Host smart-1685a163-9c3b-4eab-aa4b-9625c29434f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064709415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1064709415
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3213488767
Short name T981
Test name
Test status
Simulation time 32309397 ps
CPU time 0.93 seconds
Started Mar 12 01:10:47 PM PDT 24
Finished Mar 12 01:10:48 PM PDT 24
Peak memory 206068 kb
Host smart-3e044884-4fb6-4015-b9ef-905505fdc898
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213488767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3213488767
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1512744815
Short name T668
Test name
Test status
Simulation time 1856850605 ps
CPU time 3.45 seconds
Started Mar 12 03:05:36 PM PDT 24
Finished Mar 12 03:05:40 PM PDT 24
Peak memory 216032 kb
Host smart-76b058c4-3da2-4102-a1dd-2d6e32908767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512744815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1512744815
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2721597985
Short name T1096
Test name
Test status
Simulation time 1032817884 ps
CPU time 8.8 seconds
Started Mar 12 01:10:26 PM PDT 24
Finished Mar 12 01:10:36 PM PDT 24
Peak memory 218056 kb
Host smart-519f0869-55af-439d-af7c-2cf298d16361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721597985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2721597985
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1943379642
Short name T694
Test name
Test status
Simulation time 5511827274 ps
CPU time 8.93 seconds
Started Mar 12 01:10:28 PM PDT 24
Finished Mar 12 01:10:38 PM PDT 24
Peak memory 216068 kb
Host smart-323d4976-03cb-4376-8c0b-f12cd8133c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943379642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1943379642
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3707914
Short name T763
Test name
Test status
Simulation time 481910409 ps
CPU time 3.59 seconds
Started Mar 12 03:05:39 PM PDT 24
Finished Mar 12 03:05:43 PM PDT 24
Peak memory 216124 kb
Host smart-9d218d01-46be-4bdf-b240-b0a53871c074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3707914
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1999002904
Short name T1721
Test name
Test status
Simulation time 114214885 ps
CPU time 1.74 seconds
Started Mar 12 01:10:29 PM PDT 24
Finished Mar 12 01:10:31 PM PDT 24
Peak memory 216020 kb
Host smart-67e2dadb-00fe-4ed5-b3c7-8f0c258c30c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999002904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1999002904
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2832423664
Short name T45
Test name
Test status
Simulation time 295473367 ps
CPU time 2.9 seconds
Started Mar 12 03:05:38 PM PDT 24
Finished Mar 12 03:05:41 PM PDT 24
Peak memory 216192 kb
Host smart-643bdf31-2b9f-4f38-bbd1-b31e22ddad46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832423664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2832423664
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.317022300
Short name T470
Test name
Test status
Simulation time 204686756 ps
CPU time 0.94 seconds
Started Mar 12 03:05:37 PM PDT 24
Finished Mar 12 03:05:38 PM PDT 24
Peak memory 206076 kb
Host smart-7a8e1abd-ab37-4514-878a-18802e3221f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317022300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.317022300
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.982905098
Short name T569
Test name
Test status
Simulation time 211035706 ps
CPU time 0.72 seconds
Started Mar 12 01:10:27 PM PDT 24
Finished Mar 12 01:10:28 PM PDT 24
Peak memory 205208 kb
Host smart-87970231-82cf-4e13-a2ce-48f71a7fd7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982905098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.982905098
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.1463078265
Short name T1691
Test name
Test status
Simulation time 2089384789 ps
CPU time 11.29 seconds
Started Mar 12 01:10:48 PM PDT 24
Finished Mar 12 01:10:59 PM PDT 24
Peak memory 230676 kb
Host smart-af47d227-0344-4370-8b49-845f8041d499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463078265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1463078265
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_upload.3937079515
Short name T1739
Test name
Test status
Simulation time 447493503 ps
CPU time 7.8 seconds
Started Mar 12 03:05:37 PM PDT 24
Finished Mar 12 03:05:45 PM PDT 24
Peak memory 234972 kb
Host smart-05ef8063-a10b-4826-9f50-fe87fc41be19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937079515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3937079515
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1685508171
Short name T1259
Test name
Test status
Simulation time 38592481 ps
CPU time 0.66 seconds
Started Mar 12 03:10:15 PM PDT 24
Finished Mar 12 03:10:16 PM PDT 24
Peak memory 204596 kb
Host smart-46f6d38a-f4cb-42c5-9c8f-a606ff642b85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685508171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1685508171
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.4109390989
Short name T162
Test name
Test status
Simulation time 13887469 ps
CPU time 0.69 seconds
Started Mar 12 01:12:46 PM PDT 24
Finished Mar 12 01:12:47 PM PDT 24
Peak memory 204824 kb
Host smart-9df4526c-ee5a-4acb-8d63-70e4ccc38246
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109390989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
4109390989
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1853985815
Short name T250
Test name
Test status
Simulation time 592638112 ps
CPU time 5.3 seconds
Started Mar 12 03:10:13 PM PDT 24
Finished Mar 12 03:10:20 PM PDT 24
Peak memory 233824 kb
Host smart-ab9cee8c-70cf-4e87-bd5c-ce3db01c2e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853985815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1853985815
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.78784973
Short name T239
Test name
Test status
Simulation time 56173950 ps
CPU time 2.18 seconds
Started Mar 12 01:12:47 PM PDT 24
Finished Mar 12 01:12:50 PM PDT 24
Peak memory 216316 kb
Host smart-d1f24ab7-a18c-42c1-a8f5-f65e6c2fd026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78784973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.78784973
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3046181918
Short name T1014
Test name
Test status
Simulation time 18791022 ps
CPU time 0.79 seconds
Started Mar 12 01:12:45 PM PDT 24
Finished Mar 12 01:12:46 PM PDT 24
Peak memory 205908 kb
Host smart-4faebb87-42e5-433d-b910-f2ff56a14609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046181918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3046181918
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.4179106501
Short name T1758
Test name
Test status
Simulation time 20239169 ps
CPU time 0.73 seconds
Started Mar 12 03:10:15 PM PDT 24
Finished Mar 12 03:10:16 PM PDT 24
Peak memory 204688 kb
Host smart-eecfaffe-5162-4146-8f2a-dd892829e499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179106501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.4179106501
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2728558666
Short name T291
Test name
Test status
Simulation time 29525189761 ps
CPU time 129.61 seconds
Started Mar 12 01:12:48 PM PDT 24
Finished Mar 12 01:14:58 PM PDT 24
Peak memory 264332 kb
Host smart-9743c4e9-b84a-4265-8441-b01db11f3d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728558666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2728558666
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3465514940
Short name T412
Test name
Test status
Simulation time 38732991571 ps
CPU time 102.82 seconds
Started Mar 12 03:10:12 PM PDT 24
Finished Mar 12 03:11:57 PM PDT 24
Peak memory 256056 kb
Host smart-187c6a7b-b0b8-4ce7-aafc-bfcb3c6640a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465514940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3465514940
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1271406229
Short name T1333
Test name
Test status
Simulation time 210242323771 ps
CPU time 402.29 seconds
Started Mar 12 03:10:11 PM PDT 24
Finished Mar 12 03:16:56 PM PDT 24
Peak memory 256004 kb
Host smart-3f9de12b-7346-41ff-8d04-200ce182a9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271406229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1271406229
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.587925784
Short name T1806
Test name
Test status
Simulation time 63415754098 ps
CPU time 76.44 seconds
Started Mar 12 01:12:46 PM PDT 24
Finished Mar 12 01:14:02 PM PDT 24
Peak memory 233668 kb
Host smart-70cbe0c9-dabe-420e-b10b-27a9cf441702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587925784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.587925784
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1222900216
Short name T252
Test name
Test status
Simulation time 134782659056 ps
CPU time 442.66 seconds
Started Mar 12 03:10:15 PM PDT 24
Finished Mar 12 03:17:38 PM PDT 24
Peak memory 256904 kb
Host smart-7ad10232-3611-4749-88a1-b05aa538c279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222900216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1222900216
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2747617658
Short name T1301
Test name
Test status
Simulation time 27232589356 ps
CPU time 61.36 seconds
Started Mar 12 01:12:47 PM PDT 24
Finished Mar 12 01:13:48 PM PDT 24
Peak memory 234972 kb
Host smart-2c9b1109-e161-46a7-b0ba-7ceb33afdd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747617658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2747617658
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1554876872
Short name T689
Test name
Test status
Simulation time 22530424887 ps
CPU time 27.37 seconds
Started Mar 12 03:10:14 PM PDT 24
Finished Mar 12 03:10:42 PM PDT 24
Peak memory 239764 kb
Host smart-6adcaf60-2d20-4ebf-868a-87fa29d14bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554876872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1554876872
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1915250646
Short name T946
Test name
Test status
Simulation time 784557509 ps
CPU time 10.23 seconds
Started Mar 12 01:12:46 PM PDT 24
Finished Mar 12 01:12:56 PM PDT 24
Peak memory 224184 kb
Host smart-76743e35-a67c-441f-aad9-cf6c4849fa56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915250646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1915250646
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2788462175
Short name T714
Test name
Test status
Simulation time 152560832 ps
CPU time 4 seconds
Started Mar 12 01:12:45 PM PDT 24
Finished Mar 12 01:12:49 PM PDT 24
Peak memory 218788 kb
Host smart-7d0333e3-0dae-499e-8fbe-2f8e011b7f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788462175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2788462175
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_intercept.379587758
Short name T1139
Test name
Test status
Simulation time 203237953 ps
CPU time 4.61 seconds
Started Mar 12 03:10:09 PM PDT 24
Finished Mar 12 03:10:15 PM PDT 24
Peak memory 234052 kb
Host smart-ca95b31b-33b5-4912-a676-f297ae7454bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379587758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.379587758
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1497048387
Short name T1687
Test name
Test status
Simulation time 725295405 ps
CPU time 13.08 seconds
Started Mar 12 01:12:46 PM PDT 24
Finished Mar 12 01:12:59 PM PDT 24
Peak memory 240564 kb
Host smart-598e52c3-9c0c-4ac6-b72a-c68930372020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497048387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1497048387
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.4023155390
Short name T163
Test name
Test status
Simulation time 354994475 ps
CPU time 2.57 seconds
Started Mar 12 03:10:16 PM PDT 24
Finished Mar 12 03:10:19 PM PDT 24
Peak memory 223952 kb
Host smart-77948453-e4f3-44b2-96f2-7fea45540482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023155390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.4023155390
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2573780243
Short name T1597
Test name
Test status
Simulation time 7142715208 ps
CPU time 8.05 seconds
Started Mar 12 01:12:48 PM PDT 24
Finished Mar 12 01:12:57 PM PDT 24
Peak memory 233332 kb
Host smart-50a3c64d-0f8b-4b37-b005-ae9d7b4b930e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573780243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2573780243
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.50368147
Short name T955
Test name
Test status
Simulation time 39680403884 ps
CPU time 13.18 seconds
Started Mar 12 03:10:13 PM PDT 24
Finished Mar 12 03:10:28 PM PDT 24
Peak memory 219128 kb
Host smart-99c23ee6-fd5e-413a-9aaf-1d322dc0e0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50368147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap.50368147
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1762644505
Short name T1695
Test name
Test status
Simulation time 2345384403 ps
CPU time 4.64 seconds
Started Mar 12 01:12:35 PM PDT 24
Finished Mar 12 01:12:40 PM PDT 24
Peak memory 216456 kb
Host smart-b2a6a380-adb1-4a75-93f5-818934612727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762644505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1762644505
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.427219271
Short name T1172
Test name
Test status
Simulation time 1486812996 ps
CPU time 7.81 seconds
Started Mar 12 03:10:10 PM PDT 24
Finished Mar 12 03:10:21 PM PDT 24
Peak memory 237100 kb
Host smart-9b570442-b3a3-4c49-bf63-25c34e821187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427219271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.427219271
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2151255279
Short name T1487
Test name
Test status
Simulation time 374707369 ps
CPU time 3.89 seconds
Started Mar 12 03:10:09 PM PDT 24
Finished Mar 12 03:10:17 PM PDT 24
Peak memory 221320 kb
Host smart-cde3d49c-aaea-423e-a835-11fb66af1c58
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2151255279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2151255279
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3733087291
Short name T1730
Test name
Test status
Simulation time 884775313 ps
CPU time 4.34 seconds
Started Mar 12 01:12:35 PM PDT 24
Finished Mar 12 01:12:39 PM PDT 24
Peak memory 222304 kb
Host smart-7fca3582-63fe-4e15-b90f-a660a086def1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3733087291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3733087291
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.593999217
Short name T160
Test name
Test status
Simulation time 13037307957 ps
CPU time 80.69 seconds
Started Mar 12 03:10:13 PM PDT 24
Finished Mar 12 03:11:35 PM PDT 24
Peak memory 248160 kb
Host smart-d9fa56d4-8390-4e88-8050-2a7311db3e5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593999217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres
s_all.593999217
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2052050295
Short name T1770
Test name
Test status
Simulation time 3099675388 ps
CPU time 24.56 seconds
Started Mar 12 03:10:12 PM PDT 24
Finished Mar 12 03:10:39 PM PDT 24
Peak memory 216092 kb
Host smart-05966ec5-b425-4628-b268-664641563bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052050295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2052050295
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.92980158
Short name T1159
Test name
Test status
Simulation time 839463166 ps
CPU time 7.37 seconds
Started Mar 12 01:12:37 PM PDT 24
Finished Mar 12 01:12:44 PM PDT 24
Peak memory 215940 kb
Host smart-be06a8be-a8e5-43e9-ad64-9c69d93dd4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92980158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.92980158
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2199066421
Short name T411
Test name
Test status
Simulation time 462799723 ps
CPU time 3.15 seconds
Started Mar 12 03:10:07 PM PDT 24
Finished Mar 12 03:10:11 PM PDT 24
Peak memory 215852 kb
Host smart-fc5e741a-31a1-40a3-bc18-fc2e4063f23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199066421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2199066421
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3729462354
Short name T1394
Test name
Test status
Simulation time 41222041138 ps
CPU time 22.19 seconds
Started Mar 12 01:12:34 PM PDT 24
Finished Mar 12 01:12:56 PM PDT 24
Peak memory 215996 kb
Host smart-4aec9ee1-bbfc-48ad-896d-684e9af30a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729462354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3729462354
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2194104419
Short name T1529
Test name
Test status
Simulation time 23377126 ps
CPU time 0.75 seconds
Started Mar 12 01:12:39 PM PDT 24
Finished Mar 12 01:12:40 PM PDT 24
Peak memory 205252 kb
Host smart-98f84958-e084-4070-bd97-64944ba428ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194104419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2194104419
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3344724948
Short name T779
Test name
Test status
Simulation time 84301667 ps
CPU time 4.51 seconds
Started Mar 12 03:10:11 PM PDT 24
Finished Mar 12 03:10:19 PM PDT 24
Peak memory 216256 kb
Host smart-369036a8-fa23-4cc1-aa3a-246dc3fb0b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344724948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3344724948
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2767224724
Short name T1622
Test name
Test status
Simulation time 68580745 ps
CPU time 0.83 seconds
Started Mar 12 01:12:33 PM PDT 24
Finished Mar 12 01:12:34 PM PDT 24
Peak memory 205236 kb
Host smart-152086e1-03ef-4d4a-8118-66228906c370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767224724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2767224724
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.555599828
Short name T1886
Test name
Test status
Simulation time 275916864 ps
CPU time 0.98 seconds
Started Mar 12 03:10:07 PM PDT 24
Finished Mar 12 03:10:09 PM PDT 24
Peak memory 206252 kb
Host smart-4b9c1996-8c25-4904-85e1-fdb6401ea994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555599828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.555599828
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.169049388
Short name T1330
Test name
Test status
Simulation time 1176925278 ps
CPU time 8.06 seconds
Started Mar 12 03:10:11 PM PDT 24
Finished Mar 12 03:10:22 PM PDT 24
Peak memory 229540 kb
Host smart-a9e2e4ee-937a-4c3f-95ce-636aa3e8a330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169049388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.169049388
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_upload.243365980
Short name T32
Test name
Test status
Simulation time 10944297802 ps
CPU time 24.26 seconds
Started Mar 12 01:12:46 PM PDT 24
Finished Mar 12 01:13:10 PM PDT 24
Peak memory 232196 kb
Host smart-b2d379b6-1103-4ad3-9c5c-8bb67f7973ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243365980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.243365980
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1620830041
Short name T532
Test name
Test status
Simulation time 28505609 ps
CPU time 0.72 seconds
Started Mar 12 03:10:14 PM PDT 24
Finished Mar 12 03:10:15 PM PDT 24
Peak memory 203672 kb
Host smart-d1daae29-050d-40e1-a9ef-d0ffa2a61e4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620830041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1620830041
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3090679811
Short name T607
Test name
Test status
Simulation time 14620903 ps
CPU time 0.69 seconds
Started Mar 12 01:12:40 PM PDT 24
Finished Mar 12 01:12:41 PM PDT 24
Peak memory 204668 kb
Host smart-f4e76472-fcae-49be-85d5-e81b77515170
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090679811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3090679811
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3848306605
Short name T1822
Test name
Test status
Simulation time 1406175227 ps
CPU time 5.25 seconds
Started Mar 12 03:10:10 PM PDT 24
Finished Mar 12 03:10:19 PM PDT 24
Peak memory 224104 kb
Host smart-47a09459-b21d-48bf-8aeb-500707a2f55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848306605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3848306605
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.594579020
Short name T1899
Test name
Test status
Simulation time 966333587 ps
CPU time 3.48 seconds
Started Mar 12 01:12:34 PM PDT 24
Finished Mar 12 01:12:37 PM PDT 24
Peak memory 233368 kb
Host smart-244916ef-43e8-4039-852e-c76d98a135f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594579020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.594579020
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1188881041
Short name T1290
Test name
Test status
Simulation time 15817360 ps
CPU time 0.75 seconds
Started Mar 12 01:12:46 PM PDT 24
Finished Mar 12 01:12:47 PM PDT 24
Peak memory 204872 kb
Host smart-5896181c-1df5-45ea-be92-485dccef62bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188881041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1188881041
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2088642169
Short name T409
Test name
Test status
Simulation time 47695725 ps
CPU time 0.77 seconds
Started Mar 12 03:10:11 PM PDT 24
Finished Mar 12 03:10:15 PM PDT 24
Peak memory 206256 kb
Host smart-c1122f2f-6f8b-4ec5-b82b-8a0e1de5251c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088642169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2088642169
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1252319431
Short name T1741
Test name
Test status
Simulation time 175005797 ps
CPU time 4.29 seconds
Started Mar 12 01:12:46 PM PDT 24
Finished Mar 12 01:12:50 PM PDT 24
Peak memory 235584 kb
Host smart-e9e024fc-d9a8-440a-9da8-8dae5a43d877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252319431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1252319431
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.4202356765
Short name T536
Test name
Test status
Simulation time 43055659944 ps
CPU time 49.14 seconds
Started Mar 12 03:10:12 PM PDT 24
Finished Mar 12 03:11:03 PM PDT 24
Peak memory 251016 kb
Host smart-31832bec-56ec-4a7e-b89a-6132ff07012c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202356765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.4202356765
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2713344680
Short name T801
Test name
Test status
Simulation time 11325490457 ps
CPU time 151.71 seconds
Started Mar 12 03:10:13 PM PDT 24
Finished Mar 12 03:12:46 PM PDT 24
Peak memory 268656 kb
Host smart-36df053a-df52-4e11-9092-f64604102620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713344680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2713344680
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2722890713
Short name T1626
Test name
Test status
Simulation time 94986552058 ps
CPU time 294.49 seconds
Started Mar 12 01:12:39 PM PDT 24
Finished Mar 12 01:17:34 PM PDT 24
Peak memory 265368 kb
Host smart-1abb4dfa-6ac5-4a94-a0fc-7806a9ce7895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722890713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2722890713
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1464465033
Short name T1144
Test name
Test status
Simulation time 18244994824 ps
CPU time 132.17 seconds
Started Mar 12 01:12:44 PM PDT 24
Finished Mar 12 01:14:56 PM PDT 24
Peak memory 233360 kb
Host smart-eef9b14b-9eb7-4cc7-907f-9688ac1f5cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464465033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1464465033
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.666422109
Short name T217
Test name
Test status
Simulation time 117585846883 ps
CPU time 213.05 seconds
Started Mar 12 03:10:07 PM PDT 24
Finished Mar 12 03:13:41 PM PDT 24
Peak memory 255816 kb
Host smart-ae53a648-da60-4b85-bc53-8cbfedfa8b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666422109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle
.666422109
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2691244521
Short name T687
Test name
Test status
Simulation time 9603818977 ps
CPU time 26.41 seconds
Started Mar 12 01:12:48 PM PDT 24
Finished Mar 12 01:13:15 PM PDT 24
Peak memory 238008 kb
Host smart-faf30822-c4bd-47cc-a305-8e77feca01c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691244521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2691244521
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.746098084
Short name T1884
Test name
Test status
Simulation time 1051764710 ps
CPU time 14.49 seconds
Started Mar 12 03:10:13 PM PDT 24
Finished Mar 12 03:10:29 PM PDT 24
Peak memory 240304 kb
Host smart-1555c6b7-3bf0-46ae-8fca-bcba64d02e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746098084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.746098084
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1184924190
Short name T1386
Test name
Test status
Simulation time 552116544 ps
CPU time 5.46 seconds
Started Mar 12 03:10:14 PM PDT 24
Finished Mar 12 03:10:20 PM PDT 24
Peak memory 219572 kb
Host smart-6a5bc008-9273-420d-988e-fa5f68050a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184924190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1184924190
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3028319509
Short name T1720
Test name
Test status
Simulation time 2525424079 ps
CPU time 7.75 seconds
Started Mar 12 01:12:48 PM PDT 24
Finished Mar 12 01:12:56 PM PDT 24
Peak memory 234752 kb
Host smart-bf8a520c-78b6-46d0-a06c-2013fdec7641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028319509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3028319509
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1795798073
Short name T1512
Test name
Test status
Simulation time 7851934920 ps
CPU time 5.56 seconds
Started Mar 12 01:12:48 PM PDT 24
Finished Mar 12 01:12:54 PM PDT 24
Peak memory 232292 kb
Host smart-d76ca5dd-fa41-4f99-b929-97e554f60565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795798073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1795798073
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3760520574
Short name T327
Test name
Test status
Simulation time 227107688 ps
CPU time 3.12 seconds
Started Mar 12 03:10:12 PM PDT 24
Finished Mar 12 03:10:18 PM PDT 24
Peak memory 232404 kb
Host smart-c320aea6-317c-46b8-bf0a-9f975e63a7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760520574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3760520574
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1296931864
Short name T1188
Test name
Test status
Simulation time 810242414 ps
CPU time 4.16 seconds
Started Mar 12 03:10:11 PM PDT 24
Finished Mar 12 03:10:18 PM PDT 24
Peak memory 236112 kb
Host smart-58d02699-8bc6-4f2a-bda2-45c5e46d05a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296931864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1296931864
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1666082978
Short name T959
Test name
Test status
Simulation time 10025212568 ps
CPU time 28.37 seconds
Started Mar 12 01:12:49 PM PDT 24
Finished Mar 12 01:13:18 PM PDT 24
Peak memory 217500 kb
Host smart-6e65ca29-66cd-4cc8-bb0a-1c53f91fb563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666082978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1666082978
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1146954230
Short name T3
Test name
Test status
Simulation time 56186644511 ps
CPU time 40.61 seconds
Started Mar 12 03:10:11 PM PDT 24
Finished Mar 12 03:10:55 PM PDT 24
Peak memory 235672 kb
Host smart-af80cfbe-9fbb-464e-bd71-bc7c1e77b156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146954230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1146954230
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3138439160
Short name T977
Test name
Test status
Simulation time 818699376 ps
CPU time 7.87 seconds
Started Mar 12 01:12:38 PM PDT 24
Finished Mar 12 01:12:46 PM PDT 24
Peak memory 232704 kb
Host smart-36457089-cdbd-4996-bb2a-9e7d4b187a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138439160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3138439160
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3330689572
Short name T1892
Test name
Test status
Simulation time 1282926328 ps
CPU time 3.79 seconds
Started Mar 12 03:10:14 PM PDT 24
Finished Mar 12 03:10:18 PM PDT 24
Peak memory 221624 kb
Host smart-4bfc2df0-2d49-4366-98a5-ba0630f5e9c9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3330689572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3330689572
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.4150463811
Short name T1520
Test name
Test status
Simulation time 864116679 ps
CPU time 5.29 seconds
Started Mar 12 01:12:45 PM PDT 24
Finished Mar 12 01:12:51 PM PDT 24
Peak memory 218348 kb
Host smart-eb46216e-5791-4631-ac91-9852db499b56
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4150463811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.4150463811
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.1221271342
Short name T1550
Test name
Test status
Simulation time 108708748 ps
CPU time 1.08 seconds
Started Mar 12 03:10:12 PM PDT 24
Finished Mar 12 03:10:15 PM PDT 24
Peak memory 206544 kb
Host smart-28af0a3c-bc64-4748-b92c-1dc8fd2bf083
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221271342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.1221271342
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.494872652
Short name T318
Test name
Test status
Simulation time 6284031308 ps
CPU time 8.68 seconds
Started Mar 12 01:12:42 PM PDT 24
Finished Mar 12 01:12:50 PM PDT 24
Peak memory 216160 kb
Host smart-2175dd67-5b7a-448a-b19b-1ca22d78a995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494872652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.494872652
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.627879253
Short name T706
Test name
Test status
Simulation time 3808103313 ps
CPU time 27.16 seconds
Started Mar 12 03:10:12 PM PDT 24
Finished Mar 12 03:10:41 PM PDT 24
Peak memory 216088 kb
Host smart-c5390cf7-a72f-4e1f-ae6e-030f881374ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627879253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.627879253
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.650681379
Short name T323
Test name
Test status
Simulation time 5303437692 ps
CPU time 14.64 seconds
Started Mar 12 01:12:48 PM PDT 24
Finished Mar 12 01:13:03 PM PDT 24
Peak memory 216584 kb
Host smart-1ce0121b-03ea-4673-831c-0701b166b39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650681379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.650681379
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.947607742
Short name T1722
Test name
Test status
Simulation time 5545680182 ps
CPU time 15.3 seconds
Started Mar 12 03:10:09 PM PDT 24
Finished Mar 12 03:10:28 PM PDT 24
Peak memory 215624 kb
Host smart-6010ad9a-9422-4c59-9aeb-dc5be15c76a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947607742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.947607742
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1367850444
Short name T1864
Test name
Test status
Simulation time 88155682 ps
CPU time 1.37 seconds
Started Mar 12 01:12:47 PM PDT 24
Finished Mar 12 01:12:49 PM PDT 24
Peak memory 216052 kb
Host smart-14f0e18e-c2a1-4477-8d98-336587199712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367850444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1367850444
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2552271060
Short name T1160
Test name
Test status
Simulation time 2945588929 ps
CPU time 3.78 seconds
Started Mar 12 03:10:09 PM PDT 24
Finished Mar 12 03:10:15 PM PDT 24
Peak memory 216200 kb
Host smart-d8e70763-2eed-4a9e-b81b-cd35fed9cf5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552271060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2552271060
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3634363014
Short name T1753
Test name
Test status
Simulation time 29439185 ps
CPU time 0.7 seconds
Started Mar 12 03:10:14 PM PDT 24
Finished Mar 12 03:10:15 PM PDT 24
Peak memory 205116 kb
Host smart-8c3a1365-bfdf-4c1a-97e0-d4c064aa86dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634363014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3634363014
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.807539526
Short name T1125
Test name
Test status
Simulation time 177838914 ps
CPU time 0.82 seconds
Started Mar 12 01:12:46 PM PDT 24
Finished Mar 12 01:12:47 PM PDT 24
Peak memory 204968 kb
Host smart-240e0e8d-2b6a-4e0b-aec7-448b903669e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807539526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.807539526
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.112883011
Short name T1272
Test name
Test status
Simulation time 2689121194 ps
CPU time 6.56 seconds
Started Mar 12 01:12:44 PM PDT 24
Finished Mar 12 01:12:51 PM PDT 24
Peak memory 233764 kb
Host smart-d48a272b-77fc-443d-b2f8-08f3fb3ba63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112883011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.112883011
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_upload.1271401438
Short name T908
Test name
Test status
Simulation time 1241860798 ps
CPU time 7.91 seconds
Started Mar 12 03:10:09 PM PDT 24
Finished Mar 12 03:10:17 PM PDT 24
Peak memory 239588 kb
Host smart-e010b874-cb26-4828-a8a0-fb6713584a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271401438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1271401438
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.841290111
Short name T1870
Test name
Test status
Simulation time 77023011 ps
CPU time 0.7 seconds
Started Mar 12 03:10:25 PM PDT 24
Finished Mar 12 03:10:26 PM PDT 24
Peak memory 204256 kb
Host smart-9716f362-a2b0-4213-8046-d9eb4878aaef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841290111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.841290111
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.988361972
Short name T1390
Test name
Test status
Simulation time 14173785 ps
CPU time 0.74 seconds
Started Mar 12 01:12:47 PM PDT 24
Finished Mar 12 01:12:48 PM PDT 24
Peak memory 204796 kb
Host smart-9f376b36-c406-4f0a-a6de-ba97e0f50d53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988361972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.988361972
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2672561307
Short name T814
Test name
Test status
Simulation time 14437866227 ps
CPU time 10.07 seconds
Started Mar 12 03:10:14 PM PDT 24
Finished Mar 12 03:10:25 PM PDT 24
Peak memory 233152 kb
Host smart-aa7634ac-7148-4cfd-834f-c87c845e6727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672561307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2672561307
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.4113765337
Short name T379
Test name
Test status
Simulation time 32449329 ps
CPU time 2.53 seconds
Started Mar 12 01:12:46 PM PDT 24
Finished Mar 12 01:12:49 PM PDT 24
Peak memory 233084 kb
Host smart-00f18a07-70a6-45e2-89d3-c73801ec3283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113765337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.4113765337
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2065605188
Short name T1645
Test name
Test status
Simulation time 162430764 ps
CPU time 0.77 seconds
Started Mar 12 01:12:36 PM PDT 24
Finished Mar 12 01:12:37 PM PDT 24
Peak memory 205768 kb
Host smart-1b6d56bf-d28f-457b-b4c7-a43d16a15f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065605188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2065605188
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.495025073
Short name T1170
Test name
Test status
Simulation time 16864133 ps
CPU time 0.77 seconds
Started Mar 12 03:10:13 PM PDT 24
Finished Mar 12 03:10:15 PM PDT 24
Peak memory 204948 kb
Host smart-885a3cbb-9863-44c4-825b-8b02f3e41c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495025073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.495025073
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3873832850
Short name T1051
Test name
Test status
Simulation time 110849280415 ps
CPU time 73.64 seconds
Started Mar 12 03:10:22 PM PDT 24
Finished Mar 12 03:11:37 PM PDT 24
Peak memory 240832 kb
Host smart-b0397200-d697-48aa-9786-f48667555859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873832850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3873832850
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.4141046072
Short name T433
Test name
Test status
Simulation time 68588245884 ps
CPU time 242.25 seconds
Started Mar 12 01:12:50 PM PDT 24
Finished Mar 12 01:16:52 PM PDT 24
Peak memory 250000 kb
Host smart-32a757e4-ef73-4fc4-a26b-5f39e26460f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141046072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.4141046072
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1887425394
Short name T309
Test name
Test status
Simulation time 310779517625 ps
CPU time 579.27 seconds
Started Mar 12 01:12:47 PM PDT 24
Finished Mar 12 01:22:27 PM PDT 24
Peak memory 273572 kb
Host smart-38137477-fac4-4f7b-a783-f521a6e8cc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887425394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1887425394
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.727541508
Short name T1463
Test name
Test status
Simulation time 98966237134 ps
CPU time 369.12 seconds
Started Mar 12 03:10:24 PM PDT 24
Finished Mar 12 03:16:34 PM PDT 24
Peak memory 250076 kb
Host smart-a4cc99a5-d053-4657-8e34-d9501949d641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727541508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle
.727541508
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.344859191
Short name T1136
Test name
Test status
Simulation time 8795700341 ps
CPU time 22.18 seconds
Started Mar 12 03:10:11 PM PDT 24
Finished Mar 12 03:10:36 PM PDT 24
Peak memory 234968 kb
Host smart-4a088f3e-3c97-4f70-8400-13491402bfde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344859191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.344859191
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3640584441
Short name T1400
Test name
Test status
Simulation time 19486326260 ps
CPU time 26.22 seconds
Started Mar 12 01:12:46 PM PDT 24
Finished Mar 12 01:13:12 PM PDT 24
Peak memory 235052 kb
Host smart-860c86e9-2fba-4a68-8864-6b5b9f627585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640584441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3640584441
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.248184990
Short name T857
Test name
Test status
Simulation time 2729408264 ps
CPU time 8.55 seconds
Started Mar 12 01:12:42 PM PDT 24
Finished Mar 12 01:12:51 PM PDT 24
Peak memory 224224 kb
Host smart-277bb5f4-100b-472b-92f8-933c51ce82ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248184990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.248184990
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3798470172
Short name T1138
Test name
Test status
Simulation time 150580903 ps
CPU time 2.96 seconds
Started Mar 12 03:10:08 PM PDT 24
Finished Mar 12 03:10:11 PM PDT 24
Peak memory 233880 kb
Host smart-de136a61-a15b-48df-bbdb-21777ba4cbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798470172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3798470172
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1919964210
Short name T1135
Test name
Test status
Simulation time 233699446 ps
CPU time 5.29 seconds
Started Mar 12 01:12:47 PM PDT 24
Finished Mar 12 01:12:52 PM PDT 24
Peak memory 233376 kb
Host smart-cfa54122-c3fd-4396-ade1-dab0214d1e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919964210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1919964210
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3995489699
Short name T1838
Test name
Test status
Simulation time 13429883048 ps
CPU time 19.08 seconds
Started Mar 12 03:10:14 PM PDT 24
Finished Mar 12 03:10:34 PM PDT 24
Peak memory 233264 kb
Host smart-cc1727c1-3971-49f6-8759-9668905341fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995489699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3995489699
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1099021738
Short name T269
Test name
Test status
Simulation time 9894292679 ps
CPU time 31.15 seconds
Started Mar 12 03:10:12 PM PDT 24
Finished Mar 12 03:10:46 PM PDT 24
Peak memory 234316 kb
Host smart-903c6e8d-30e2-43c4-b0b9-180d8feca458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099021738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1099021738
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3720630026
Short name T811
Test name
Test status
Simulation time 2131711641 ps
CPU time 8.41 seconds
Started Mar 12 01:12:42 PM PDT 24
Finished Mar 12 01:12:50 PM PDT 24
Peak memory 234380 kb
Host smart-1877e657-1c52-414b-9e03-7df13d66dfd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720630026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3720630026
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1641257830
Short name T1447
Test name
Test status
Simulation time 9706262237 ps
CPU time 25.36 seconds
Started Mar 12 03:10:16 PM PDT 24
Finished Mar 12 03:10:41 PM PDT 24
Peak memory 218940 kb
Host smart-2ca1bfb8-032d-4199-89dc-9de2c2ebad3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641257830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1641257830
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.236489283
Short name T1293
Test name
Test status
Simulation time 19516003262 ps
CPU time 13.23 seconds
Started Mar 12 01:12:44 PM PDT 24
Finished Mar 12 01:12:57 PM PDT 24
Peak memory 224192 kb
Host smart-54188f53-c0b8-413a-909f-58cd96d9129a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236489283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.236489283
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1650253895
Short name T1854
Test name
Test status
Simulation time 1948610835 ps
CPU time 4.43 seconds
Started Mar 12 01:12:43 PM PDT 24
Finished Mar 12 01:12:48 PM PDT 24
Peak memory 221720 kb
Host smart-6a77ecf5-82c5-45a3-aef3-e3f596718e35
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1650253895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1650253895
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3947804285
Short name T1385
Test name
Test status
Simulation time 894583453 ps
CPU time 4.5 seconds
Started Mar 12 03:10:12 PM PDT 24
Finished Mar 12 03:10:19 PM PDT 24
Peak memory 216144 kb
Host smart-0c06170f-803f-42d4-b1ca-7e1f21d5710a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3947804285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3947804285
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.173600095
Short name T1097
Test name
Test status
Simulation time 225043107 ps
CPU time 1.17 seconds
Started Mar 12 01:12:46 PM PDT 24
Finished Mar 12 01:12:47 PM PDT 24
Peak memory 206252 kb
Host smart-43171120-3db2-4064-a7a2-6da6c96453b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173600095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.173600095
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.796118860
Short name T156
Test name
Test status
Simulation time 1030550043 ps
CPU time 19.46 seconds
Started Mar 12 03:10:22 PM PDT 24
Finished Mar 12 03:10:43 PM PDT 24
Peak memory 235760 kb
Host smart-907622ea-e266-40d3-9a11-95fab4b11a49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796118860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.796118860
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1285868643
Short name T1889
Test name
Test status
Simulation time 3872891451 ps
CPU time 18.9 seconds
Started Mar 12 03:10:12 PM PDT 24
Finished Mar 12 03:10:33 PM PDT 24
Peak memory 216172 kb
Host smart-1cf98a82-7db5-4eae-a2eb-2ede2ff1d587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285868643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1285868643
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2842976066
Short name T407
Test name
Test status
Simulation time 8174638473 ps
CPU time 51.08 seconds
Started Mar 12 01:12:47 PM PDT 24
Finished Mar 12 01:13:39 PM PDT 24
Peak memory 216128 kb
Host smart-751855af-c00d-4c28-98f7-8e1054a08e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842976066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2842976066
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2270713607
Short name T1774
Test name
Test status
Simulation time 1296848498 ps
CPU time 3.65 seconds
Started Mar 12 01:12:45 PM PDT 24
Finished Mar 12 01:12:49 PM PDT 24
Peak memory 216004 kb
Host smart-3eed78e6-5066-4fed-acc3-acebf080cc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270713607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2270713607
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2371118796
Short name T1600
Test name
Test status
Simulation time 426236205 ps
CPU time 2.96 seconds
Started Mar 12 03:10:07 PM PDT 24
Finished Mar 12 03:10:10 PM PDT 24
Peak memory 207880 kb
Host smart-fb8f00a4-8f34-4cd1-9e83-b26d5294aae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371118796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2371118796
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1764178770
Short name T1843
Test name
Test status
Simulation time 691067593 ps
CPU time 8.21 seconds
Started Mar 12 03:10:12 PM PDT 24
Finished Mar 12 03:10:22 PM PDT 24
Peak memory 216100 kb
Host smart-6501fbed-e367-4275-8169-0d8b0a13db82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764178770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1764178770
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3808102234
Short name T1556
Test name
Test status
Simulation time 91057405 ps
CPU time 3.48 seconds
Started Mar 12 01:12:39 PM PDT 24
Finished Mar 12 01:12:43 PM PDT 24
Peak memory 216192 kb
Host smart-5ac8d7d7-92d8-46e7-8a0b-d14888ec93de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808102234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3808102234
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1710015135
Short name T642
Test name
Test status
Simulation time 328533402 ps
CPU time 1 seconds
Started Mar 12 01:12:38 PM PDT 24
Finished Mar 12 01:12:39 PM PDT 24
Peak memory 206276 kb
Host smart-83fe4aa3-f0ad-4258-8aa6-6e1bba4db274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710015135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1710015135
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2954128550
Short name T1028
Test name
Test status
Simulation time 60484004 ps
CPU time 1 seconds
Started Mar 12 03:10:13 PM PDT 24
Finished Mar 12 03:10:15 PM PDT 24
Peak memory 205232 kb
Host smart-dac73ec4-2d0c-4997-af6d-35392bb77d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954128550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2954128550
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1807408208
Short name T746
Test name
Test status
Simulation time 1698630143 ps
CPU time 6.33 seconds
Started Mar 12 01:12:48 PM PDT 24
Finished Mar 12 01:12:54 PM PDT 24
Peak memory 228668 kb
Host smart-3e03ad59-a288-4daf-a731-4e5472aa32d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807408208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1807408208
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_upload.2407530989
Short name T1163
Test name
Test status
Simulation time 10626254674 ps
CPU time 7.74 seconds
Started Mar 12 03:10:15 PM PDT 24
Finished Mar 12 03:10:23 PM PDT 24
Peak memory 218300 kb
Host smart-3429cc88-9ab8-46fa-b2df-2292c56c7933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407530989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2407530989
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3309642426
Short name T892
Test name
Test status
Simulation time 14609805 ps
CPU time 0.72 seconds
Started Mar 12 03:10:34 PM PDT 24
Finished Mar 12 03:10:35 PM PDT 24
Peak memory 204812 kb
Host smart-26931a69-d196-40ac-904f-7d7b20f001e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309642426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3309642426
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.4077043360
Short name T397
Test name
Test status
Simulation time 26277845 ps
CPU time 0.67 seconds
Started Mar 12 01:12:52 PM PDT 24
Finished Mar 12 01:12:53 PM PDT 24
Peak memory 205076 kb
Host smart-70c3585d-8b71-4d29-89b6-fe94059f8bc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077043360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
4077043360
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1214838647
Short name T1642
Test name
Test status
Simulation time 238819337 ps
CPU time 4.26 seconds
Started Mar 12 01:12:45 PM PDT 24
Finished Mar 12 01:12:49 PM PDT 24
Peak memory 234376 kb
Host smart-63626638-a588-4172-a54c-f9a0ece3c996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214838647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1214838647
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.697182913
Short name T995
Test name
Test status
Simulation time 54821075 ps
CPU time 2.94 seconds
Started Mar 12 03:10:22 PM PDT 24
Finished Mar 12 03:10:26 PM PDT 24
Peak memory 233396 kb
Host smart-54d84a66-34c2-4377-a78a-d543551c88af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697182913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.697182913
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1120555497
Short name T1897
Test name
Test status
Simulation time 14889177 ps
CPU time 0.72 seconds
Started Mar 12 03:10:22 PM PDT 24
Finished Mar 12 03:10:24 PM PDT 24
Peak memory 204896 kb
Host smart-a3c12083-b2dc-4512-a413-e96abb9b2e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120555497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1120555497
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1898259623
Short name T1776
Test name
Test status
Simulation time 16996945 ps
CPU time 0.77 seconds
Started Mar 12 01:12:48 PM PDT 24
Finished Mar 12 01:12:49 PM PDT 24
Peak memory 205224 kb
Host smart-695a94b3-9aeb-4dc4-86af-76ba10548bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898259623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1898259623
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1214991364
Short name T1746
Test name
Test status
Simulation time 99508864408 ps
CPU time 315.88 seconds
Started Mar 12 01:12:55 PM PDT 24
Finished Mar 12 01:18:11 PM PDT 24
Peak memory 255972 kb
Host smart-d4e3d298-32e0-4714-afe6-e01cf8e3366e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214991364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1214991364
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3405581600
Short name T234
Test name
Test status
Simulation time 13272414085 ps
CPU time 9.38 seconds
Started Mar 12 03:10:22 PM PDT 24
Finished Mar 12 03:10:33 PM PDT 24
Peak memory 218836 kb
Host smart-dc76fb4a-2213-485e-9ac1-5bf0e787ea4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405581600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3405581600
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2410546429
Short name T952
Test name
Test status
Simulation time 32507390711 ps
CPU time 73.25 seconds
Started Mar 12 03:10:23 PM PDT 24
Finished Mar 12 03:11:38 PM PDT 24
Peak memory 252848 kb
Host smart-b71331b0-2419-4eb8-903f-84d298fb0479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410546429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2410546429
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3950392545
Short name T860
Test name
Test status
Simulation time 189431790627 ps
CPU time 211.65 seconds
Started Mar 12 01:12:47 PM PDT 24
Finished Mar 12 01:16:20 PM PDT 24
Peak memory 254536 kb
Host smart-d271c783-f661-4e74-b453-bc33a0f0bd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950392545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3950392545
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2839464393
Short name T587
Test name
Test status
Simulation time 4084696216 ps
CPU time 87.05 seconds
Started Mar 12 03:10:28 PM PDT 24
Finished Mar 12 03:11:55 PM PDT 24
Peak memory 255284 kb
Host smart-68c2b759-6a76-459e-a9d9-1d5f1b2a3f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839464393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2839464393
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.730508604
Short name T897
Test name
Test status
Simulation time 116905066235 ps
CPU time 215.08 seconds
Started Mar 12 01:12:49 PM PDT 24
Finished Mar 12 01:16:25 PM PDT 24
Peak memory 251456 kb
Host smart-d3eda63b-fa18-48e9-a9af-091e47d60302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730508604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle
.730508604
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1318822253
Short name T1415
Test name
Test status
Simulation time 11325056312 ps
CPU time 58.57 seconds
Started Mar 12 01:12:47 PM PDT 24
Finished Mar 12 01:13:46 PM PDT 24
Peak memory 256400 kb
Host smart-32e4fdf5-857e-44ed-95f9-922e53f875d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318822253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1318822253
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.4142705218
Short name T1526
Test name
Test status
Simulation time 5835150632 ps
CPU time 15.31 seconds
Started Mar 12 03:10:24 PM PDT 24
Finished Mar 12 03:10:40 PM PDT 24
Peak memory 240172 kb
Host smart-0f2150e8-e9fd-4b3a-a2fe-e2478d238a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142705218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.4142705218
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2179947921
Short name T1765
Test name
Test status
Simulation time 5453205700 ps
CPU time 17.46 seconds
Started Mar 12 01:12:47 PM PDT 24
Finished Mar 12 01:13:05 PM PDT 24
Peak memory 219656 kb
Host smart-c7334859-7b06-407e-96bc-8d9663e25ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179947921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2179947921
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_intercept.4158538321
Short name T961
Test name
Test status
Simulation time 311058128 ps
CPU time 3.9 seconds
Started Mar 12 03:10:27 PM PDT 24
Finished Mar 12 03:10:31 PM PDT 24
Peak memory 216636 kb
Host smart-c43fb0ab-8e21-4f58-9a4c-bc70b5d042bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158538321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.4158538321
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2687448681
Short name T503
Test name
Test status
Simulation time 66746753972 ps
CPU time 42.99 seconds
Started Mar 12 03:10:22 PM PDT 24
Finished Mar 12 03:11:06 PM PDT 24
Peak memory 236164 kb
Host smart-9d05a72e-1267-43c4-ba06-e2e9eeba3717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687448681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2687448681
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3202560443
Short name T357
Test name
Test status
Simulation time 1603244546 ps
CPU time 12.54 seconds
Started Mar 12 01:12:47 PM PDT 24
Finished Mar 12 01:12:59 PM PDT 24
Peak memory 239412 kb
Host smart-c0787ac2-3cbc-40f5-a169-eb75f79b0731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202560443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3202560443
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2418558447
Short name T865
Test name
Test status
Simulation time 46079616622 ps
CPU time 14.55 seconds
Started Mar 12 01:12:48 PM PDT 24
Finished Mar 12 01:13:04 PM PDT 24
Peak memory 238920 kb
Host smart-bd06b3ba-792f-4f6b-93e1-3144bb52647b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418558447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2418558447
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.4070939011
Short name T1202
Test name
Test status
Simulation time 97510306 ps
CPU time 2.38 seconds
Started Mar 12 03:10:24 PM PDT 24
Finished Mar 12 03:10:27 PM PDT 24
Peak memory 216588 kb
Host smart-693613e8-64ea-4104-aa05-109210d15d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070939011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.4070939011
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1092776162
Short name T1375
Test name
Test status
Simulation time 1978324283 ps
CPU time 6.74 seconds
Started Mar 12 03:10:23 PM PDT 24
Finished Mar 12 03:10:31 PM PDT 24
Peak memory 217316 kb
Host smart-f8f09a97-9c74-41a5-8073-d957dc5029aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092776162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1092776162
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2730326942
Short name T1270
Test name
Test status
Simulation time 60487186 ps
CPU time 2.36 seconds
Started Mar 12 01:12:49 PM PDT 24
Finished Mar 12 01:12:51 PM PDT 24
Peak memory 232628 kb
Host smart-97be3e8e-20bd-45ba-93bc-864cb9a99f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730326942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2730326942
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1906724599
Short name T431
Test name
Test status
Simulation time 771557605 ps
CPU time 4.6 seconds
Started Mar 12 03:10:22 PM PDT 24
Finished Mar 12 03:10:27 PM PDT 24
Peak memory 221788 kb
Host smart-909deb44-034f-4bb0-bb70-3343c7d15ee7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1906724599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1906724599
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3833696883
Short name T506
Test name
Test status
Simulation time 1560757983 ps
CPU time 6.34 seconds
Started Mar 12 01:12:55 PM PDT 24
Finished Mar 12 01:13:02 PM PDT 24
Peak memory 218752 kb
Host smart-ced8fdf0-f6b8-4fcf-9238-52fd30db51b2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3833696883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3833696883
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1954492972
Short name T1514
Test name
Test status
Simulation time 53766651 ps
CPU time 1.03 seconds
Started Mar 12 01:12:49 PM PDT 24
Finished Mar 12 01:12:50 PM PDT 24
Peak memory 206800 kb
Host smart-17eaf402-81ae-447b-83dd-b413d8d2dbfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954492972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1954492972
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.905991545
Short name T272
Test name
Test status
Simulation time 1167794001099 ps
CPU time 506.55 seconds
Started Mar 12 03:10:27 PM PDT 24
Finished Mar 12 03:18:54 PM PDT 24
Peak memory 256768 kb
Host smart-d7801543-77c0-4dc2-9f20-78b65806fa12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905991545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.905991545
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.161707773
Short name T964
Test name
Test status
Simulation time 3107439531 ps
CPU time 11.67 seconds
Started Mar 12 03:10:23 PM PDT 24
Finished Mar 12 03:10:36 PM PDT 24
Peak memory 216072 kb
Host smart-6c89efbf-65ba-49e9-a7ab-44cc0e4190f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161707773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.161707773
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3454262192
Short name T735
Test name
Test status
Simulation time 2363219689 ps
CPU time 11.41 seconds
Started Mar 12 01:12:46 PM PDT 24
Finished Mar 12 01:12:58 PM PDT 24
Peak memory 215860 kb
Host smart-beb60068-cd33-4e29-94a4-30e264ddcd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454262192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3454262192
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1813721320
Short name T1332
Test name
Test status
Simulation time 15295223143 ps
CPU time 7.19 seconds
Started Mar 12 03:10:24 PM PDT 24
Finished Mar 12 03:10:32 PM PDT 24
Peak memory 216156 kb
Host smart-6380a69b-1718-4198-b002-3a0bc66407b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813721320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1813721320
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2714394233
Short name T1203
Test name
Test status
Simulation time 2057784645 ps
CPU time 7.49 seconds
Started Mar 12 01:12:46 PM PDT 24
Finished Mar 12 01:12:54 PM PDT 24
Peak memory 208048 kb
Host smart-4a79c116-2aaa-4038-96b4-e87f594626a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714394233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2714394233
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2303043475
Short name T333
Test name
Test status
Simulation time 429734170 ps
CPU time 1.29 seconds
Started Mar 12 01:12:45 PM PDT 24
Finished Mar 12 01:12:47 PM PDT 24
Peak memory 207928 kb
Host smart-ba96bfa4-c33c-4633-834a-175b247c0e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303043475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2303043475
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2412235493
Short name T425
Test name
Test status
Simulation time 1284851396 ps
CPU time 4.53 seconds
Started Mar 12 03:10:24 PM PDT 24
Finished Mar 12 03:10:29 PM PDT 24
Peak memory 216020 kb
Host smart-5c947cea-8d71-43f9-9414-e8388818b944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412235493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2412235493
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1867825415
Short name T388
Test name
Test status
Simulation time 132759852 ps
CPU time 0.99 seconds
Started Mar 12 01:12:51 PM PDT 24
Finished Mar 12 01:12:52 PM PDT 24
Peak memory 205468 kb
Host smart-ee438af1-23dc-49b3-b6dc-5c1d4a7e8f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867825415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1867825415
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.424670700
Short name T1903
Test name
Test status
Simulation time 51465352 ps
CPU time 0.75 seconds
Started Mar 12 03:10:21 PM PDT 24
Finished Mar 12 03:10:23 PM PDT 24
Peak memory 205256 kb
Host smart-608134cb-b8dd-4e80-b47e-5ed2e5ebcaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424670700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.424670700
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1315278667
Short name T830
Test name
Test status
Simulation time 83887706330 ps
CPU time 58.95 seconds
Started Mar 12 03:10:21 PM PDT 24
Finished Mar 12 03:11:20 PM PDT 24
Peak memory 235128 kb
Host smart-d47f9e16-aacb-45ff-a037-595c23771c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315278667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1315278667
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_upload.1793710718
Short name T1477
Test name
Test status
Simulation time 9871821357 ps
CPU time 29.63 seconds
Started Mar 12 01:12:47 PM PDT 24
Finished Mar 12 01:13:17 PM PDT 24
Peak memory 240612 kb
Host smart-2e057cb1-1412-49cb-94e1-1a8a803da769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793710718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1793710718
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.207683907
Short name T755
Test name
Test status
Simulation time 27691312 ps
CPU time 0.75 seconds
Started Mar 12 03:10:34 PM PDT 24
Finished Mar 12 03:10:35 PM PDT 24
Peak memory 204796 kb
Host smart-f0e29159-f4c2-41fd-b05c-62dce6f6de15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207683907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.207683907
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3613649919
Short name T324
Test name
Test status
Simulation time 23399034 ps
CPU time 0.7 seconds
Started Mar 12 01:12:47 PM PDT 24
Finished Mar 12 01:12:47 PM PDT 24
Peak memory 204204 kb
Host smart-f2f2babe-c9cd-4fc3-a2f6-420b118c3370
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613649919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3613649919
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1772417903
Short name T1869
Test name
Test status
Simulation time 1312837345 ps
CPU time 5.98 seconds
Started Mar 12 03:10:34 PM PDT 24
Finished Mar 12 03:10:40 PM PDT 24
Peak memory 219388 kb
Host smart-a78a7f65-dbd5-4b87-95c7-bd7752e389fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772417903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1772417903
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.967979967
Short name T1750
Test name
Test status
Simulation time 1184165876 ps
CPU time 3.75 seconds
Started Mar 12 01:12:47 PM PDT 24
Finished Mar 12 01:12:50 PM PDT 24
Peak memory 233948 kb
Host smart-e67d8f7a-4aec-45bb-8944-9c1da1ec9937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967979967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.967979967
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1470333256
Short name T1504
Test name
Test status
Simulation time 41795773 ps
CPU time 0.8 seconds
Started Mar 12 01:12:51 PM PDT 24
Finished Mar 12 01:12:52 PM PDT 24
Peak memory 204904 kb
Host smart-06767914-0c77-490b-a194-e8953ad0e33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470333256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1470333256
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3423157804
Short name T551
Test name
Test status
Simulation time 32384212 ps
CPU time 0.78 seconds
Started Mar 12 03:10:34 PM PDT 24
Finished Mar 12 03:10:34 PM PDT 24
Peak memory 205244 kb
Host smart-e6ca2e28-0bdc-46e9-aba6-7f94388ef470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423157804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3423157804
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1654678129
Short name T1444
Test name
Test status
Simulation time 6067903004 ps
CPU time 79.13 seconds
Started Mar 12 01:12:48 PM PDT 24
Finished Mar 12 01:14:08 PM PDT 24
Peak memory 265228 kb
Host smart-96f4751a-6694-4d72-acf7-699eb991fb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654678129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1654678129
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2549695943
Short name T1458
Test name
Test status
Simulation time 1810369971 ps
CPU time 8.6 seconds
Started Mar 12 03:10:33 PM PDT 24
Finished Mar 12 03:10:42 PM PDT 24
Peak memory 237680 kb
Host smart-ce8ee040-0c7f-486e-9783-99c39aa94e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549695943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2549695943
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.21740909
Short name T471
Test name
Test status
Simulation time 63983298354 ps
CPU time 198.9 seconds
Started Mar 12 03:10:33 PM PDT 24
Finished Mar 12 03:13:53 PM PDT 24
Peak memory 256108 kb
Host smart-3e934335-52b2-49d4-a2bc-6ae3a0273ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21740909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.21740909
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2550365010
Short name T50
Test name
Test status
Simulation time 36907089919 ps
CPU time 319.15 seconds
Started Mar 12 01:12:44 PM PDT 24
Finished Mar 12 01:18:04 PM PDT 24
Peak memory 254576 kb
Host smart-f7d84f08-d51a-46fb-a5f6-57143db8bf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550365010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2550365010
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1068513798
Short name T1297
Test name
Test status
Simulation time 11569603106 ps
CPU time 107.68 seconds
Started Mar 12 01:12:49 PM PDT 24
Finished Mar 12 01:14:37 PM PDT 24
Peak memory 252332 kb
Host smart-d7b6be8c-53e5-4820-9ea6-aefdd7e3fbde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068513798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1068513798
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3651144733
Short name T18
Test name
Test status
Simulation time 65045721360 ps
CPU time 140.77 seconds
Started Mar 12 03:10:35 PM PDT 24
Finished Mar 12 03:12:57 PM PDT 24
Peak memory 252728 kb
Host smart-d1bd7a49-6518-49bb-91f1-adb9d46fda7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651144733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3651144733
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2894719983
Short name T1275
Test name
Test status
Simulation time 7109313702 ps
CPU time 15.76 seconds
Started Mar 12 03:10:35 PM PDT 24
Finished Mar 12 03:10:51 PM PDT 24
Peak memory 233036 kb
Host smart-2685f1b8-3980-441c-86b7-977013afcbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894719983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2894719983
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.570680469
Short name T1101
Test name
Test status
Simulation time 3028435333 ps
CPU time 17.25 seconds
Started Mar 12 01:12:47 PM PDT 24
Finished Mar 12 01:13:05 PM PDT 24
Peak memory 232444 kb
Host smart-6e3a6376-f242-48e8-bccb-2c7d122c54d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570680469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.570680469
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.1130622505
Short name T802
Test name
Test status
Simulation time 364787914 ps
CPU time 4.42 seconds
Started Mar 12 03:10:33 PM PDT 24
Finished Mar 12 03:10:37 PM PDT 24
Peak memory 233292 kb
Host smart-ab60145a-ba2c-4b59-ad7b-84ce64562afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130622505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1130622505
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_intercept.610520317
Short name T193
Test name
Test status
Simulation time 16699348552 ps
CPU time 14.57 seconds
Started Mar 12 01:12:48 PM PDT 24
Finished Mar 12 01:13:03 PM PDT 24
Peak memory 220292 kb
Host smart-f52f89ad-d5a3-4123-befb-b566ad2dbbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610520317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.610520317
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3194098169
Short name T670
Test name
Test status
Simulation time 36101832350 ps
CPU time 19.88 seconds
Started Mar 12 01:12:47 PM PDT 24
Finished Mar 12 01:13:07 PM PDT 24
Peak memory 237540 kb
Host smart-cd3837d4-da2a-49d1-a824-7c2a36cb0b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194098169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3194098169
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.4178196075
Short name T1334
Test name
Test status
Simulation time 169700050 ps
CPU time 4.53 seconds
Started Mar 12 03:10:35 PM PDT 24
Finished Mar 12 03:10:39 PM PDT 24
Peak memory 232376 kb
Host smart-65bb8c20-4dc4-4222-b49e-f30630e33002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178196075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.4178196075
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.145946326
Short name T1635
Test name
Test status
Simulation time 2933998110 ps
CPU time 12.58 seconds
Started Mar 12 01:12:48 PM PDT 24
Finished Mar 12 01:13:01 PM PDT 24
Peak memory 240424 kb
Host smart-4dbcda1c-fa74-488d-9744-b8ae02e7f71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145946326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap
.145946326
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.48215958
Short name T990
Test name
Test status
Simulation time 28577911196 ps
CPU time 30.44 seconds
Started Mar 12 03:10:33 PM PDT 24
Finished Mar 12 03:11:04 PM PDT 24
Peak memory 224228 kb
Host smart-fe8f3d49-a429-420f-97f8-992e58181be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48215958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap.48215958
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2054980370
Short name T1751
Test name
Test status
Simulation time 687259147 ps
CPU time 5.49 seconds
Started Mar 12 01:12:49 PM PDT 24
Finished Mar 12 01:12:55 PM PDT 24
Peak memory 236340 kb
Host smart-7e406ebd-c4a9-4409-965d-0ff646544043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054980370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2054980370
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.4261697545
Short name T1700
Test name
Test status
Simulation time 1033480277 ps
CPU time 4.57 seconds
Started Mar 12 03:10:35 PM PDT 24
Finished Mar 12 03:10:39 PM PDT 24
Peak memory 216640 kb
Host smart-4d32ad2e-0f6e-4bff-acae-9252c594e4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261697545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.4261697545
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.643958137
Short name T1117
Test name
Test status
Simulation time 517078302 ps
CPU time 4.17 seconds
Started Mar 12 03:10:34 PM PDT 24
Finished Mar 12 03:10:38 PM PDT 24
Peak memory 222224 kb
Host smart-c213bb49-64da-4d16-a2e1-eac7ef46a350
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=643958137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.643958137
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.671506525
Short name T1835
Test name
Test status
Simulation time 4398048320 ps
CPU time 6.14 seconds
Started Mar 12 01:12:47 PM PDT 24
Finished Mar 12 01:12:54 PM PDT 24
Peak memory 222336 kb
Host smart-14d9973e-c836-4023-a49d-1ae3a474acd9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=671506525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.671506525
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.3639531554
Short name T161
Test name
Test status
Simulation time 785147091 ps
CPU time 1.01 seconds
Started Mar 12 03:10:38 PM PDT 24
Finished Mar 12 03:10:40 PM PDT 24
Peak memory 206364 kb
Host smart-e4997f90-55b7-483a-9f9c-60205fb878f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639531554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3639531554
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1449924058
Short name T739
Test name
Test status
Simulation time 1549646934 ps
CPU time 8.91 seconds
Started Mar 12 03:10:35 PM PDT 24
Finished Mar 12 03:10:44 PM PDT 24
Peak memory 216072 kb
Host smart-b62a84ac-761c-4cd2-9f42-f8525acdf07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449924058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1449924058
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2752401686
Short name T1744
Test name
Test status
Simulation time 5222331370 ps
CPU time 21.75 seconds
Started Mar 12 01:12:44 PM PDT 24
Finished Mar 12 01:13:06 PM PDT 24
Peak memory 216132 kb
Host smart-c0e132bb-01ce-4039-96d7-9efecaaff2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752401686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2752401686
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2315778646
Short name T1492
Test name
Test status
Simulation time 2471609936 ps
CPU time 6.49 seconds
Started Mar 12 03:10:35 PM PDT 24
Finished Mar 12 03:10:42 PM PDT 24
Peak memory 216156 kb
Host smart-3528e784-6e7a-4efc-b3a5-65dfac604506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315778646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2315778646
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2472099773
Short name T808
Test name
Test status
Simulation time 7542435134 ps
CPU time 11.1 seconds
Started Mar 12 01:12:47 PM PDT 24
Finished Mar 12 01:12:59 PM PDT 24
Peak memory 216100 kb
Host smart-164e3cbe-8d4c-4242-818c-5a90f9f6054a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472099773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2472099773
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1960509075
Short name T524
Test name
Test status
Simulation time 463600451 ps
CPU time 8.39 seconds
Started Mar 12 01:12:47 PM PDT 24
Finished Mar 12 01:12:55 PM PDT 24
Peak memory 216092 kb
Host smart-2649e068-9168-4fc7-834e-e1ca84e811a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960509075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1960509075
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3389764415
Short name T1148
Test name
Test status
Simulation time 242522127 ps
CPU time 2.99 seconds
Started Mar 12 03:10:33 PM PDT 24
Finished Mar 12 03:10:36 PM PDT 24
Peak memory 216160 kb
Host smart-18f9bfda-0d27-416d-a8a1-862b80e24fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389764415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3389764415
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.4204943343
Short name T1036
Test name
Test status
Simulation time 149278106 ps
CPU time 0.86 seconds
Started Mar 12 03:10:36 PM PDT 24
Finished Mar 12 03:10:37 PM PDT 24
Peak memory 206280 kb
Host smart-8d33b428-5099-4b74-98eb-0393962338b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204943343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.4204943343
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.652206425
Short name T898
Test name
Test status
Simulation time 331018588 ps
CPU time 0.92 seconds
Started Mar 12 01:12:48 PM PDT 24
Finished Mar 12 01:12:50 PM PDT 24
Peak memory 205252 kb
Host smart-24ffeca8-6e68-4ecf-a317-85fc47e67096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652206425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.652206425
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.1384073057
Short name T1756
Test name
Test status
Simulation time 552413250 ps
CPU time 6.14 seconds
Started Mar 12 03:10:33 PM PDT 24
Finished Mar 12 03:10:40 PM PDT 24
Peak memory 228680 kb
Host smart-6e4f23df-be7e-42f2-8b03-c328d4b97f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384073057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1384073057
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_upload.1525385015
Short name T1662
Test name
Test status
Simulation time 621931039 ps
CPU time 8.19 seconds
Started Mar 12 01:12:48 PM PDT 24
Finished Mar 12 01:12:57 PM PDT 24
Peak memory 218360 kb
Host smart-794af7e1-85c9-47b9-9cd3-708fcec3ba30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525385015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1525385015
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2077426625
Short name T507
Test name
Test status
Simulation time 11623943 ps
CPU time 0.69 seconds
Started Mar 12 01:13:05 PM PDT 24
Finished Mar 12 01:13:06 PM PDT 24
Peak memory 204984 kb
Host smart-77b5eb34-0ffe-436b-9e92-49888b87adfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077426625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2077426625
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.634241513
Short name T1395
Test name
Test status
Simulation time 36686324 ps
CPU time 0.77 seconds
Started Mar 12 03:10:48 PM PDT 24
Finished Mar 12 03:10:49 PM PDT 24
Peak memory 204112 kb
Host smart-39955766-d465-4495-bbac-267e62884540
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634241513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.634241513
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2350119443
Short name T843
Test name
Test status
Simulation time 992355694 ps
CPU time 3.98 seconds
Started Mar 12 01:13:01 PM PDT 24
Finished Mar 12 01:13:06 PM PDT 24
Peak memory 224132 kb
Host smart-0a55b54e-e63a-474f-af06-f761264f7e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350119443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2350119443
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3967686240
Short name T1696
Test name
Test status
Simulation time 4694853586 ps
CPU time 4.96 seconds
Started Mar 12 03:10:36 PM PDT 24
Finished Mar 12 03:10:41 PM PDT 24
Peak memory 219252 kb
Host smart-bb6b5d40-7167-49bd-8d07-a76a344db35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967686240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3967686240
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3508115517
Short name T1576
Test name
Test status
Simulation time 35867456 ps
CPU time 0.79 seconds
Started Mar 12 03:10:33 PM PDT 24
Finished Mar 12 03:10:34 PM PDT 24
Peak memory 205960 kb
Host smart-ebf27a11-d223-4dda-8e4f-d102c1073967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508115517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3508115517
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3817181133
Short name T420
Test name
Test status
Simulation time 27493280 ps
CPU time 0.75 seconds
Started Mar 12 01:12:47 PM PDT 24
Finished Mar 12 01:12:48 PM PDT 24
Peak memory 206184 kb
Host smart-2454cc47-bfe7-40be-859f-f5a005829dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817181133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3817181133
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2320890778
Short name T257
Test name
Test status
Simulation time 3236712760 ps
CPU time 54 seconds
Started Mar 12 01:13:02 PM PDT 24
Finished Mar 12 01:13:56 PM PDT 24
Peak memory 257016 kb
Host smart-0a211e2c-5016-41ec-bf78-17c95c61d49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320890778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2320890778
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.3127103878
Short name T859
Test name
Test status
Simulation time 3504594418 ps
CPU time 55.24 seconds
Started Mar 12 03:10:48 PM PDT 24
Finished Mar 12 03:11:44 PM PDT 24
Peak memory 257020 kb
Host smart-21712dd2-69f2-4c4b-978d-eb1b005e58b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127103878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3127103878
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.2294646880
Short name T667
Test name
Test status
Simulation time 14445807408 ps
CPU time 61.06 seconds
Started Mar 12 03:10:48 PM PDT 24
Finished Mar 12 03:11:50 PM PDT 24
Peak memory 250908 kb
Host smart-42f1caab-8a73-4060-a52e-8605cc20ae52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294646880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2294646880
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3292791139
Short name T1499
Test name
Test status
Simulation time 12134410137 ps
CPU time 144.53 seconds
Started Mar 12 01:13:03 PM PDT 24
Finished Mar 12 01:15:28 PM PDT 24
Peak memory 256156 kb
Host smart-c3de9898-eae2-4df6-a77b-3fdd23d4ab35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292791139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3292791139
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.4020156450
Short name T188
Test name
Test status
Simulation time 17699299012 ps
CPU time 96.11 seconds
Started Mar 12 01:13:04 PM PDT 24
Finished Mar 12 01:14:40 PM PDT 24
Peak memory 254700 kb
Host smart-899a792e-34c9-4724-8206-1d375e600ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020156450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.4020156450
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.4021811581
Short name T517
Test name
Test status
Simulation time 13691485194 ps
CPU time 80.96 seconds
Started Mar 12 03:10:48 PM PDT 24
Finished Mar 12 03:12:10 PM PDT 24
Peak memory 249968 kb
Host smart-c31e7b0a-6cc5-4ee5-99bb-6aadb8d0c934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021811581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.4021811581
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1109778250
Short name T434
Test name
Test status
Simulation time 20229572651 ps
CPU time 32.6 seconds
Started Mar 12 03:10:42 PM PDT 24
Finished Mar 12 03:11:15 PM PDT 24
Peak memory 237896 kb
Host smart-ceb07633-d889-44f8-b4b4-1e1827ad7da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109778250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1109778250
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3348620763
Short name T936
Test name
Test status
Simulation time 9303553167 ps
CPU time 17.4 seconds
Started Mar 12 01:13:03 PM PDT 24
Finished Mar 12 01:13:21 PM PDT 24
Peak memory 240652 kb
Host smart-d7690a86-b9f4-4fcf-8288-39b2efee4b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348620763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3348620763
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.2389683381
Short name T984
Test name
Test status
Simulation time 2448170091 ps
CPU time 10.44 seconds
Started Mar 12 03:10:38 PM PDT 24
Finished Mar 12 03:10:48 PM PDT 24
Peak memory 218764 kb
Host smart-024ab6c8-108d-43ff-a806-954d48b72b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389683381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2389683381
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3392733917
Short name T1779
Test name
Test status
Simulation time 8860614299 ps
CPU time 12.98 seconds
Started Mar 12 01:13:03 PM PDT 24
Finished Mar 12 01:13:16 PM PDT 24
Peak memory 239364 kb
Host smart-6ac0e692-eb29-4be8-943c-7979473b7dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392733917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3392733917
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3726846030
Short name T768
Test name
Test status
Simulation time 4090864221 ps
CPU time 8.99 seconds
Started Mar 12 01:13:04 PM PDT 24
Finished Mar 12 01:13:13 PM PDT 24
Peak memory 232440 kb
Host smart-cfbcb7da-2612-49e8-b023-392f6558723d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726846030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3726846030
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.890588730
Short name T1158
Test name
Test status
Simulation time 6971566338 ps
CPU time 22.33 seconds
Started Mar 12 03:10:40 PM PDT 24
Finished Mar 12 03:11:03 PM PDT 24
Peak memory 231836 kb
Host smart-cdbfbe03-da33-4dbd-9b27-010af530fbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890588730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.890588730
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2849988050
Short name T1682
Test name
Test status
Simulation time 32021406071 ps
CPU time 20.32 seconds
Started Mar 12 03:10:40 PM PDT 24
Finished Mar 12 03:11:00 PM PDT 24
Peak memory 233504 kb
Host smart-4dff932f-3f08-4924-a2e0-b3ed3ad858a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849988050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2849988050
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.64251780
Short name T29
Test name
Test status
Simulation time 16029568452 ps
CPU time 17.07 seconds
Started Mar 12 01:12:48 PM PDT 24
Finished Mar 12 01:13:05 PM PDT 24
Peak memory 232452 kb
Host smart-f29bf909-0d8c-46ab-bd55-6cf54c8ba19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64251780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap.64251780
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1471289798
Short name T684
Test name
Test status
Simulation time 1311279310 ps
CPU time 6.07 seconds
Started Mar 12 01:12:49 PM PDT 24
Finished Mar 12 01:12:55 PM PDT 24
Peak memory 233132 kb
Host smart-5904e8bc-7663-434f-becd-aa3ca7f55a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471289798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1471289798
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1940014903
Short name T1814
Test name
Test status
Simulation time 9498063568 ps
CPU time 8.47 seconds
Started Mar 12 03:10:37 PM PDT 24
Finished Mar 12 03:10:46 PM PDT 24
Peak memory 230444 kb
Host smart-873cd74e-dbe6-4a5f-8742-101e1dde5f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940014903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1940014903
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1873370143
Short name T1299
Test name
Test status
Simulation time 4209067857 ps
CPU time 5.39 seconds
Started Mar 12 03:10:43 PM PDT 24
Finished Mar 12 03:10:49 PM PDT 24
Peak memory 219884 kb
Host smart-cf675af1-a0b5-4af6-9f9e-7e68269558b3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1873370143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1873370143
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.645495882
Short name T951
Test name
Test status
Simulation time 2492989678 ps
CPU time 5.75 seconds
Started Mar 12 01:13:03 PM PDT 24
Finished Mar 12 01:13:09 PM PDT 24
Peak memory 218608 kb
Host smart-d26cc376-cf98-4d0d-9080-8b1b7599a0f4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=645495882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.645495882
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1318593940
Short name T168
Test name
Test status
Simulation time 174532042 ps
CPU time 1.26 seconds
Started Mar 12 01:13:01 PM PDT 24
Finished Mar 12 01:13:03 PM PDT 24
Peak memory 206632 kb
Host smart-0e6f5967-804f-4915-91be-5500fd57e88a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318593940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1318593940
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.44401271
Short name T1911
Test name
Test status
Simulation time 31473092 ps
CPU time 0.9 seconds
Started Mar 12 03:10:47 PM PDT 24
Finished Mar 12 03:10:48 PM PDT 24
Peak memory 205916 kb
Host smart-30cd9d47-7e0f-44c6-ab69-5e75c814f979
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44401271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stress
_all.44401271
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1567733780
Short name T1857
Test name
Test status
Simulation time 2329827997 ps
CPU time 14.22 seconds
Started Mar 12 01:12:48 PM PDT 24
Finished Mar 12 01:13:02 PM PDT 24
Peak memory 216120 kb
Host smart-d602e751-77f1-4546-9d10-4f2f8ab7408a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567733780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1567733780
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.657478681
Short name T1466
Test name
Test status
Simulation time 25800393370 ps
CPU time 40.58 seconds
Started Mar 12 03:10:40 PM PDT 24
Finished Mar 12 03:11:21 PM PDT 24
Peak memory 216156 kb
Host smart-af7cd532-1b28-4eb6-b5c7-3ad60fce9cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657478681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.657478681
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1730480587
Short name T1754
Test name
Test status
Simulation time 893508973 ps
CPU time 2.11 seconds
Started Mar 12 01:12:47 PM PDT 24
Finished Mar 12 01:12:50 PM PDT 24
Peak memory 207660 kb
Host smart-52b60968-1552-494d-8b98-beaa5eb34112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730480587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1730480587
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.275704569
Short name T1914
Test name
Test status
Simulation time 128162233 ps
CPU time 1.79 seconds
Started Mar 12 03:10:41 PM PDT 24
Finished Mar 12 03:10:43 PM PDT 24
Peak memory 206620 kb
Host smart-e64a4ab1-9906-4b32-b250-7db46acf8470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275704569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.275704569
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3772360532
Short name T1113
Test name
Test status
Simulation time 45966887 ps
CPU time 1.65 seconds
Started Mar 12 01:12:51 PM PDT 24
Finished Mar 12 01:12:53 PM PDT 24
Peak memory 207580 kb
Host smart-25175d37-2e44-436d-b82c-9d5474564752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772360532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3772360532
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3802176200
Short name T1602
Test name
Test status
Simulation time 982521801 ps
CPU time 3.29 seconds
Started Mar 12 03:10:43 PM PDT 24
Finished Mar 12 03:10:47 PM PDT 24
Peak memory 216040 kb
Host smart-2e6dc4af-1c37-4994-b30f-3aa7d33ed3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802176200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3802176200
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1058560391
Short name T1292
Test name
Test status
Simulation time 1106590701 ps
CPU time 1.17 seconds
Started Mar 12 03:10:34 PM PDT 24
Finished Mar 12 03:10:36 PM PDT 24
Peak memory 206248 kb
Host smart-758abfe7-633f-44e8-9015-302c55f7c996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058560391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1058560391
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.859356639
Short name T540
Test name
Test status
Simulation time 172843518 ps
CPU time 0.73 seconds
Started Mar 12 01:12:47 PM PDT 24
Finished Mar 12 01:12:47 PM PDT 24
Peak memory 205284 kb
Host smart-6a5c94c4-d1f8-4fbf-9005-a19bb8e27960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859356639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.859356639
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2942957762
Short name T519
Test name
Test status
Simulation time 2667895838 ps
CPU time 12.26 seconds
Started Mar 12 01:12:59 PM PDT 24
Finished Mar 12 01:13:11 PM PDT 24
Peak memory 234024 kb
Host smart-ec7c6714-fd76-4557-81ee-fa43306e6718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942957762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2942957762
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_upload.40345142
Short name T573
Test name
Test status
Simulation time 2698853077 ps
CPU time 11.29 seconds
Started Mar 12 03:10:34 PM PDT 24
Finished Mar 12 03:10:46 PM PDT 24
Peak memory 216620 kb
Host smart-7571ca46-3f5c-4a81-a072-43644a47afe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40345142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.40345142
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1831542958
Short name T57
Test name
Test status
Simulation time 11553632 ps
CPU time 0.69 seconds
Started Mar 12 03:10:48 PM PDT 24
Finished Mar 12 03:10:49 PM PDT 24
Peak memory 204800 kb
Host smart-15dad367-27bf-45dd-b45f-d023ca877e36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831542958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1831542958
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.676774034
Short name T839
Test name
Test status
Simulation time 25483829 ps
CPU time 0.75 seconds
Started Mar 12 01:13:02 PM PDT 24
Finished Mar 12 01:13:03 PM PDT 24
Peak memory 204204 kb
Host smart-2c64f7d8-6bc3-4625-8a56-6b23febc7af8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676774034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.676774034
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1127776819
Short name T499
Test name
Test status
Simulation time 42414975 ps
CPU time 2.62 seconds
Started Mar 12 01:13:03 PM PDT 24
Finished Mar 12 01:13:06 PM PDT 24
Peak memory 233232 kb
Host smart-44024b5f-6d4a-436c-a6e5-d1c094a2579c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127776819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1127776819
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3749211882
Short name T1408
Test name
Test status
Simulation time 548441257 ps
CPU time 3.16 seconds
Started Mar 12 03:10:48 PM PDT 24
Finished Mar 12 03:10:51 PM PDT 24
Peak memory 224212 kb
Host smart-f21be2f7-ae02-43d8-a2b6-6baee18c72ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749211882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3749211882
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1489164595
Short name T1027
Test name
Test status
Simulation time 22459555 ps
CPU time 0.74 seconds
Started Mar 12 01:13:03 PM PDT 24
Finished Mar 12 01:13:04 PM PDT 24
Peak memory 205232 kb
Host smart-de5d6f70-0337-4908-b60e-6e2ab4728763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489164595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1489164595
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3793280582
Short name T344
Test name
Test status
Simulation time 19426732 ps
CPU time 0.81 seconds
Started Mar 12 03:10:49 PM PDT 24
Finished Mar 12 03:10:50 PM PDT 24
Peak memory 205940 kb
Host smart-00333657-ae03-477e-9690-1b1e1c3ee49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793280582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3793280582
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2026655125
Short name T545
Test name
Test status
Simulation time 4158402645 ps
CPU time 31.33 seconds
Started Mar 12 01:13:00 PM PDT 24
Finished Mar 12 01:13:31 PM PDT 24
Peak memory 240664 kb
Host smart-4152ad49-5980-45fe-b6cf-a366542850a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026655125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2026655125
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3516321844
Short name T1448
Test name
Test status
Simulation time 98247407066 ps
CPU time 156.41 seconds
Started Mar 12 03:10:48 PM PDT 24
Finished Mar 12 03:13:25 PM PDT 24
Peak memory 252108 kb
Host smart-2f043739-8b1d-4194-a553-da29b08046ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516321844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3516321844
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3341764904
Short name T1486
Test name
Test status
Simulation time 2447960784 ps
CPU time 32.08 seconds
Started Mar 12 01:13:02 PM PDT 24
Finished Mar 12 01:13:35 PM PDT 24
Peak memory 237208 kb
Host smart-715a3b66-a68f-48ce-a34a-01d9f11eebd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341764904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3341764904
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.420938410
Short name T1459
Test name
Test status
Simulation time 26584236178 ps
CPU time 168.48 seconds
Started Mar 12 03:10:51 PM PDT 24
Finished Mar 12 03:13:40 PM PDT 24
Peak memory 251704 kb
Host smart-fe5068e1-0ba2-4e8d-87c1-d74fb15924e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420938410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.420938410
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.302926261
Short name T1065
Test name
Test status
Simulation time 6444369605 ps
CPU time 60.57 seconds
Started Mar 12 01:13:04 PM PDT 24
Finished Mar 12 01:14:05 PM PDT 24
Peak memory 250568 kb
Host smart-e7c00088-d06f-4d12-b78e-b5a56371d0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302926261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.302926261
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.3479710673
Short name T202
Test name
Test status
Simulation time 4632066290 ps
CPU time 62.28 seconds
Started Mar 12 03:10:48 PM PDT 24
Finished Mar 12 03:11:51 PM PDT 24
Peak memory 250232 kb
Host smart-08080c8b-eb7b-4963-a974-83ecb84aa7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479710673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.3479710673
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1756953988
Short name T1210
Test name
Test status
Simulation time 7536011753 ps
CPU time 34.69 seconds
Started Mar 12 01:13:04 PM PDT 24
Finished Mar 12 01:13:39 PM PDT 24
Peak memory 239660 kb
Host smart-cadd1396-04cc-4c2d-870a-b3b6b55d1f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756953988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1756953988
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1402086158
Short name T1885
Test name
Test status
Simulation time 37452755 ps
CPU time 2.4 seconds
Started Mar 12 01:13:06 PM PDT 24
Finished Mar 12 01:13:08 PM PDT 24
Peak memory 224188 kb
Host smart-80615057-a421-4721-b92c-0ae22bb7504f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402086158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1402086158
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3626511636
Short name T1749
Test name
Test status
Simulation time 1207188882 ps
CPU time 5.49 seconds
Started Mar 12 03:10:47 PM PDT 24
Finished Mar 12 03:10:53 PM PDT 24
Peak memory 233376 kb
Host smart-76d8a28a-c489-460c-ae04-2b7b207c551e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626511636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3626511636
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1171494833
Short name T840
Test name
Test status
Simulation time 2222880204 ps
CPU time 14.13 seconds
Started Mar 12 03:10:46 PM PDT 24
Finished Mar 12 03:11:01 PM PDT 24
Peak memory 256948 kb
Host smart-5ac62694-c8f0-466f-916c-a548be600104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171494833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1171494833
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3268357318
Short name T663
Test name
Test status
Simulation time 8061940404 ps
CPU time 24.95 seconds
Started Mar 12 01:13:03 PM PDT 24
Finished Mar 12 01:13:28 PM PDT 24
Peak memory 231104 kb
Host smart-e790b9d5-7623-447d-ad46-70745d93c2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268357318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3268357318
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2464520237
Short name T1456
Test name
Test status
Simulation time 7881188801 ps
CPU time 7.47 seconds
Started Mar 12 03:10:48 PM PDT 24
Finished Mar 12 03:10:56 PM PDT 24
Peak memory 233064 kb
Host smart-94913fdd-007f-4c94-ac51-a248aac96209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464520237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2464520237
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3684491335
Short name T118
Test name
Test status
Simulation time 2112617308 ps
CPU time 7.52 seconds
Started Mar 12 01:13:01 PM PDT 24
Finished Mar 12 01:13:08 PM PDT 24
Peak memory 232744 kb
Host smart-ac3109e9-e2cd-40c7-8425-184e4b51f55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684491335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3684491335
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2622735712
Short name T1282
Test name
Test status
Simulation time 4799528377 ps
CPU time 16.51 seconds
Started Mar 12 03:10:47 PM PDT 24
Finished Mar 12 03:11:04 PM PDT 24
Peak memory 224284 kb
Host smart-d1bb2d0a-e280-47fc-966e-2bc29e189d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622735712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2622735712
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.397014843
Short name T473
Test name
Test status
Simulation time 5431855265 ps
CPU time 18.44 seconds
Started Mar 12 01:13:03 PM PDT 24
Finished Mar 12 01:13:22 PM PDT 24
Peak memory 232824 kb
Host smart-3a2f201e-bf1b-4987-8297-063855ec6afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397014843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.397014843
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1329064095
Short name T1507
Test name
Test status
Simulation time 917988655 ps
CPU time 4.24 seconds
Started Mar 12 01:13:03 PM PDT 24
Finished Mar 12 01:13:07 PM PDT 24
Peak memory 222160 kb
Host smart-8d7edee7-1575-497f-bb17-d7aace3ef26a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1329064095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1329064095
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1467452150
Short name T6
Test name
Test status
Simulation time 2964172419 ps
CPU time 4.7 seconds
Started Mar 12 03:10:50 PM PDT 24
Finished Mar 12 03:10:55 PM PDT 24
Peak memory 216224 kb
Host smart-5429ca3d-031a-4db3-b482-e8833f8ef965
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1467452150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1467452150
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.106785660
Short name T1225
Test name
Test status
Simulation time 48627558739 ps
CPU time 173.64 seconds
Started Mar 12 03:10:47 PM PDT 24
Finished Mar 12 03:13:42 PM PDT 24
Peak memory 251440 kb
Host smart-ee1cec12-f3f1-43e0-8ea3-d9afc19cf910
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106785660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.106785660
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.2746567309
Short name T1455
Test name
Test status
Simulation time 119934664274 ps
CPU time 376.94 seconds
Started Mar 12 01:13:02 PM PDT 24
Finished Mar 12 01:19:19 PM PDT 24
Peak memory 257148 kb
Host smart-c6835da4-ad18-4bbc-a099-4c788cf59a98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746567309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2746567309
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1398896520
Short name T1638
Test name
Test status
Simulation time 7514691205 ps
CPU time 17.3 seconds
Started Mar 12 03:10:47 PM PDT 24
Finished Mar 12 03:11:05 PM PDT 24
Peak memory 215900 kb
Host smart-e61caf7b-2b47-49ba-b62a-e453fb7d761c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398896520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1398896520
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.4269273051
Short name T1737
Test name
Test status
Simulation time 4246217727 ps
CPU time 29.1 seconds
Started Mar 12 01:12:59 PM PDT 24
Finished Mar 12 01:13:29 PM PDT 24
Peak memory 216168 kb
Host smart-d596025d-d356-4475-8fe8-a23db928e388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269273051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.4269273051
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2409339820
Short name T539
Test name
Test status
Simulation time 12638548476 ps
CPU time 32.51 seconds
Started Mar 12 03:10:49 PM PDT 24
Finished Mar 12 03:11:22 PM PDT 24
Peak memory 216060 kb
Host smart-34adbfe5-5b60-4be9-80d8-894f65312e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409339820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2409339820
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3599761300
Short name T674
Test name
Test status
Simulation time 996358022 ps
CPU time 3.52 seconds
Started Mar 12 01:13:02 PM PDT 24
Finished Mar 12 01:13:06 PM PDT 24
Peak memory 207908 kb
Host smart-9eaaa044-1e65-4805-9a68-c7b025ebc33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599761300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3599761300
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.211110418
Short name T597
Test name
Test status
Simulation time 603402285 ps
CPU time 3.81 seconds
Started Mar 12 01:13:02 PM PDT 24
Finished Mar 12 01:13:06 PM PDT 24
Peak memory 217760 kb
Host smart-284ba122-db93-41f5-956b-9b02c62333ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211110418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.211110418
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2120080314
Short name T1374
Test name
Test status
Simulation time 59697930 ps
CPU time 1.49 seconds
Started Mar 12 03:10:46 PM PDT 24
Finished Mar 12 03:10:48 PM PDT 24
Peak memory 216032 kb
Host smart-c1f9ae5e-bfa2-4ba0-9590-fe1c11c00b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120080314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2120080314
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2151067081
Short name T621
Test name
Test status
Simulation time 194304766 ps
CPU time 0.88 seconds
Started Mar 12 03:10:44 PM PDT 24
Finished Mar 12 03:10:46 PM PDT 24
Peak memory 205220 kb
Host smart-ab70e4aa-4c64-451e-81a0-4e8612b6aa61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151067081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2151067081
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3373739908
Short name T1414
Test name
Test status
Simulation time 122921119 ps
CPU time 1.2 seconds
Started Mar 12 01:13:05 PM PDT 24
Finished Mar 12 01:13:06 PM PDT 24
Peak memory 206300 kb
Host smart-9f570b4c-9921-4974-bae5-89be9956e101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373739908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3373739908
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1025874486
Short name T888
Test name
Test status
Simulation time 14020147808 ps
CPU time 26.75 seconds
Started Mar 12 01:13:05 PM PDT 24
Finished Mar 12 01:13:32 PM PDT 24
Peak memory 229696 kb
Host smart-a2c80ab5-38d6-40d1-a451-f96fe6cf62c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025874486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1025874486
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_upload.3686739560
Short name T489
Test name
Test status
Simulation time 207667898 ps
CPU time 2.77 seconds
Started Mar 12 03:10:47 PM PDT 24
Finished Mar 12 03:10:50 PM PDT 24
Peak memory 217052 kb
Host smart-deaadec1-f458-4ceb-9203-b7edcb03e323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686739560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3686739560
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.135434217
Short name T1257
Test name
Test status
Simulation time 13740082 ps
CPU time 0.75 seconds
Started Mar 12 01:13:05 PM PDT 24
Finished Mar 12 01:13:06 PM PDT 24
Peak memory 204800 kb
Host smart-89ab15bf-5454-4c80-8010-b5c4be9df0de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135434217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.135434217
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2953646297
Short name T351
Test name
Test status
Simulation time 10979267 ps
CPU time 0.79 seconds
Started Mar 12 03:10:49 PM PDT 24
Finished Mar 12 03:10:50 PM PDT 24
Peak memory 204764 kb
Host smart-ac8351f7-4eab-4221-8c9d-da7997913991
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953646297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2953646297
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1998802556
Short name T867
Test name
Test status
Simulation time 361262859 ps
CPU time 4.84 seconds
Started Mar 12 03:10:48 PM PDT 24
Finished Mar 12 03:10:53 PM PDT 24
Peak memory 233340 kb
Host smart-8a5002ca-3040-41fa-8ca4-dc5c61760440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998802556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1998802556
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2247074202
Short name T1262
Test name
Test status
Simulation time 502723704 ps
CPU time 2.42 seconds
Started Mar 12 01:13:03 PM PDT 24
Finished Mar 12 01:13:06 PM PDT 24
Peak memory 224088 kb
Host smart-7495d6c3-1c61-4495-acc8-958cba9d75af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247074202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2247074202
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1842527091
Short name T1764
Test name
Test status
Simulation time 19255626 ps
CPU time 0.78 seconds
Started Mar 12 03:10:46 PM PDT 24
Finished Mar 12 03:10:47 PM PDT 24
Peak memory 204920 kb
Host smart-f2c2651e-f229-46a4-bdd3-185cb602bbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842527091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1842527091
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3714119435
Short name T613
Test name
Test status
Simulation time 25302013 ps
CPU time 0.83 seconds
Started Mar 12 01:13:00 PM PDT 24
Finished Mar 12 01:13:01 PM PDT 24
Peak memory 205940 kb
Host smart-7bbd81b6-0e57-4e76-b42f-f10c4bc6c80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714119435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3714119435
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.3164171298
Short name T1872
Test name
Test status
Simulation time 8293421121 ps
CPU time 83.17 seconds
Started Mar 12 01:13:03 PM PDT 24
Finished Mar 12 01:14:26 PM PDT 24
Peak memory 265136 kb
Host smart-bbd067d5-4570-4cec-aafd-5d75845ebfdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164171298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3164171298
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.3665696726
Short name T1001
Test name
Test status
Simulation time 244503350209 ps
CPU time 505.58 seconds
Started Mar 12 03:10:50 PM PDT 24
Finished Mar 12 03:19:16 PM PDT 24
Peak memory 265208 kb
Host smart-fbd2517e-bee7-446d-acdb-817cdeb19f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665696726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3665696726
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3568845169
Short name T853
Test name
Test status
Simulation time 40917488423 ps
CPU time 290.75 seconds
Started Mar 12 01:13:03 PM PDT 24
Finished Mar 12 01:17:54 PM PDT 24
Peak memory 248900 kb
Host smart-150f959d-8def-42aa-a67a-ff6030ad7b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568845169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3568845169
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3781101245
Short name T1302
Test name
Test status
Simulation time 15490987250 ps
CPU time 159.58 seconds
Started Mar 12 03:10:51 PM PDT 24
Finished Mar 12 03:13:31 PM PDT 24
Peak memory 257196 kb
Host smart-142a5ced-ac90-4350-b1e2-0876d672661c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781101245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3781101245
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.1442246135
Short name T1693
Test name
Test status
Simulation time 55236508006 ps
CPU time 120.29 seconds
Started Mar 12 03:10:51 PM PDT 24
Finished Mar 12 03:12:52 PM PDT 24
Peak memory 267728 kb
Host smart-c1a46cd3-74f3-4af1-b05c-04dbacc96c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442246135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.1442246135
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.349050724
Short name T1127
Test name
Test status
Simulation time 459179418969 ps
CPU time 233.07 seconds
Started Mar 12 01:13:02 PM PDT 24
Finished Mar 12 01:16:56 PM PDT 24
Peak memory 264516 kb
Host smart-4ad7b4cf-4535-43e5-88f3-de01f75cba11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349050724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.349050724
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2052795621
Short name T1531
Test name
Test status
Simulation time 317567887 ps
CPU time 7.73 seconds
Started Mar 12 03:10:49 PM PDT 24
Finished Mar 12 03:10:57 PM PDT 24
Peak memory 236672 kb
Host smart-ea94d8bf-7ea4-4965-b2de-f7458d49fe72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052795621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2052795621
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1391516644
Short name T1926
Test name
Test status
Simulation time 1131658077 ps
CPU time 3.93 seconds
Started Mar 12 01:13:04 PM PDT 24
Finished Mar 12 01:13:09 PM PDT 24
Peak memory 233760 kb
Host smart-e92574c7-77d7-4154-b173-f05ad94f3531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391516644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1391516644
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_intercept.803605755
Short name T669
Test name
Test status
Simulation time 345126167 ps
CPU time 2.54 seconds
Started Mar 12 03:10:49 PM PDT 24
Finished Mar 12 03:10:52 PM PDT 24
Peak memory 224120 kb
Host smart-27f2d25e-0fc7-4181-9c90-7a79924e551e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803605755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.803605755
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1785376255
Short name T235
Test name
Test status
Simulation time 502349906 ps
CPU time 8.28 seconds
Started Mar 12 01:13:06 PM PDT 24
Finished Mar 12 01:13:14 PM PDT 24
Peak memory 221816 kb
Host smart-cdc5ac99-34bb-477b-98cd-751619237165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785376255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1785376255
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.4022117623
Short name T1473
Test name
Test status
Simulation time 2609948472 ps
CPU time 6.41 seconds
Started Mar 12 03:10:49 PM PDT 24
Finished Mar 12 03:10:56 PM PDT 24
Peak memory 232424 kb
Host smart-019c7d19-76fa-40f1-8393-d414bcd918d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022117623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.4022117623
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2876507847
Short name T1516
Test name
Test status
Simulation time 15077596475 ps
CPU time 14.2 seconds
Started Mar 12 03:10:49 PM PDT 24
Finished Mar 12 03:11:03 PM PDT 24
Peak memory 236964 kb
Host smart-449be8a2-a330-42b6-a8bd-639e6fd59e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876507847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2876507847
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3822255022
Short name T838
Test name
Test status
Simulation time 99437936 ps
CPU time 2.38 seconds
Started Mar 12 01:13:02 PM PDT 24
Finished Mar 12 01:13:04 PM PDT 24
Peak memory 216608 kb
Host smart-8209563f-8411-4c22-8002-44a4aa547a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822255022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3822255022
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1795281872
Short name T541
Test name
Test status
Simulation time 4020883114 ps
CPU time 3.58 seconds
Started Mar 12 01:13:04 PM PDT 24
Finished Mar 12 01:13:08 PM PDT 24
Peak memory 224144 kb
Host smart-f5dbfb38-9fa9-4cd7-b4c8-81c73b9f1cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795281872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1795281872
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3740402201
Short name T1686
Test name
Test status
Simulation time 2130427156 ps
CPU time 5.25 seconds
Started Mar 12 03:10:50 PM PDT 24
Finished Mar 12 03:10:55 PM PDT 24
Peak memory 224124 kb
Host smart-8be61b1b-9f9c-428c-9177-420d48e37680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740402201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3740402201
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1913582659
Short name T942
Test name
Test status
Simulation time 551769588 ps
CPU time 4.73 seconds
Started Mar 12 03:10:49 PM PDT 24
Finished Mar 12 03:10:54 PM PDT 24
Peak memory 222200 kb
Host smart-d9164b18-0da8-4eb6-b2b2-1fa65bbbb3fe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1913582659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1913582659
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2538376470
Short name T1322
Test name
Test status
Simulation time 7627343060 ps
CPU time 3.97 seconds
Started Mar 12 01:13:02 PM PDT 24
Finished Mar 12 01:13:06 PM PDT 24
Peak memory 216352 kb
Host smart-d530d8c0-55c9-4e9b-b5a4-3f89068f6ea4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2538376470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2538376470
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1558066543
Short name T477
Test name
Test status
Simulation time 186439930 ps
CPU time 1.16 seconds
Started Mar 12 01:13:03 PM PDT 24
Finished Mar 12 01:13:05 PM PDT 24
Peak memory 206232 kb
Host smart-89d39eec-c7b0-4aaa-a96f-cd9190996dad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558066543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1558066543
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.481995320
Short name T1041
Test name
Test status
Simulation time 209987385 ps
CPU time 0.98 seconds
Started Mar 12 03:10:48 PM PDT 24
Finished Mar 12 03:10:50 PM PDT 24
Peak memory 205944 kb
Host smart-186258f2-2313-4c54-b929-6f1dfda607aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481995320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.481995320
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2411965775
Short name T1192
Test name
Test status
Simulation time 935576468 ps
CPU time 14.19 seconds
Started Mar 12 01:12:59 PM PDT 24
Finished Mar 12 01:13:14 PM PDT 24
Peak memory 216052 kb
Host smart-f63f904a-c00e-4bfa-960d-1346e91280e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411965775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2411965775
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3977564798
Short name T377
Test name
Test status
Simulation time 10006298922 ps
CPU time 29.89 seconds
Started Mar 12 03:10:51 PM PDT 24
Finished Mar 12 03:11:21 PM PDT 24
Peak memory 216184 kb
Host smart-c5f029c9-ef36-4382-880b-d52133be2906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977564798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3977564798
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2958417770
Short name T1598
Test name
Test status
Simulation time 762266665 ps
CPU time 4.95 seconds
Started Mar 12 01:13:01 PM PDT 24
Finished Mar 12 01:13:07 PM PDT 24
Peak memory 216052 kb
Host smart-40ff61a3-65fa-491e-8e10-1c9352a497e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958417770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2958417770
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3713820049
Short name T353
Test name
Test status
Simulation time 2354673771 ps
CPU time 8.73 seconds
Started Mar 12 03:10:49 PM PDT 24
Finished Mar 12 03:10:58 PM PDT 24
Peak memory 216164 kb
Host smart-b60871cd-325e-4365-83af-c3f3d8aa068b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713820049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3713820049
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1006171421
Short name T1525
Test name
Test status
Simulation time 912673288 ps
CPU time 1.66 seconds
Started Mar 12 01:13:01 PM PDT 24
Finished Mar 12 01:13:04 PM PDT 24
Peak memory 216108 kb
Host smart-ea59e703-043d-4b59-9e19-4019dcfcc4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006171421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1006171421
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.225869417
Short name T1544
Test name
Test status
Simulation time 227618608 ps
CPU time 2.29 seconds
Started Mar 12 03:10:49 PM PDT 24
Finished Mar 12 03:10:52 PM PDT 24
Peak memory 216256 kb
Host smart-3d10f16c-6732-4619-a0d9-85941ee68f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225869417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.225869417
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1346754692
Short name T1424
Test name
Test status
Simulation time 75781888 ps
CPU time 0.78 seconds
Started Mar 12 03:10:47 PM PDT 24
Finished Mar 12 03:10:48 PM PDT 24
Peak memory 205280 kb
Host smart-b6df58df-4957-462a-ab40-f2d9654e0c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346754692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1346754692
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.987297831
Short name T769
Test name
Test status
Simulation time 553581803 ps
CPU time 1 seconds
Started Mar 12 01:13:01 PM PDT 24
Finished Mar 12 01:13:03 PM PDT 24
Peak memory 205280 kb
Host smart-6ba5bcfe-45c4-412a-b3c5-f24ec483154b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987297831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.987297831
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2123228784
Short name T1368
Test name
Test status
Simulation time 500259771 ps
CPU time 3.17 seconds
Started Mar 12 01:13:02 PM PDT 24
Finished Mar 12 01:13:06 PM PDT 24
Peak memory 232928 kb
Host smart-aa460f01-50ec-4b05-9d74-74e50af96d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123228784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2123228784
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_upload.4140161701
Short name T914
Test name
Test status
Simulation time 1584854082 ps
CPU time 7.21 seconds
Started Mar 12 03:10:49 PM PDT 24
Finished Mar 12 03:10:56 PM PDT 24
Peak memory 233416 kb
Host smart-b890919a-dacb-473b-b3d2-9d60e0564287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140161701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.4140161701
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3807511909
Short name T798
Test name
Test status
Simulation time 12830429 ps
CPU time 0.82 seconds
Started Mar 12 03:11:01 PM PDT 24
Finished Mar 12 03:11:02 PM PDT 24
Peak memory 204820 kb
Host smart-43d05a53-199d-4efa-bda4-1b2827c7ee98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807511909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3807511909
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.448813366
Short name T1241
Test name
Test status
Simulation time 29512013 ps
CPU time 0.72 seconds
Started Mar 12 01:13:17 PM PDT 24
Finished Mar 12 01:13:18 PM PDT 24
Peak memory 204800 kb
Host smart-89c9dc62-5efc-49ab-a4d4-0ea5698bad40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448813366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.448813366
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.243590667
Short name T1562
Test name
Test status
Simulation time 60436529 ps
CPU time 2.85 seconds
Started Mar 12 01:13:23 PM PDT 24
Finished Mar 12 01:13:26 PM PDT 24
Peak memory 232920 kb
Host smart-da6caa78-641c-4de0-b612-6d3b3bfca418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243590667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.243590667
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.4287433232
Short name T916
Test name
Test status
Simulation time 696513308 ps
CPU time 4.25 seconds
Started Mar 12 03:11:01 PM PDT 24
Finished Mar 12 03:11:06 PM PDT 24
Peak memory 220228 kb
Host smart-51b33790-a76b-4f83-bc49-96906b3dd5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287433232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.4287433232
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1585406377
Short name T905
Test name
Test status
Simulation time 84155940 ps
CPU time 0.84 seconds
Started Mar 12 01:13:02 PM PDT 24
Finished Mar 12 01:13:03 PM PDT 24
Peak memory 205880 kb
Host smart-88e0af7c-4235-42aa-a94e-d88b2ebd25fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585406377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1585406377
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.507795458
Short name T1506
Test name
Test status
Simulation time 74714059 ps
CPU time 0.79 seconds
Started Mar 12 03:10:48 PM PDT 24
Finished Mar 12 03:10:50 PM PDT 24
Peak memory 206276 kb
Host smart-d3830a41-87f7-42b4-8de6-e686b503f211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507795458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.507795458
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1988976231
Short name T1735
Test name
Test status
Simulation time 8494846628 ps
CPU time 41.01 seconds
Started Mar 12 03:11:02 PM PDT 24
Finished Mar 12 03:11:44 PM PDT 24
Peak memory 232464 kb
Host smart-3b8c66e0-365b-4554-a2b3-d5225cfe7dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988976231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1988976231
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2367953437
Short name T215
Test name
Test status
Simulation time 9584984258 ps
CPU time 33.66 seconds
Started Mar 12 01:13:20 PM PDT 24
Finished Mar 12 01:13:54 PM PDT 24
Peak memory 240144 kb
Host smart-50cec1de-4fc4-480f-b142-bf205dd96fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367953437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2367953437
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2871268378
Short name T890
Test name
Test status
Simulation time 28711255471 ps
CPU time 61.87 seconds
Started Mar 12 01:13:20 PM PDT 24
Finished Mar 12 01:14:22 PM PDT 24
Peak memory 237584 kb
Host smart-397d0c68-b32c-4301-9bfa-bfa19ea251c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871268378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2871268378
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.4003305690
Short name T817
Test name
Test status
Simulation time 3572490534 ps
CPU time 55.1 seconds
Started Mar 12 03:11:02 PM PDT 24
Finished Mar 12 03:11:58 PM PDT 24
Peak memory 248900 kb
Host smart-7f1087e0-d755-458b-b505-050a629da21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003305690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.4003305690
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1497554353
Short name T1475
Test name
Test status
Simulation time 153102769106 ps
CPU time 665.57 seconds
Started Mar 12 01:13:19 PM PDT 24
Finished Mar 12 01:24:25 PM PDT 24
Peak memory 266328 kb
Host smart-53e2ad91-c7c5-43a9-9b64-8930a20ef1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497554353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.1497554353
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3981113604
Short name T564
Test name
Test status
Simulation time 4994709413 ps
CPU time 113.11 seconds
Started Mar 12 03:11:03 PM PDT 24
Finished Mar 12 03:12:57 PM PDT 24
Peak memory 257180 kb
Host smart-7bf04c9c-48b9-4102-948c-3f1a1c5cd1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981113604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3981113604
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1555882349
Short name T313
Test name
Test status
Simulation time 5369157444 ps
CPU time 31.18 seconds
Started Mar 12 03:11:01 PM PDT 24
Finished Mar 12 03:11:32 PM PDT 24
Peak memory 247532 kb
Host smart-8312ca63-180f-431d-8437-d72bcfae00ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555882349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1555882349
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3634286325
Short name T369
Test name
Test status
Simulation time 302488388 ps
CPU time 6.51 seconds
Started Mar 12 01:13:18 PM PDT 24
Finished Mar 12 01:13:26 PM PDT 24
Peak memory 238900 kb
Host smart-f9322863-638d-4c3a-82c3-292e972cbf7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634286325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3634286325
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3987510944
Short name T460
Test name
Test status
Simulation time 3231082093 ps
CPU time 5.88 seconds
Started Mar 12 03:10:51 PM PDT 24
Finished Mar 12 03:10:57 PM PDT 24
Peak memory 233252 kb
Host smart-dfc96973-7014-4f5b-a6d1-5a4df3de168f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987510944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3987510944
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_intercept.437197433
Short name T909
Test name
Test status
Simulation time 12670527995 ps
CPU time 8.22 seconds
Started Mar 12 01:13:18 PM PDT 24
Finished Mar 12 01:13:28 PM PDT 24
Peak memory 232588 kb
Host smart-77b28c86-5e8b-466f-8749-2823fe1314da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437197433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.437197433
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2015478032
Short name T1670
Test name
Test status
Simulation time 3016741447 ps
CPU time 9.47 seconds
Started Mar 12 03:10:58 PM PDT 24
Finished Mar 12 03:11:08 PM PDT 24
Peak memory 233240 kb
Host smart-ac2269ec-3a37-4370-9e5a-3cdf288f131b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015478032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2015478032
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2728377403
Short name T958
Test name
Test status
Simulation time 9456333282 ps
CPU time 31.15 seconds
Started Mar 12 01:13:20 PM PDT 24
Finished Mar 12 01:13:51 PM PDT 24
Peak memory 247204 kb
Host smart-171e2e30-25b4-4e75-958f-6dc2fd8c5ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728377403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2728377403
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1622973371
Short name T260
Test name
Test status
Simulation time 11308305916 ps
CPU time 8.07 seconds
Started Mar 12 01:13:20 PM PDT 24
Finished Mar 12 01:13:28 PM PDT 24
Peak memory 232760 kb
Host smart-9d4ab278-7cc3-4d30-9635-45dcf9d4a42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622973371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1622973371
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.97723197
Short name T306
Test name
Test status
Simulation time 1472838943 ps
CPU time 5.35 seconds
Started Mar 12 03:10:49 PM PDT 24
Finished Mar 12 03:10:55 PM PDT 24
Peak memory 232376 kb
Host smart-952e1baa-2c72-4ab6-807e-e81b4fe2fa4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97723197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap.97723197
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3742927629
Short name T554
Test name
Test status
Simulation time 10661051798 ps
CPU time 19.31 seconds
Started Mar 12 01:13:19 PM PDT 24
Finished Mar 12 01:13:39 PM PDT 24
Peak memory 232672 kb
Host smart-291d7693-33c1-4b20-ad33-35290969589f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742927629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3742927629
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.414316190
Short name T225
Test name
Test status
Simulation time 10577231217 ps
CPU time 13.55 seconds
Started Mar 12 03:10:51 PM PDT 24
Finished Mar 12 03:11:05 PM PDT 24
Peak memory 218664 kb
Host smart-bafb9d20-8ec3-4661-a480-2df0e36992e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414316190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.414316190
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3637335964
Short name T1690
Test name
Test status
Simulation time 2534584902 ps
CPU time 4.68 seconds
Started Mar 12 03:11:02 PM PDT 24
Finished Mar 12 03:11:07 PM PDT 24
Peak memory 216320 kb
Host smart-892367ca-c4cc-4593-a330-12c4a0bfe523
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3637335964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3637335964
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.985881086
Short name T508
Test name
Test status
Simulation time 334105350 ps
CPU time 3.55 seconds
Started Mar 12 01:13:19 PM PDT 24
Finished Mar 12 01:13:23 PM PDT 24
Peak memory 218644 kb
Host smart-0f34afcd-7663-4ef7-a7b1-6841cd8e2b11
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=985881086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dire
ct.985881086
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.4081555548
Short name T822
Test name
Test status
Simulation time 35702169 ps
CPU time 0.97 seconds
Started Mar 12 03:11:03 PM PDT 24
Finished Mar 12 03:11:04 PM PDT 24
Peak memory 205836 kb
Host smart-4b5ed10f-ee2c-43f4-af47-391b1181a692
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081555548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.4081555548
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.544498466
Short name T91
Test name
Test status
Simulation time 27075326157 ps
CPU time 195.94 seconds
Started Mar 12 01:13:20 PM PDT 24
Finished Mar 12 01:16:37 PM PDT 24
Peak memory 256412 kb
Host smart-56dd0093-c466-478d-a6c9-adeef6e18952
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544498466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stres
s_all.544498466
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1588744826
Short name T1417
Test name
Test status
Simulation time 2495938659 ps
CPU time 13.28 seconds
Started Mar 12 01:13:01 PM PDT 24
Finished Mar 12 01:13:15 PM PDT 24
Peak memory 216132 kb
Host smart-0b662663-8b6a-45cb-a836-0c9f9c7afb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588744826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1588744826
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3819836486
Short name T864
Test name
Test status
Simulation time 520498176 ps
CPU time 5.73 seconds
Started Mar 12 03:10:52 PM PDT 24
Finished Mar 12 03:10:57 PM PDT 24
Peak memory 216072 kb
Host smart-307f9a39-d86a-4294-9555-78d47e0e6a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819836486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3819836486
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3754476696
Short name T1618
Test name
Test status
Simulation time 4248369322 ps
CPU time 13.79 seconds
Started Mar 12 03:10:51 PM PDT 24
Finished Mar 12 03:11:05 PM PDT 24
Peak memory 216532 kb
Host smart-7b041cbb-8bfa-4a39-90c4-462c1c75cf4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754476696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3754476696
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.4287436340
Short name T1281
Test name
Test status
Simulation time 5097974311 ps
CPU time 18.88 seconds
Started Mar 12 01:13:01 PM PDT 24
Finished Mar 12 01:13:21 PM PDT 24
Peak memory 216052 kb
Host smart-7d528f6f-cd11-4bbd-adf0-230071513181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287436340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.4287436340
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1038707018
Short name T1816
Test name
Test status
Simulation time 41665090 ps
CPU time 1.53 seconds
Started Mar 12 01:13:18 PM PDT 24
Finished Mar 12 01:13:21 PM PDT 24
Peak memory 215952 kb
Host smart-83261f71-2dbd-4261-b826-139bb171a5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038707018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1038707018
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3084639433
Short name T651
Test name
Test status
Simulation time 114235557 ps
CPU time 1.71 seconds
Started Mar 12 03:10:51 PM PDT 24
Finished Mar 12 03:10:53 PM PDT 24
Peak memory 216044 kb
Host smart-82162831-5244-4262-87e8-ac8f3372fada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084639433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3084639433
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1548148575
Short name T1238
Test name
Test status
Simulation time 190915048 ps
CPU time 0.92 seconds
Started Mar 12 01:13:16 PM PDT 24
Finished Mar 12 01:13:17 PM PDT 24
Peak memory 205732 kb
Host smart-7f0f791b-fec7-4e1b-92d5-98c45ca13017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548148575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1548148575
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1751155338
Short name T1175
Test name
Test status
Simulation time 28358768 ps
CPU time 0.8 seconds
Started Mar 12 03:10:48 PM PDT 24
Finished Mar 12 03:10:49 PM PDT 24
Peak memory 205252 kb
Host smart-739202f9-561b-432c-a481-4893ef4dbe9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751155338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1751155338
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.3120499006
Short name T1643
Test name
Test status
Simulation time 880579450 ps
CPU time 5.09 seconds
Started Mar 12 01:13:19 PM PDT 24
Finished Mar 12 01:13:25 PM PDT 24
Peak memory 236248 kb
Host smart-ad3578d7-e049-493e-80db-306b1b1865ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120499006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3120499006
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_upload.3428950228
Short name T661
Test name
Test status
Simulation time 961631086 ps
CPU time 4.69 seconds
Started Mar 12 03:11:02 PM PDT 24
Finished Mar 12 03:11:07 PM PDT 24
Peak memory 235168 kb
Host smart-47dde7db-4376-487e-90c8-a02553e36070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428950228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3428950228
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2862387403
Short name T1208
Test name
Test status
Simulation time 25495736 ps
CPU time 0.74 seconds
Started Mar 12 01:13:22 PM PDT 24
Finished Mar 12 01:13:23 PM PDT 24
Peak memory 204780 kb
Host smart-3da06221-2f79-4198-abfa-a021eaa251a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862387403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2862387403
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3134373244
Short name T1185
Test name
Test status
Simulation time 18677377 ps
CPU time 0.74 seconds
Started Mar 12 03:11:02 PM PDT 24
Finished Mar 12 03:11:03 PM PDT 24
Peak memory 204804 kb
Host smart-8304347e-76fc-4326-8ce1-8c17e445a09d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134373244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3134373244
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1422493746
Short name T1522
Test name
Test status
Simulation time 39604066 ps
CPU time 2.23 seconds
Started Mar 12 01:13:19 PM PDT 24
Finished Mar 12 01:13:22 PM PDT 24
Peak memory 216112 kb
Host smart-7d65bef7-5e25-4ada-9535-3adbf3eb8273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422493746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1422493746
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.2700381923
Short name T612
Test name
Test status
Simulation time 204694049 ps
CPU time 3.03 seconds
Started Mar 12 03:11:04 PM PDT 24
Finished Mar 12 03:11:07 PM PDT 24
Peak memory 235640 kb
Host smart-bd658c03-0507-45d4-a58e-2a2280f656e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700381923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2700381923
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1852198392
Short name T491
Test name
Test status
Simulation time 40465844 ps
CPU time 0.79 seconds
Started Mar 12 03:11:01 PM PDT 24
Finished Mar 12 03:11:01 PM PDT 24
Peak memory 205948 kb
Host smart-db632918-5ad1-4bd7-b1fc-78249a934af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852198392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1852198392
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2472829985
Short name T335
Test name
Test status
Simulation time 26246825 ps
CPU time 0.76 seconds
Started Mar 12 01:13:18 PM PDT 24
Finished Mar 12 01:13:20 PM PDT 24
Peak memory 205968 kb
Host smart-9a51e1a8-ab2e-4f65-af62-8a439792d8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472829985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2472829985
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3297678893
Short name T1921
Test name
Test status
Simulation time 19550618418 ps
CPU time 119.83 seconds
Started Mar 12 01:13:20 PM PDT 24
Finished Mar 12 01:15:20 PM PDT 24
Peak memory 240572 kb
Host smart-10d8d501-2b25-44ad-ab90-e84cdb26fde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297678893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3297678893
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1221152355
Short name T923
Test name
Test status
Simulation time 25674488776 ps
CPU time 68.54 seconds
Started Mar 12 03:11:01 PM PDT 24
Finished Mar 12 03:12:09 PM PDT 24
Peak memory 252936 kb
Host smart-fda26145-12f6-4c13-93b5-0f5f4706438a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221152355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1221152355
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.4058071745
Short name T1803
Test name
Test status
Simulation time 1806150919 ps
CPU time 6.48 seconds
Started Mar 12 01:13:17 PM PDT 24
Finished Mar 12 01:13:24 PM PDT 24
Peak memory 219948 kb
Host smart-a7e5f810-e7f4-43a3-bba5-5f4e1f2fef71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058071745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.4058071745
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1735315066
Short name T1491
Test name
Test status
Simulation time 14747623664 ps
CPU time 121.55 seconds
Started Mar 12 01:13:20 PM PDT 24
Finished Mar 12 01:15:22 PM PDT 24
Peak memory 265320 kb
Host smart-dcfb3232-7fde-431a-9542-c7a938ade699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735315066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1735315066
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1683448303
Short name T940
Test name
Test status
Simulation time 852160005 ps
CPU time 11.04 seconds
Started Mar 12 03:10:59 PM PDT 24
Finished Mar 12 03:11:11 PM PDT 24
Peak memory 238948 kb
Host smart-161a842b-2bba-4542-b880-73f6176365da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683448303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1683448303
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3464462050
Short name T1810
Test name
Test status
Simulation time 6415455856 ps
CPU time 14.96 seconds
Started Mar 12 01:13:23 PM PDT 24
Finished Mar 12 01:13:38 PM PDT 24
Peak memory 239700 kb
Host smart-3fc748f9-a1a6-41ae-a535-eba3b4de368c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464462050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3464462050
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1655354339
Short name T265
Test name
Test status
Simulation time 1090583328 ps
CPU time 5.25 seconds
Started Mar 12 03:11:00 PM PDT 24
Finished Mar 12 03:11:05 PM PDT 24
Peak memory 232748 kb
Host smart-2126209c-6412-450c-b11e-fe4b48a84add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655354339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1655354339
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3049683959
Short name T1217
Test name
Test status
Simulation time 1375991885 ps
CPU time 5.86 seconds
Started Mar 12 01:13:24 PM PDT 24
Finished Mar 12 01:13:31 PM PDT 24
Peak memory 224168 kb
Host smart-38bff719-eba8-4c07-983a-7aa64a683b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049683959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3049683959
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3400745900
Short name T1106
Test name
Test status
Simulation time 4750524360 ps
CPU time 9.24 seconds
Started Mar 12 01:13:25 PM PDT 24
Finished Mar 12 01:13:34 PM PDT 24
Peak memory 232488 kb
Host smart-65b05ea6-b54d-4848-8757-47f8c3f13e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400745900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3400745900
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3755267523
Short name T249
Test name
Test status
Simulation time 576071588 ps
CPU time 10.62 seconds
Started Mar 12 03:11:02 PM PDT 24
Finished Mar 12 03:11:13 PM PDT 24
Peak memory 232424 kb
Host smart-013e3e52-8230-493e-9714-378b32fa4e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755267523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3755267523
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1059856966
Short name T1439
Test name
Test status
Simulation time 975668237 ps
CPU time 6.94 seconds
Started Mar 12 01:13:20 PM PDT 24
Finished Mar 12 01:13:28 PM PDT 24
Peak memory 224216 kb
Host smart-b928a751-1479-4404-a9ca-b79d85e2e189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059856966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1059856966
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3241480856
Short name T266
Test name
Test status
Simulation time 45061556665 ps
CPU time 28.63 seconds
Started Mar 12 03:11:02 PM PDT 24
Finished Mar 12 03:11:30 PM PDT 24
Peak memory 233428 kb
Host smart-1c90d196-43dc-4d5c-88b1-f6ead72d36a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241480856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3241480856
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2079985654
Short name T1703
Test name
Test status
Simulation time 8381687633 ps
CPU time 23.19 seconds
Started Mar 12 01:13:19 PM PDT 24
Finished Mar 12 01:13:43 PM PDT 24
Peak memory 239472 kb
Host smart-5b39167b-0050-4702-87ba-1dd2e2e7c743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079985654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2079985654
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3677104179
Short name T1796
Test name
Test status
Simulation time 498978581 ps
CPU time 9.61 seconds
Started Mar 12 03:10:59 PM PDT 24
Finished Mar 12 03:11:09 PM PDT 24
Peak memory 237608 kb
Host smart-0a209f57-d31a-4f9d-b806-9309b8ffbded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677104179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3677104179
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1070964649
Short name T616
Test name
Test status
Simulation time 461201492 ps
CPU time 3.21 seconds
Started Mar 12 03:11:00 PM PDT 24
Finished Mar 12 03:11:03 PM PDT 24
Peak memory 218756 kb
Host smart-6b303658-f7b2-4b7e-b3ac-1b21e9ca7463
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1070964649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1070964649
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3063323077
Short name T606
Test name
Test status
Simulation time 8146549249 ps
CPU time 5.26 seconds
Started Mar 12 01:13:18 PM PDT 24
Finished Mar 12 01:13:23 PM PDT 24
Peak memory 222424 kb
Host smart-81f11ab1-7980-401c-9f54-929fe4ef5b93
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3063323077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3063323077
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.258983426
Short name T468
Test name
Test status
Simulation time 60128107 ps
CPU time 1.19 seconds
Started Mar 12 03:11:03 PM PDT 24
Finished Mar 12 03:11:04 PM PDT 24
Peak memory 206540 kb
Host smart-5df44c8d-484b-44c7-835f-fa5663234fac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258983426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stres
s_all.258983426
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2734610051
Short name T385
Test name
Test status
Simulation time 22640914504 ps
CPU time 33.39 seconds
Started Mar 12 03:11:02 PM PDT 24
Finished Mar 12 03:11:36 PM PDT 24
Peak memory 216148 kb
Host smart-2d688563-0497-426e-85f5-96c4fdaad6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734610051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2734610051
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.813552256
Short name T1672
Test name
Test status
Simulation time 2400824834 ps
CPU time 5.26 seconds
Started Mar 12 01:13:19 PM PDT 24
Finished Mar 12 01:13:25 PM PDT 24
Peak memory 216056 kb
Host smart-7fa37f02-b91c-4ece-82fe-5887a89fd728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813552256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.813552256
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2356091775
Short name T1853
Test name
Test status
Simulation time 10935637536 ps
CPU time 6.74 seconds
Started Mar 12 01:13:20 PM PDT 24
Finished Mar 12 01:13:27 PM PDT 24
Peak memory 216040 kb
Host smart-1cacce99-3703-4872-9ea4-baebd1b1e673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356091775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2356091775
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2966370205
Short name T403
Test name
Test status
Simulation time 7148148597 ps
CPU time 12.25 seconds
Started Mar 12 03:11:02 PM PDT 24
Finished Mar 12 03:11:14 PM PDT 24
Peak memory 216116 kb
Host smart-dcaf2ec6-de63-46d5-854a-3bb4f5f9bd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966370205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2966370205
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.2317749015
Short name T347
Test name
Test status
Simulation time 536815190 ps
CPU time 1.31 seconds
Started Mar 12 01:13:17 PM PDT 24
Finished Mar 12 01:13:19 PM PDT 24
Peak memory 207104 kb
Host smart-b34d4406-ca66-4b9c-a020-4a7aab273770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317749015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2317749015
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3257015650
Short name T1915
Test name
Test status
Simulation time 980969968 ps
CPU time 2.98 seconds
Started Mar 12 03:11:00 PM PDT 24
Finished Mar 12 03:11:03 PM PDT 24
Peak memory 216136 kb
Host smart-ca368ee9-3faf-4de1-9006-3a90575a5196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257015650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3257015650
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2952460995
Short name T1707
Test name
Test status
Simulation time 77525997 ps
CPU time 0.93 seconds
Started Mar 12 01:13:23 PM PDT 24
Finished Mar 12 01:13:24 PM PDT 24
Peak memory 205292 kb
Host smart-92f05fc7-6037-45c6-984f-2e3426832ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952460995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2952460995
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.627747606
Short name T1849
Test name
Test status
Simulation time 95358345 ps
CPU time 1.03 seconds
Started Mar 12 03:11:02 PM PDT 24
Finished Mar 12 03:11:03 PM PDT 24
Peak memory 206272 kb
Host smart-3713748c-8dff-4757-a4d1-8fa4b88c6b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627747606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.627747606
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.560285476
Short name T1095
Test name
Test status
Simulation time 7019341351 ps
CPU time 7.2 seconds
Started Mar 12 01:13:20 PM PDT 24
Finished Mar 12 01:13:28 PM PDT 24
Peak memory 233084 kb
Host smart-ab7dd677-53c2-4257-8c78-290b911cc6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560285476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.560285476
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_upload.835762793
Short name T1129
Test name
Test status
Simulation time 7566782710 ps
CPU time 14.68 seconds
Started Mar 12 03:11:02 PM PDT 24
Finished Mar 12 03:11:17 PM PDT 24
Peak memory 248860 kb
Host smart-08046d97-f60b-4790-9f9b-37b3344f04a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835762793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.835762793
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2587569096
Short name T692
Test name
Test status
Simulation time 65140229 ps
CPU time 0.72 seconds
Started Mar 12 03:06:00 PM PDT 24
Finished Mar 12 03:06:02 PM PDT 24
Peak memory 204232 kb
Host smart-71903726-de54-410f-84ab-75d485b702fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587569096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
587569096
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3322011803
Short name T378
Test name
Test status
Simulation time 12032134 ps
CPU time 0.69 seconds
Started Mar 12 01:10:45 PM PDT 24
Finished Mar 12 01:10:46 PM PDT 24
Peak memory 204780 kb
Host smart-bf7b2b4f-83b7-45cd-acb6-ec938e508216
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322011803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
322011803
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2630317817
Short name T1784
Test name
Test status
Simulation time 237381340 ps
CPU time 2.88 seconds
Started Mar 12 03:05:58 PM PDT 24
Finished Mar 12 03:06:01 PM PDT 24
Peak memory 233264 kb
Host smart-dd26781e-4cc1-498b-8b8e-fd1f476ecee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630317817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2630317817
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2754558504
Short name T1120
Test name
Test status
Simulation time 1215098852 ps
CPU time 2.73 seconds
Started Mar 12 01:10:41 PM PDT 24
Finished Mar 12 01:10:44 PM PDT 24
Peak memory 216976 kb
Host smart-530861c4-c338-46c0-94d0-ab8181b49752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754558504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2754558504
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1608518270
Short name T944
Test name
Test status
Simulation time 30242366 ps
CPU time 0.77 seconds
Started Mar 12 03:05:50 PM PDT 24
Finished Mar 12 03:05:51 PM PDT 24
Peak memory 206300 kb
Host smart-62daee69-fc2e-4218-9e84-aa351e986ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608518270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1608518270
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.598662424
Short name T13
Test name
Test status
Simulation time 27039192 ps
CPU time 0.76 seconds
Started Mar 12 01:10:39 PM PDT 24
Finished Mar 12 01:10:40 PM PDT 24
Peak memory 205232 kb
Host smart-3ce9c2cd-0452-4fc1-bae1-378c07698fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598662424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.598662424
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2113595223
Short name T1604
Test name
Test status
Simulation time 3715733911 ps
CPU time 65.34 seconds
Started Mar 12 01:10:48 PM PDT 24
Finished Mar 12 01:11:54 PM PDT 24
Peak memory 250756 kb
Host smart-eec69690-0241-437b-b9d2-8cf00a320b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113595223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2113595223
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3522101984
Short name T1692
Test name
Test status
Simulation time 325687402454 ps
CPU time 107.83 seconds
Started Mar 12 03:05:59 PM PDT 24
Finished Mar 12 03:07:48 PM PDT 24
Peak memory 248812 kb
Host smart-be320693-d091-4425-9cb7-7c977a448b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522101984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3522101984
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.4049843610
Short name T510
Test name
Test status
Simulation time 28611275513 ps
CPU time 152.88 seconds
Started Mar 12 01:10:46 PM PDT 24
Finished Mar 12 01:13:19 PM PDT 24
Peak memory 262116 kb
Host smart-be30ef2a-9601-4c6f-bd48-c433b47f9c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049843610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.4049843610
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.786858886
Short name T1031
Test name
Test status
Simulation time 15546033357 ps
CPU time 121.77 seconds
Started Mar 12 03:06:02 PM PDT 24
Finished Mar 12 03:08:04 PM PDT 24
Peak memory 254496 kb
Host smart-93e83cb4-5f8d-46ff-84ab-91b92e5fee7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786858886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.786858886
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2820798064
Short name T1771
Test name
Test status
Simulation time 36197037351 ps
CPU time 166.06 seconds
Started Mar 12 03:06:01 PM PDT 24
Finished Mar 12 03:08:47 PM PDT 24
Peak memory 250412 kb
Host smart-6741fa87-7847-4e43-b2eb-569d0184a7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820798064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2820798064
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.4030308525
Short name T1871
Test name
Test status
Simulation time 61263800833 ps
CPU time 492.03 seconds
Started Mar 12 01:10:46 PM PDT 24
Finished Mar 12 01:18:58 PM PDT 24
Peak memory 268204 kb
Host smart-5c9d426e-c92d-4b8f-9e68-64c38952c143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030308525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.4030308525
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3914022111
Short name T1193
Test name
Test status
Simulation time 28312326300 ps
CPU time 24.61 seconds
Started Mar 12 01:10:39 PM PDT 24
Finished Mar 12 01:11:04 PM PDT 24
Peak memory 245864 kb
Host smart-96cb4af0-df09-4b39-afed-672f1b8a8130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914022111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3914022111
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.675336711
Short name T724
Test name
Test status
Simulation time 631329054 ps
CPU time 9.33 seconds
Started Mar 12 03:05:59 PM PDT 24
Finished Mar 12 03:06:08 PM PDT 24
Peak memory 236672 kb
Host smart-58bec59a-652e-4684-a43e-830d4e174d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675336711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.675336711
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.4049915122
Short name T1483
Test name
Test status
Simulation time 835265302 ps
CPU time 4.7 seconds
Started Mar 12 01:10:46 PM PDT 24
Finished Mar 12 01:10:51 PM PDT 24
Peak memory 218320 kb
Host smart-aa6fc42c-dfb0-48e3-9fb7-ac2094b41bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049915122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.4049915122
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_intercept.4153041799
Short name T805
Test name
Test status
Simulation time 345986727 ps
CPU time 2.09 seconds
Started Mar 12 03:05:58 PM PDT 24
Finished Mar 12 03:06:01 PM PDT 24
Peak memory 217504 kb
Host smart-bd033fa4-759e-4b72-a16b-e0ae18023ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153041799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.4153041799
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1866186596
Short name T1536
Test name
Test status
Simulation time 1895306522 ps
CPU time 12.3 seconds
Started Mar 12 03:05:58 PM PDT 24
Finished Mar 12 03:06:11 PM PDT 24
Peak memory 232752 kb
Host smart-997cffbf-63e7-4cba-8266-53401abafdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866186596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1866186596
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2936637259
Short name T1119
Test name
Test status
Simulation time 36005472898 ps
CPU time 25.01 seconds
Started Mar 12 01:10:39 PM PDT 24
Finished Mar 12 01:11:04 PM PDT 24
Peak memory 224236 kb
Host smart-0fd1260c-edd7-448a-85e0-bc302ea78636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936637259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2936637259
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.1062978804
Short name T1653
Test name
Test status
Simulation time 20720845 ps
CPU time 1.01 seconds
Started Mar 12 03:05:50 PM PDT 24
Finished Mar 12 03:05:51 PM PDT 24
Peak memory 216356 kb
Host smart-ab8b7794-5eac-4040-8e4d-f7a9308cada2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062978804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.1062978804
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.3150443584
Short name T555
Test name
Test status
Simulation time 24966834 ps
CPU time 1 seconds
Started Mar 12 01:10:40 PM PDT 24
Finished Mar 12 01:10:41 PM PDT 24
Peak memory 217608 kb
Host smart-b759af7d-13cd-4f4d-96f7-73ef257b4853
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150443584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.3150443584
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2209533563
Short name T1251
Test name
Test status
Simulation time 115229071 ps
CPU time 3.73 seconds
Started Mar 12 03:05:59 PM PDT 24
Finished Mar 12 03:06:05 PM PDT 24
Peak memory 234404 kb
Host smart-2a1a6926-876c-4ce0-8d1c-fc4ec25fac75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209533563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2209533563
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.871318803
Short name T1763
Test name
Test status
Simulation time 965184640 ps
CPU time 3.72 seconds
Started Mar 12 01:10:39 PM PDT 24
Finished Mar 12 01:10:43 PM PDT 24
Peak memory 216448 kb
Host smart-5be217b5-2f0c-437c-a4ec-07229576a89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871318803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.
871318803
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3463249973
Short name T803
Test name
Test status
Simulation time 1088865908 ps
CPU time 11.89 seconds
Started Mar 12 01:10:43 PM PDT 24
Finished Mar 12 01:10:56 PM PDT 24
Peak memory 239216 kb
Host smart-256ce010-2e14-4352-817c-a12924c68056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463249973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3463249973
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.793888708
Short name T169
Test name
Test status
Simulation time 922483686 ps
CPU time 6.39 seconds
Started Mar 12 03:05:49 PM PDT 24
Finished Mar 12 03:05:56 PM PDT 24
Peak memory 233060 kb
Host smart-1a204889-3d88-4ae2-8fef-0888b3e768a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793888708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.793888708
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.3840854937
Short name T1130
Test name
Test status
Simulation time 28826731 ps
CPU time 0.72 seconds
Started Mar 12 03:05:49 PM PDT 24
Finished Mar 12 03:05:50 PM PDT 24
Peak memory 215940 kb
Host smart-b5adbb4e-7794-420e-850c-6b10de834f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840854937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.3840854937
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.635660317
Short name T1484
Test name
Test status
Simulation time 41929163 ps
CPU time 0.72 seconds
Started Mar 12 01:10:43 PM PDT 24
Finished Mar 12 01:10:45 PM PDT 24
Peak memory 215956 kb
Host smart-0bf7ead3-86a7-47f9-8ca0-22590741a955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635660317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.635660317
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1372482067
Short name T1426
Test name
Test status
Simulation time 4662681778 ps
CPU time 7.04 seconds
Started Mar 12 03:05:57 PM PDT 24
Finished Mar 12 03:06:05 PM PDT 24
Peak memory 222544 kb
Host smart-29287a71-06f4-42c5-8f9d-e54a2eb1e3c4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1372482067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1372482067
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3474378798
Short name T1795
Test name
Test status
Simulation time 228953103 ps
CPU time 3.46 seconds
Started Mar 12 01:10:48 PM PDT 24
Finished Mar 12 01:10:51 PM PDT 24
Peak memory 221756 kb
Host smart-81615d84-8248-47f9-9ff0-09448938061f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3474378798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3474378798
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1140502723
Short name T1022
Test name
Test status
Simulation time 432953663492 ps
CPU time 633.27 seconds
Started Mar 12 01:10:41 PM PDT 24
Finished Mar 12 01:21:14 PM PDT 24
Peak memory 281472 kb
Host smart-02eb07e3-9d47-42f3-9b03-d439fb765c67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140502723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1140502723
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3738443727
Short name T53
Test name
Test status
Simulation time 103651377372 ps
CPU time 401.19 seconds
Started Mar 12 03:05:58 PM PDT 24
Finished Mar 12 03:12:39 PM PDT 24
Peak memory 257184 kb
Host smart-1f3f1108-2ba5-4b05-9e4c-24ca00c5561f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738443727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3738443727
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2447505920
Short name T1191
Test name
Test status
Simulation time 2250593945 ps
CPU time 6.64 seconds
Started Mar 12 03:05:49 PM PDT 24
Finished Mar 12 03:05:56 PM PDT 24
Peak memory 216136 kb
Host smart-0bf5a51b-f98a-4706-b798-6ca0b5a2c423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447505920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2447505920
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3319298225
Short name T1197
Test name
Test status
Simulation time 9700006742 ps
CPU time 53.57 seconds
Started Mar 12 01:10:37 PM PDT 24
Finished Mar 12 01:11:31 PM PDT 24
Peak memory 216140 kb
Host smart-e6d3400f-5333-4a8d-9153-604c8b7f61e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319298225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3319298225
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2181413763
Short name T1748
Test name
Test status
Simulation time 209193167 ps
CPU time 1.07 seconds
Started Mar 12 01:10:45 PM PDT 24
Finished Mar 12 01:10:46 PM PDT 24
Peak memory 205380 kb
Host smart-6c025201-7ace-498f-8cb1-7599f6257e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181413763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2181413763
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2709400949
Short name T1807
Test name
Test status
Simulation time 10548402938 ps
CPU time 16.64 seconds
Started Mar 12 03:05:48 PM PDT 24
Finished Mar 12 03:06:05 PM PDT 24
Peak memory 216036 kb
Host smart-c9645d6b-0cfe-4b1b-a9c8-d5d78912b01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709400949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2709400949
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.133857378
Short name T1673
Test name
Test status
Simulation time 119816980 ps
CPU time 2.03 seconds
Started Mar 12 01:10:41 PM PDT 24
Finished Mar 12 01:10:43 PM PDT 24
Peak memory 207832 kb
Host smart-20b0a963-7c18-4895-8349-530cb3010d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133857378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.133857378
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3853742473
Short name T1024
Test name
Test status
Simulation time 189409723 ps
CPU time 2.56 seconds
Started Mar 12 03:05:49 PM PDT 24
Finished Mar 12 03:05:52 PM PDT 24
Peak memory 216084 kb
Host smart-fab27d3b-be77-4e15-97e0-8008fd0655a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853742473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3853742473
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1797820123
Short name T604
Test name
Test status
Simulation time 178416296 ps
CPU time 0.89 seconds
Started Mar 12 03:05:49 PM PDT 24
Finished Mar 12 03:05:50 PM PDT 24
Peak memory 206276 kb
Host smart-30238950-3e9b-4b2a-b7eb-dfd9eacb15ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797820123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1797820123
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.9984864
Short name T715
Test name
Test status
Simulation time 175477935 ps
CPU time 0.84 seconds
Started Mar 12 01:10:48 PM PDT 24
Finished Mar 12 01:10:49 PM PDT 24
Peak memory 205224 kb
Host smart-af350040-eb36-4d47-be6a-5ba19073987a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9984864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.9984864
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1351166072
Short name T919
Test name
Test status
Simulation time 1368551791 ps
CPU time 6.34 seconds
Started Mar 12 03:05:58 PM PDT 24
Finished Mar 12 03:06:05 PM PDT 24
Peak memory 224168 kb
Host smart-0fbb643f-64df-46bc-b54e-f5587a1e4a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351166072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1351166072
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_upload.357210783
Short name T965
Test name
Test status
Simulation time 13462302927 ps
CPU time 7.56 seconds
Started Mar 12 01:10:43 PM PDT 24
Finished Mar 12 01:10:51 PM PDT 24
Peak memory 234656 kb
Host smart-61a78c7c-f351-43cf-897f-f3fca4180257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357210783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.357210783
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1695795379
Short name T635
Test name
Test status
Simulation time 25119140 ps
CPU time 0.73 seconds
Started Mar 12 03:06:15 PM PDT 24
Finished Mar 12 03:06:16 PM PDT 24
Peak memory 204932 kb
Host smart-60617e5f-6787-4341-830e-6b0f277f61d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695795379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
695795379
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2345805163
Short name T1668
Test name
Test status
Simulation time 54734217 ps
CPU time 0.75 seconds
Started Mar 12 01:10:55 PM PDT 24
Finished Mar 12 01:10:56 PM PDT 24
Peak memory 204804 kb
Host smart-24a5750f-0571-4b09-8a8d-e437331cd23d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345805163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
345805163
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2655540818
Short name T533
Test name
Test status
Simulation time 627450612 ps
CPU time 3.43 seconds
Started Mar 12 01:10:52 PM PDT 24
Finished Mar 12 01:10:55 PM PDT 24
Peak memory 232684 kb
Host smart-18339db3-7a7a-4c2d-b043-576bb9ae1081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655540818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2655540818
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.417382617
Short name T1077
Test name
Test status
Simulation time 9554289556 ps
CPU time 5.32 seconds
Started Mar 12 03:06:13 PM PDT 24
Finished Mar 12 03:06:19 PM PDT 24
Peak memory 217904 kb
Host smart-7f3b44ed-65f2-41a7-88ee-b3629d01d5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417382617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.417382617
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3427463233
Short name T632
Test name
Test status
Simulation time 21520056 ps
CPU time 0.79 seconds
Started Mar 12 03:05:59 PM PDT 24
Finished Mar 12 03:06:01 PM PDT 24
Peak memory 205936 kb
Host smart-0550d7ce-90a6-4630-91f8-ed998f024e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427463233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3427463233
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3741091729
Short name T665
Test name
Test status
Simulation time 25651767 ps
CPU time 0.77 seconds
Started Mar 12 01:10:43 PM PDT 24
Finished Mar 12 01:10:44 PM PDT 24
Peak memory 205912 kb
Host smart-2b33e73b-f193-467f-be22-33972700374d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741091729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3741091729
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1615929725
Short name T1409
Test name
Test status
Simulation time 6318316798 ps
CPU time 60.62 seconds
Started Mar 12 01:10:57 PM PDT 24
Finished Mar 12 01:11:58 PM PDT 24
Peak memory 257012 kb
Host smart-f458bcf6-021b-4eae-ba92-f39f7a03b736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615929725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1615929725
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.313348950
Short name T938
Test name
Test status
Simulation time 2737474482 ps
CPU time 48.52 seconds
Started Mar 12 03:06:18 PM PDT 24
Finished Mar 12 03:07:07 PM PDT 24
Peak memory 250528 kb
Host smart-0e2d7dad-2179-4120-adc0-c48fa500cdef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313348950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.313348950
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1932306994
Short name T831
Test name
Test status
Simulation time 22927147888 ps
CPU time 67.52 seconds
Started Mar 12 01:10:58 PM PDT 24
Finished Mar 12 01:12:06 PM PDT 24
Peak memory 235732 kb
Host smart-340a675e-8ec0-4e60-839e-245e979984bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932306994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1932306994
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.4239652965
Short name T1888
Test name
Test status
Simulation time 3708260111 ps
CPU time 47.25 seconds
Started Mar 12 03:06:09 PM PDT 24
Finished Mar 12 03:06:56 PM PDT 24
Peak memory 248984 kb
Host smart-32292c0c-2e5f-4d21-9a1e-f555bde22dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239652965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.4239652965
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.1456078709
Short name T322
Test name
Test status
Simulation time 93044909072 ps
CPU time 155.78 seconds
Started Mar 12 01:10:51 PM PDT 24
Finished Mar 12 01:13:27 PM PDT 24
Peak memory 248968 kb
Host smart-17693928-04b2-4d43-903b-352a1e86838c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456078709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.1456078709
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.609867399
Short name T1303
Test name
Test status
Simulation time 6599745821 ps
CPU time 43.53 seconds
Started Mar 12 03:06:19 PM PDT 24
Finished Mar 12 03:07:02 PM PDT 24
Peak memory 255348 kb
Host smart-770f66bf-af90-4034-a98b-0bd1a1ae4b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609867399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
609867399
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3275821096
Short name T1552
Test name
Test status
Simulation time 5084375559 ps
CPU time 15.85 seconds
Started Mar 12 01:10:51 PM PDT 24
Finished Mar 12 01:11:07 PM PDT 24
Peak memory 236692 kb
Host smart-e0c123a7-4161-4f6a-aa17-16f5b3c11023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275821096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3275821096
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.992278068
Short name T1451
Test name
Test status
Simulation time 3418149228 ps
CPU time 20.33 seconds
Started Mar 12 03:06:15 PM PDT 24
Finished Mar 12 03:06:35 PM PDT 24
Peak memory 234404 kb
Host smart-2937dfe6-efc1-45ee-b344-c8080d0a60b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992278068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.992278068
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2255629744
Short name T1406
Test name
Test status
Simulation time 11430914477 ps
CPU time 8.49 seconds
Started Mar 12 03:06:13 PM PDT 24
Finished Mar 12 03:06:22 PM PDT 24
Peak memory 233108 kb
Host smart-f96181cf-27f2-4cab-84a1-40a8527fa60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255629744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2255629744
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2539973565
Short name T219
Test name
Test status
Simulation time 17702436508 ps
CPU time 16.13 seconds
Started Mar 12 01:10:37 PM PDT 24
Finished Mar 12 01:10:54 PM PDT 24
Peak memory 232844 kb
Host smart-bc3b7774-4cc1-43f0-8c10-aa2afdeef12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539973565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2539973565
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1194826426
Short name T906
Test name
Test status
Simulation time 2483800861 ps
CPU time 16.49 seconds
Started Mar 12 03:06:14 PM PDT 24
Finished Mar 12 03:06:30 PM PDT 24
Peak memory 229692 kb
Host smart-cc917161-3e9d-4b3c-96f5-6b9803ea6a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194826426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1194826426
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1753860221
Short name T1186
Test name
Test status
Simulation time 2196110384 ps
CPU time 8.42 seconds
Started Mar 12 01:10:39 PM PDT 24
Finished Mar 12 01:10:47 PM PDT 24
Peak memory 231900 kb
Host smart-ee681695-a4ec-4536-8386-e22b99bf4665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753860221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1753860221
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.2978305767
Short name T1867
Test name
Test status
Simulation time 25473293 ps
CPU time 1.08 seconds
Started Mar 12 01:10:38 PM PDT 24
Finished Mar 12 01:10:39 PM PDT 24
Peak memory 216356 kb
Host smart-074b69cf-f109-4a70-9d21-3d859908aa35
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978305767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.2978305767
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.638615810
Short name T1245
Test name
Test status
Simulation time 26298189 ps
CPU time 1.11 seconds
Started Mar 12 03:05:59 PM PDT 24
Finished Mar 12 03:06:02 PM PDT 24
Peak memory 216352 kb
Host smart-20a7e2a4-3186-455f-aee9-0c56f5dfddbe
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638615810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.spi_device_mem_parity.638615810
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3242357960
Short name T1180
Test name
Test status
Simulation time 1685479702 ps
CPU time 11.11 seconds
Started Mar 12 03:06:07 PM PDT 24
Finished Mar 12 03:06:18 PM PDT 24
Peak memory 228216 kb
Host smart-a03af784-7b80-483e-90fd-20b42e6dfb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242357960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3242357960
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.764150866
Short name T547
Test name
Test status
Simulation time 773827331 ps
CPU time 8.07 seconds
Started Mar 12 01:10:42 PM PDT 24
Finished Mar 12 01:10:51 PM PDT 24
Peak memory 224128 kb
Host smart-14df44d3-73e6-4c84-bf3e-21d24bee6151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764150866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
764150866
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2460304853
Short name T596
Test name
Test status
Simulation time 566986433 ps
CPU time 5.42 seconds
Started Mar 12 03:06:16 PM PDT 24
Finished Mar 12 03:06:21 PM PDT 24
Peak memory 224100 kb
Host smart-8793ed1a-a5a5-4eed-bea3-1a447f023523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460304853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2460304853
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3343961308
Short name T34
Test name
Test status
Simulation time 17077051709 ps
CPU time 17.85 seconds
Started Mar 12 01:10:38 PM PDT 24
Finished Mar 12 01:10:56 PM PDT 24
Peak memory 236980 kb
Host smart-18d4ffe9-303d-4045-b67e-f02a7478882d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343961308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3343961308
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.3609747498
Short name T56
Test name
Test status
Simulation time 22642314 ps
CPU time 0.75 seconds
Started Mar 12 01:10:46 PM PDT 24
Finished Mar 12 01:10:47 PM PDT 24
Peak memory 215992 kb
Host smart-a300ce1b-4e81-4cc7-8a2c-fecc50c0bf05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609747498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.3609747498
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.4067275978
Short name T1079
Test name
Test status
Simulation time 24248382 ps
CPU time 0.8 seconds
Started Mar 12 03:06:00 PM PDT 24
Finished Mar 12 03:06:02 PM PDT 24
Peak memory 215548 kb
Host smart-e0f7f19a-945c-4930-abd0-530b9b7fdd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067275978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.4067275978
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2402675431
Short name T1134
Test name
Test status
Simulation time 1404505666 ps
CPU time 5.65 seconds
Started Mar 12 03:06:15 PM PDT 24
Finished Mar 12 03:06:20 PM PDT 24
Peak memory 218184 kb
Host smart-39c800dd-fbf3-4a1b-ba90-568327ab6f0a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2402675431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2402675431
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.828084806
Short name T893
Test name
Test status
Simulation time 104284440 ps
CPU time 3.66 seconds
Started Mar 12 01:10:51 PM PDT 24
Finished Mar 12 01:10:54 PM PDT 24
Peak memory 222320 kb
Host smart-dafdc0c6-1555-48ea-9956-c8fb33378510
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=828084806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc
t.828084806
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.2172804442
Short name T480
Test name
Test status
Simulation time 242078300 ps
CPU time 0.98 seconds
Started Mar 12 03:06:15 PM PDT 24
Finished Mar 12 03:06:16 PM PDT 24
Peak memory 206164 kb
Host smart-b48ee593-8712-4296-969c-63fab4553d26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172804442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.2172804442
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3916210167
Short name T1929
Test name
Test status
Simulation time 49758273439 ps
CPU time 297.44 seconds
Started Mar 12 01:10:59 PM PDT 24
Finished Mar 12 01:15:56 PM PDT 24
Peak memory 269168 kb
Host smart-149ec5dd-468d-4144-9cb5-4645a1a185aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916210167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3916210167
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.426926459
Short name T721
Test name
Test status
Simulation time 36405280894 ps
CPU time 37.51 seconds
Started Mar 12 01:10:48 PM PDT 24
Finished Mar 12 01:11:25 PM PDT 24
Peak memory 216288 kb
Host smart-8173e53d-5ed4-4717-a141-0aee2395788d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426926459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.426926459
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.60651096
Short name T589
Test name
Test status
Simulation time 7853048537 ps
CPU time 27.47 seconds
Started Mar 12 03:06:01 PM PDT 24
Finished Mar 12 03:06:29 PM PDT 24
Peak memory 215844 kb
Host smart-0eee4c2b-ca40-4d28-b969-35ef4ae69554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60651096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.60651096
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2855507424
Short name T1062
Test name
Test status
Simulation time 7357394910 ps
CPU time 6.56 seconds
Started Mar 12 03:05:59 PM PDT 24
Finished Mar 12 03:06:08 PM PDT 24
Peak memory 216088 kb
Host smart-90ca11fe-5527-49f7-b87f-d6bf824eb51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855507424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2855507424
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.317056536
Short name T358
Test name
Test status
Simulation time 2029888027 ps
CPU time 6.48 seconds
Started Mar 12 01:10:40 PM PDT 24
Finished Mar 12 01:10:46 PM PDT 24
Peak memory 207896 kb
Host smart-9a69819f-d70c-48b8-bca2-d137c87a5a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317056536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.317056536
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.305672638
Short name T349
Test name
Test status
Simulation time 1179429798 ps
CPU time 3.98 seconds
Started Mar 12 01:10:43 PM PDT 24
Finished Mar 12 01:10:48 PM PDT 24
Peak memory 216364 kb
Host smart-32fea71b-26bd-437a-a89a-4af430e67489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305672638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.305672638
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.407079148
Short name T823
Test name
Test status
Simulation time 101208198 ps
CPU time 1.57 seconds
Started Mar 12 03:06:09 PM PDT 24
Finished Mar 12 03:06:10 PM PDT 24
Peak memory 216064 kb
Host smart-82419f48-2f30-419f-b477-afa78d6c309b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407079148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.407079148
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1264140512
Short name T393
Test name
Test status
Simulation time 162106772 ps
CPU time 0.99 seconds
Started Mar 12 01:10:38 PM PDT 24
Finished Mar 12 01:10:39 PM PDT 24
Peak memory 206280 kb
Host smart-6a8a21f3-5fab-45f6-9bc0-ffe262d0abf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264140512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1264140512
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2014323346
Short name T885
Test name
Test status
Simulation time 11879347 ps
CPU time 0.76 seconds
Started Mar 12 03:06:00 PM PDT 24
Finished Mar 12 03:06:02 PM PDT 24
Peak memory 205232 kb
Host smart-f02b7928-db6d-4151-9eee-906f320123d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014323346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2014323346
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1623806339
Short name T49
Test name
Test status
Simulation time 1213321575 ps
CPU time 6.3 seconds
Started Mar 12 03:06:13 PM PDT 24
Finished Mar 12 03:06:20 PM PDT 24
Peak memory 237712 kb
Host smart-59704d5c-7146-4c75-9501-47237b328bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623806339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1623806339
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_upload.2775207517
Short name T1061
Test name
Test status
Simulation time 6994555040 ps
CPU time 9.85 seconds
Started Mar 12 01:10:39 PM PDT 24
Finished Mar 12 01:10:49 PM PDT 24
Peak memory 221180 kb
Host smart-c48db71c-b044-4faa-8903-cbc83e4df43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775207517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2775207517
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1051123380
Short name T852
Test name
Test status
Simulation time 15650576 ps
CPU time 0.7 seconds
Started Mar 12 01:10:52 PM PDT 24
Finished Mar 12 01:10:53 PM PDT 24
Peak memory 204764 kb
Host smart-17f26363-dc26-4853-a419-a0cfa0a09131
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051123380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
051123380
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.175650775
Short name T1200
Test name
Test status
Simulation time 184559714 ps
CPU time 0.68 seconds
Started Mar 12 03:06:16 PM PDT 24
Finished Mar 12 03:06:17 PM PDT 24
Peak memory 204172 kb
Host smart-5288a7d5-f344-4a08-87d1-24d564e01bb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175650775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.175650775
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2274179217
Short name T1574
Test name
Test status
Simulation time 362496976 ps
CPU time 3.81 seconds
Started Mar 12 01:10:53 PM PDT 24
Finished Mar 12 01:10:57 PM PDT 24
Peak memory 217976 kb
Host smart-7c3881f6-421e-4fff-b11f-ae312c97b95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274179217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2274179217
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2995340011
Short name T560
Test name
Test status
Simulation time 398543315 ps
CPU time 3.01 seconds
Started Mar 12 03:06:27 PM PDT 24
Finished Mar 12 03:06:30 PM PDT 24
Peak memory 232820 kb
Host smart-97c29d61-2e2c-4b0f-a158-ccdf4ed3c984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995340011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2995340011
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1228328206
Short name T1316
Test name
Test status
Simulation time 27877676 ps
CPU time 0.72 seconds
Started Mar 12 01:10:57 PM PDT 24
Finished Mar 12 01:10:57 PM PDT 24
Peak memory 204892 kb
Host smart-bc799e57-7232-4cc5-a023-c7a178e2c2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228328206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1228328206
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1520983992
Short name T1194
Test name
Test status
Simulation time 27716545 ps
CPU time 0.74 seconds
Started Mar 12 03:06:10 PM PDT 24
Finished Mar 12 03:06:11 PM PDT 24
Peak memory 204896 kb
Host smart-f3d3e87f-6b4f-4b7e-a989-77832c94877e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520983992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1520983992
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1543418045
Short name T1201
Test name
Test status
Simulation time 12204695217 ps
CPU time 61.74 seconds
Started Mar 12 03:06:20 PM PDT 24
Finished Mar 12 03:07:22 PM PDT 24
Peak memory 253352 kb
Host smart-81745394-ceda-45de-8458-b14e2e2df2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543418045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1543418045
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.4033734375
Short name T190
Test name
Test status
Simulation time 5267300798 ps
CPU time 35 seconds
Started Mar 12 01:10:58 PM PDT 24
Finished Mar 12 01:11:33 PM PDT 24
Peak memory 238064 kb
Host smart-f0126a62-56d3-41b6-93d3-052b52428736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033734375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.4033734375
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2907683534
Short name T405
Test name
Test status
Simulation time 7684828642 ps
CPU time 67.18 seconds
Started Mar 12 03:06:20 PM PDT 24
Finished Mar 12 03:07:28 PM PDT 24
Peak memory 249328 kb
Host smart-5d75a822-c1a5-43d7-a4a0-00f15784f6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907683534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2907683534
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.4035384723
Short name T432
Test name
Test status
Simulation time 14919300026 ps
CPU time 44.86 seconds
Started Mar 12 01:11:04 PM PDT 24
Finished Mar 12 01:11:50 PM PDT 24
Peak memory 240812 kb
Host smart-51d3365e-1a05-4814-8c4d-6ae4c63ba371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035384723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.4035384723
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.115857333
Short name T1038
Test name
Test status
Simulation time 8016456599 ps
CPU time 78.04 seconds
Started Mar 12 01:10:57 PM PDT 24
Finished Mar 12 01:12:15 PM PDT 24
Peak memory 255164 kb
Host smart-36041f10-59c6-487f-b4e2-46cd368a0dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115857333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.
115857333
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.560089018
Short name T1845
Test name
Test status
Simulation time 267245588045 ps
CPU time 339.05 seconds
Started Mar 12 03:06:18 PM PDT 24
Finished Mar 12 03:11:57 PM PDT 24
Peak memory 249580 kb
Host smart-dfcb2eae-ac66-49f8-ac83-a6a53deaad32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560089018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.
560089018
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1531946510
Short name T1909
Test name
Test status
Simulation time 970718000 ps
CPU time 13.68 seconds
Started Mar 12 03:06:20 PM PDT 24
Finished Mar 12 03:06:34 PM PDT 24
Peak memory 250408 kb
Host smart-7f386cfa-9607-439e-a607-a375f2c6b788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531946510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1531946510
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3672962821
Short name T141
Test name
Test status
Simulation time 35073963852 ps
CPU time 37.31 seconds
Started Mar 12 01:10:54 PM PDT 24
Finished Mar 12 01:11:32 PM PDT 24
Peak memory 248324 kb
Host smart-e2f0bee0-89f5-4e99-b709-63710a0c5751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672962821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3672962821
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1799181876
Short name T922
Test name
Test status
Simulation time 389569577 ps
CPU time 3.37 seconds
Started Mar 12 03:06:09 PM PDT 24
Finished Mar 12 03:06:12 PM PDT 24
Peak memory 233032 kb
Host smart-5f0d3f02-48f4-4f69-83bf-323ef15a18d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799181876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1799181876
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2114797860
Short name T381
Test name
Test status
Simulation time 1956459229 ps
CPU time 2.85 seconds
Started Mar 12 01:10:52 PM PDT 24
Finished Mar 12 01:10:55 PM PDT 24
Peak memory 224200 kb
Host smart-265054b1-b18d-4bb8-a30c-904744b22c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114797860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2114797860
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1207414487
Short name T1398
Test name
Test status
Simulation time 36847774058 ps
CPU time 17.14 seconds
Started Mar 12 03:06:18 PM PDT 24
Finished Mar 12 03:06:35 PM PDT 24
Peak memory 240004 kb
Host smart-b2359125-4bbc-49ed-be86-c86c5655cf14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207414487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1207414487
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2829789922
Short name T502
Test name
Test status
Simulation time 2054854323 ps
CPU time 11.05 seconds
Started Mar 12 01:10:52 PM PDT 24
Finished Mar 12 01:11:03 PM PDT 24
Peak memory 234056 kb
Host smart-984a834c-e1bd-4246-a8ea-3e15981bca29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829789922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2829789922
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.3836910995
Short name T1413
Test name
Test status
Simulation time 27982395 ps
CPU time 1.06 seconds
Started Mar 12 03:06:15 PM PDT 24
Finished Mar 12 03:06:16 PM PDT 24
Peak memory 217556 kb
Host smart-3b35d80e-685b-4924-a659-7af1bd1bf7ec
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836910995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.3836910995
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.585066845
Short name T1935
Test name
Test status
Simulation time 33766083 ps
CPU time 1.08 seconds
Started Mar 12 01:10:58 PM PDT 24
Finished Mar 12 01:10:59 PM PDT 24
Peak memory 216324 kb
Host smart-f9e2489b-5033-4fe9-8f19-eb0c31547fd2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585066845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.spi_device_mem_parity.585066845
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3025634564
Short name T1937
Test name
Test status
Simulation time 8186756218 ps
CPU time 8.62 seconds
Started Mar 12 01:10:52 PM PDT 24
Finished Mar 12 01:11:01 PM PDT 24
Peak memory 224672 kb
Host smart-62c5af7e-1307-4f67-98f5-09ab51a83787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025634564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3025634564
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.563423411
Short name T1377
Test name
Test status
Simulation time 726391190 ps
CPU time 8.74 seconds
Started Mar 12 03:06:12 PM PDT 24
Finished Mar 12 03:06:21 PM PDT 24
Peak memory 239848 kb
Host smart-4aaecbce-c3ac-4f27-9e5c-7a0b0ea0d7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563423411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
563423411
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.143990877
Short name T214
Test name
Test status
Simulation time 8018234029 ps
CPU time 24.74 seconds
Started Mar 12 03:06:06 PM PDT 24
Finished Mar 12 03:06:31 PM PDT 24
Peak memory 234476 kb
Host smart-6eab6068-26d5-4fb0-8cc6-1bbc4dc26626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143990877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.143990877
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2452754496
Short name T492
Test name
Test status
Simulation time 56014694 ps
CPU time 2.38 seconds
Started Mar 12 01:10:53 PM PDT 24
Finished Mar 12 01:10:56 PM PDT 24
Peak memory 232376 kb
Host smart-f4e9a18c-0052-42ca-95b4-12556d69a681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452754496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2452754496
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.1932136125
Short name T1712
Test name
Test status
Simulation time 22270015 ps
CPU time 0.72 seconds
Started Mar 12 01:10:51 PM PDT 24
Finished Mar 12 01:10:52 PM PDT 24
Peak memory 215956 kb
Host smart-934b3f9e-1e9b-4de5-aef0-76b21231a05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932136125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.1932136125
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.2487560081
Short name T1423
Test name
Test status
Simulation time 35590440 ps
CPU time 0.71 seconds
Started Mar 12 03:06:12 PM PDT 24
Finished Mar 12 03:06:13 PM PDT 24
Peak memory 215964 kb
Host smart-1e35045e-50f8-4c42-9528-c379e5bebda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487560081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.2487560081
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.202449174
Short name T1255
Test name
Test status
Simulation time 206058549 ps
CPU time 3.4 seconds
Started Mar 12 03:06:19 PM PDT 24
Finished Mar 12 03:06:23 PM PDT 24
Peak memory 218268 kb
Host smart-ebfd8141-7a39-4c8e-811a-816032b0a83e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=202449174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.202449174
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.4208842535
Short name T1570
Test name
Test status
Simulation time 553183001 ps
CPU time 4.99 seconds
Started Mar 12 01:10:55 PM PDT 24
Finished Mar 12 01:11:00 PM PDT 24
Peak memory 222380 kb
Host smart-59e2bb12-464f-490c-827a-5881b7bbcc3d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4208842535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.4208842535
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1785209226
Short name T1639
Test name
Test status
Simulation time 189928022 ps
CPU time 0.98 seconds
Started Mar 12 01:10:57 PM PDT 24
Finished Mar 12 01:10:58 PM PDT 24
Peak memory 206288 kb
Host smart-9d308dd9-0aaf-45e3-be14-46602bef33d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785209226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1785209226
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.948782355
Short name T192
Test name
Test status
Simulation time 79601873932 ps
CPU time 511.65 seconds
Started Mar 12 03:06:18 PM PDT 24
Finished Mar 12 03:14:50 PM PDT 24
Peak memory 250132 kb
Host smart-ce698220-c855-4a66-b246-080eeace7f09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948782355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.948782355
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2320623265
Short name T921
Test name
Test status
Simulation time 9070818930 ps
CPU time 31.19 seconds
Started Mar 12 01:11:00 PM PDT 24
Finished Mar 12 01:11:32 PM PDT 24
Peak memory 216128 kb
Host smart-3175813d-66ff-445f-8551-73a9d700d183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320623265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2320623265
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.373760760
Short name T666
Test name
Test status
Simulation time 26394654168 ps
CPU time 34.86 seconds
Started Mar 12 03:06:08 PM PDT 24
Finished Mar 12 03:06:43 PM PDT 24
Peak memory 216060 kb
Host smart-ee3c1a35-821c-4e1c-8ad7-1536a1972810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373760760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.373760760
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3163878392
Short name T1904
Test name
Test status
Simulation time 298995466 ps
CPU time 2.16 seconds
Started Mar 12 01:10:54 PM PDT 24
Finished Mar 12 01:10:57 PM PDT 24
Peak memory 207724 kb
Host smart-035f3656-e45e-4c60-a611-a73740d92832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163878392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3163878392
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.365655947
Short name T1461
Test name
Test status
Simulation time 3927684946 ps
CPU time 11.57 seconds
Started Mar 12 03:06:14 PM PDT 24
Finished Mar 12 03:06:26 PM PDT 24
Peak memory 216000 kb
Host smart-7ff771e1-1401-468f-8f62-871367278dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365655947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.365655947
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2318301493
Short name T338
Test name
Test status
Simulation time 413073123 ps
CPU time 5.56 seconds
Started Mar 12 01:10:57 PM PDT 24
Finished Mar 12 01:11:03 PM PDT 24
Peak memory 216104 kb
Host smart-2dfe34b9-2942-4c95-8ada-14d0742b6923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318301493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2318301493
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.924360716
Short name T1880
Test name
Test status
Simulation time 228803951 ps
CPU time 6.34 seconds
Started Mar 12 03:06:08 PM PDT 24
Finished Mar 12 03:06:15 PM PDT 24
Peak memory 216052 kb
Host smart-e99b7936-5aff-4b59-89cf-00c212182d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924360716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.924360716
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.4092344942
Short name T479
Test name
Test status
Simulation time 185235135 ps
CPU time 0.89 seconds
Started Mar 12 03:06:14 PM PDT 24
Finished Mar 12 03:06:15 PM PDT 24
Peak memory 205704 kb
Host smart-f1b2cafd-5060-4166-9d79-e568e8aafcb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092344942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.4092344942
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.534464364
Short name T1285
Test name
Test status
Simulation time 25628472 ps
CPU time 0.81 seconds
Started Mar 12 01:10:52 PM PDT 24
Finished Mar 12 01:10:53 PM PDT 24
Peak memory 205216 kb
Host smart-a0980387-4f0c-4e63-acbe-5e8cee932f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534464364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.534464364
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.3304578472
Short name T398
Test name
Test status
Simulation time 1105192285 ps
CPU time 5.96 seconds
Started Mar 12 03:06:18 PM PDT 24
Finished Mar 12 03:06:24 PM PDT 24
Peak memory 233112 kb
Host smart-128672d6-5de9-43d1-9e40-98c72544d173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304578472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3304578472
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_upload.540297802
Short name T526
Test name
Test status
Simulation time 20797280852 ps
CPU time 17.27 seconds
Started Mar 12 01:10:53 PM PDT 24
Finished Mar 12 01:11:10 PM PDT 24
Peak memory 218136 kb
Host smart-81c65eff-ed35-411d-ba06-6580ba1f99fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540297802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.540297802
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1162581996
Short name T1856
Test name
Test status
Simulation time 142698799 ps
CPU time 0.74 seconds
Started Mar 12 03:06:18 PM PDT 24
Finished Mar 12 03:06:19 PM PDT 24
Peak memory 204212 kb
Host smart-c67e9010-5621-4aa4-9c05-3ced5c66e569
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162581996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
162581996
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1817186905
Short name T1759
Test name
Test status
Simulation time 18368390 ps
CPU time 0.69 seconds
Started Mar 12 01:10:51 PM PDT 24
Finished Mar 12 01:10:52 PM PDT 24
Peak memory 204228 kb
Host smart-c2cad853-780f-46b7-8ff2-31458e065580
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817186905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
817186905
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2873715760
Short name T1016
Test name
Test status
Simulation time 409934954 ps
CPU time 4.61 seconds
Started Mar 12 01:10:57 PM PDT 24
Finished Mar 12 01:11:02 PM PDT 24
Peak memory 232540 kb
Host smart-fd48f5e6-7d70-43e3-b1ab-eb70c1118c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873715760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2873715760
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2941228824
Short name T1782
Test name
Test status
Simulation time 2219385175 ps
CPU time 7.29 seconds
Started Mar 12 03:06:20 PM PDT 24
Finished Mar 12 03:06:28 PM PDT 24
Peak memory 219936 kb
Host smart-1fbf6dbd-cf28-4e97-9915-496cf51d3161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941228824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2941228824
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2680342895
Short name T1102
Test name
Test status
Simulation time 62780834 ps
CPU time 0.78 seconds
Started Mar 12 01:10:52 PM PDT 24
Finished Mar 12 01:10:53 PM PDT 24
Peak memory 205952 kb
Host smart-c654dae8-37f1-4e43-9944-d243d24d713a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680342895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2680342895
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.712002052
Short name T868
Test name
Test status
Simulation time 35308693 ps
CPU time 0.78 seconds
Started Mar 12 03:06:22 PM PDT 24
Finished Mar 12 03:06:25 PM PDT 24
Peak memory 205972 kb
Host smart-53970fb9-3731-4e40-ac7e-bf6b24cef9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712002052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.712002052
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1324693012
Short name T795
Test name
Test status
Simulation time 67469077537 ps
CPU time 146.17 seconds
Started Mar 12 01:10:53 PM PDT 24
Finished Mar 12 01:13:19 PM PDT 24
Peak memory 256656 kb
Host smart-05a6d84d-0bbd-4839-b1f5-0f8dfc1ef67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324693012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1324693012
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2746851400
Short name T216
Test name
Test status
Simulation time 42543662530 ps
CPU time 103.02 seconds
Started Mar 12 03:06:17 PM PDT 24
Finished Mar 12 03:08:00 PM PDT 24
Peak memory 247196 kb
Host smart-0b4f489d-cea8-46cb-aa99-1c536848f495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746851400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2746851400
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1105619954
Short name T274
Test name
Test status
Simulation time 47161829202 ps
CPU time 171.89 seconds
Started Mar 12 01:10:51 PM PDT 24
Finished Mar 12 01:13:43 PM PDT 24
Peak memory 262984 kb
Host smart-e906801c-4966-4480-ac50-0246b9826e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105619954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1105619954
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.3796800393
Short name T303
Test name
Test status
Simulation time 219638384315 ps
CPU time 196.6 seconds
Started Mar 12 03:06:16 PM PDT 24
Finished Mar 12 03:09:33 PM PDT 24
Peak memory 271308 kb
Host smart-3039ee35-b5c8-48be-9fc0-2e8f9538118b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796800393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3796800393
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2254662610
Short name T283
Test name
Test status
Simulation time 9629797933 ps
CPU time 79.94 seconds
Started Mar 12 03:06:19 PM PDT 24
Finished Mar 12 03:07:39 PM PDT 24
Peak memory 253784 kb
Host smart-e05238b6-916b-4b8c-958d-a7608b4be57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254662610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2254662610
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.4287592635
Short name T1592
Test name
Test status
Simulation time 158413515636 ps
CPU time 257.63 seconds
Started Mar 12 01:10:53 PM PDT 24
Finished Mar 12 01:15:12 PM PDT 24
Peak memory 267348 kb
Host smart-aace0daa-1aff-4e9f-b4f6-dca773e1096a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287592635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.4287592635
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1405431137
Short name T1927
Test name
Test status
Simulation time 1839403924 ps
CPU time 7.32 seconds
Started Mar 12 03:06:17 PM PDT 24
Finished Mar 12 03:06:24 PM PDT 24
Peak memory 244224 kb
Host smart-31b979bd-5abc-4cdb-83bb-48fb483a5409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405431137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1405431137
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.995886154
Short name T142
Test name
Test status
Simulation time 1854503028 ps
CPU time 14.42 seconds
Started Mar 12 01:10:56 PM PDT 24
Finished Mar 12 01:11:10 PM PDT 24
Peak memory 234240 kb
Host smart-b9c4a3f8-ea26-4358-8a75-2558f7d981a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995886154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.995886154
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.771833392
Short name T588
Test name
Test status
Simulation time 15389857040 ps
CPU time 8.02 seconds
Started Mar 12 01:10:55 PM PDT 24
Finished Mar 12 01:11:03 PM PDT 24
Peak memory 224276 kb
Host smart-2d81cb06-b53e-4950-904e-ed1ad4cc4170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771833392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.771833392
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3466901763
Short name T948
Test name
Test status
Simulation time 4226564500 ps
CPU time 5.34 seconds
Started Mar 12 03:06:18 PM PDT 24
Finished Mar 12 03:06:24 PM PDT 24
Peak memory 233828 kb
Host smart-51945c22-ca5c-4640-a74c-0e3fbe4d878d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466901763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3466901763
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.657082434
Short name T1165
Test name
Test status
Simulation time 51593691883 ps
CPU time 35.69 seconds
Started Mar 12 01:11:00 PM PDT 24
Finished Mar 12 01:11:37 PM PDT 24
Peak memory 240628 kb
Host smart-25187c9e-6786-4c49-b15f-ccfe8b4aede1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657082434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.657082434
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.1136762993
Short name T688
Test name
Test status
Simulation time 34881795 ps
CPU time 1.08 seconds
Started Mar 12 03:06:17 PM PDT 24
Finished Mar 12 03:06:18 PM PDT 24
Peak memory 216384 kb
Host smart-92629f8a-ffab-4d6a-ad7b-edc6b736226e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136762993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.1136762993
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.655528864
Short name T1932
Test name
Test status
Simulation time 27880099 ps
CPU time 1.11 seconds
Started Mar 12 01:10:58 PM PDT 24
Finished Mar 12 01:10:59 PM PDT 24
Peak memory 217552 kb
Host smart-ea98d4ba-9b50-46c4-a699-a6bbf4e90185
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655528864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.spi_device_mem_parity.655528864
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3786384940
Short name T568
Test name
Test status
Simulation time 511573583 ps
CPU time 2.84 seconds
Started Mar 12 03:06:17 PM PDT 24
Finished Mar 12 03:06:20 PM PDT 24
Peak memory 233116 kb
Host smart-bae6901d-a5ca-4923-91f4-0a1b6d64901c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786384940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3786384940
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.4293609121
Short name T1154
Test name
Test status
Simulation time 2479856266 ps
CPU time 7.7 seconds
Started Mar 12 01:10:55 PM PDT 24
Finished Mar 12 01:11:02 PM PDT 24
Peak memory 216220 kb
Host smart-9005f791-8c93-4109-bab2-be6cfd79ca87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293609121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.4293609121
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2750950290
Short name T1567
Test name
Test status
Simulation time 848157248 ps
CPU time 3.82 seconds
Started Mar 12 03:06:18 PM PDT 24
Finished Mar 12 03:06:22 PM PDT 24
Peak memory 233044 kb
Host smart-10be5148-6de8-4efc-8dad-54bab7e92650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750950290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2750950290
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3883443102
Short name T1493
Test name
Test status
Simulation time 7649087168 ps
CPU time 5.74 seconds
Started Mar 12 01:10:54 PM PDT 24
Finished Mar 12 01:11:00 PM PDT 24
Peak memory 234300 kb
Host smart-a1b0d22b-59e5-4d75-9152-880c47dfbea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883443102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3883443102
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.2330861190
Short name T1511
Test name
Test status
Simulation time 23376941 ps
CPU time 0.73 seconds
Started Mar 12 01:10:51 PM PDT 24
Finished Mar 12 01:10:52 PM PDT 24
Peak memory 215980 kb
Host smart-75d921da-8604-4050-9a70-3de964dc2a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330861190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.2330861190
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.2915221922
Short name T707
Test name
Test status
Simulation time 28296349 ps
CPU time 0.72 seconds
Started Mar 12 03:06:18 PM PDT 24
Finished Mar 12 03:06:19 PM PDT 24
Peak memory 215944 kb
Host smart-1b9baf75-4a64-45fc-bd7c-509a58b66cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915221922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.2915221922
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1781323489
Short name T1547
Test name
Test status
Simulation time 5511855340 ps
CPU time 6.74 seconds
Started Mar 12 01:10:54 PM PDT 24
Finished Mar 12 01:11:01 PM PDT 24
Peak memory 222548 kb
Host smart-d0dc8815-dd16-4300-863a-e16e03c0a99a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1781323489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1781323489
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2048275239
Short name T1056
Test name
Test status
Simulation time 466289788 ps
CPU time 4.21 seconds
Started Mar 12 03:06:18 PM PDT 24
Finished Mar 12 03:06:23 PM PDT 24
Peak memory 218732 kb
Host smart-7ff9abfd-3f35-45f7-a137-f77acd63ceed
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2048275239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2048275239
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1211285881
Short name T917
Test name
Test status
Simulation time 26438680845 ps
CPU time 55.33 seconds
Started Mar 12 01:10:53 PM PDT 24
Finished Mar 12 01:11:48 PM PDT 24
Peak memory 236560 kb
Host smart-5753f56f-b1d4-4ca1-86b3-fe1fc55e217b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211285881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1211285881
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2026839039
Short name T1920
Test name
Test status
Simulation time 72428407033 ps
CPU time 418.1 seconds
Started Mar 12 03:06:19 PM PDT 24
Finished Mar 12 03:13:17 PM PDT 24
Peak memory 251600 kb
Host smart-77774ce5-d41c-4dd4-9ab3-1e5ef0fdd22e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026839039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2026839039
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1601274804
Short name T1934
Test name
Test status
Simulation time 879932854 ps
CPU time 4.98 seconds
Started Mar 12 01:10:54 PM PDT 24
Finished Mar 12 01:11:00 PM PDT 24
Peak memory 216012 kb
Host smart-606f314f-1bb1-4869-a169-e9663cf94e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601274804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1601274804
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.754035526
Short name T1324
Test name
Test status
Simulation time 2635376016 ps
CPU time 22.83 seconds
Started Mar 12 03:06:18 PM PDT 24
Finished Mar 12 03:06:41 PM PDT 24
Peak memory 216136 kb
Host smart-3140803d-76ba-4496-a391-a25af2a97100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754035526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.754035526
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1152449898
Short name T1633
Test name
Test status
Simulation time 1118804548 ps
CPU time 9.35 seconds
Started Mar 12 03:06:18 PM PDT 24
Finished Mar 12 03:06:27 PM PDT 24
Peak memory 216112 kb
Host smart-592769d8-ecd4-41ba-8940-150a026cfcd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152449898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1152449898
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.4217831519
Short name T1789
Test name
Test status
Simulation time 4414487861 ps
CPU time 4.86 seconds
Started Mar 12 01:10:53 PM PDT 24
Finished Mar 12 01:10:58 PM PDT 24
Peak memory 216072 kb
Host smart-d2478e8b-0aec-4925-9c20-e403ed5a4a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217831519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.4217831519
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2548084046
Short name T389
Test name
Test status
Simulation time 98720584 ps
CPU time 1.37 seconds
Started Mar 12 01:10:54 PM PDT 24
Finished Mar 12 01:10:56 PM PDT 24
Peak memory 216048 kb
Host smart-e2c135c2-b33f-4466-b033-0377cbbdfdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548084046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2548084046
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.45582018
Short name T457
Test name
Test status
Simulation time 77289857 ps
CPU time 3.01 seconds
Started Mar 12 03:06:18 PM PDT 24
Finished Mar 12 03:06:21 PM PDT 24
Peak memory 216272 kb
Host smart-9700bd42-b738-4ad8-a86d-99d918099c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45582018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.45582018
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3084600909
Short name T672
Test name
Test status
Simulation time 109731935 ps
CPU time 0.73 seconds
Started Mar 12 03:06:17 PM PDT 24
Finished Mar 12 03:06:18 PM PDT 24
Peak memory 205264 kb
Host smart-62ddc51b-cd7a-4383-afdc-65cc73483cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084600909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3084600909
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.74371615
Short name T1289
Test name
Test status
Simulation time 102195652 ps
CPU time 1.04 seconds
Started Mar 12 01:10:53 PM PDT 24
Finished Mar 12 01:10:54 PM PDT 24
Peak memory 206284 kb
Host smart-8d43197e-99b4-4710-8a80-78e7aec2aebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74371615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.74371615
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2895012708
Short name T1709
Test name
Test status
Simulation time 23730212910 ps
CPU time 22.51 seconds
Started Mar 12 01:10:54 PM PDT 24
Finished Mar 12 01:11:17 PM PDT 24
Peak memory 236396 kb
Host smart-0c54f9b0-ab78-4eff-90fd-d7c7bddbc68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895012708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2895012708
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_upload.3155285461
Short name T1326
Test name
Test status
Simulation time 5847023599 ps
CPU time 11.6 seconds
Started Mar 12 03:06:59 PM PDT 24
Finished Mar 12 03:07:10 PM PDT 24
Peak memory 229364 kb
Host smart-ba726687-2fd0-46cc-ab9d-66f149708ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155285461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3155285461
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2878219066
Short name T1610
Test name
Test status
Simulation time 17739967 ps
CPU time 0.69 seconds
Started Mar 12 03:06:30 PM PDT 24
Finished Mar 12 03:06:32 PM PDT 24
Peak memory 204932 kb
Host smart-a456aece-a9e8-43d2-be89-c741583d2f9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878219066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
878219066
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3343510173
Short name T487
Test name
Test status
Simulation time 15186522 ps
CPU time 0.71 seconds
Started Mar 12 01:11:04 PM PDT 24
Finished Mar 12 01:11:05 PM PDT 24
Peak memory 204212 kb
Host smart-c5f0646c-0e88-4ae5-a3ae-5fa4589efa04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343510173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
343510173
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2249897650
Short name T1264
Test name
Test status
Simulation time 5686285132 ps
CPU time 6.61 seconds
Started Mar 12 03:06:33 PM PDT 24
Finished Mar 12 03:06:40 PM PDT 24
Peak memory 233312 kb
Host smart-5a036043-a0af-45cb-b2e3-ee26d112bf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249897650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2249897650
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3777776330
Short name T1745
Test name
Test status
Simulation time 83888266 ps
CPU time 2.74 seconds
Started Mar 12 01:11:03 PM PDT 24
Finished Mar 12 01:11:06 PM PDT 24
Peak memory 233504 kb
Host smart-b5c58099-6f26-4ee0-919c-c4d8adaf631e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777776330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3777776330
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2075210762
Short name T753
Test name
Test status
Simulation time 35615985 ps
CPU time 0.78 seconds
Started Mar 12 03:06:30 PM PDT 24
Finished Mar 12 03:06:32 PM PDT 24
Peak memory 205744 kb
Host smart-2ca6d656-bcd2-4181-bcc0-321ce64a0f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075210762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2075210762
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.4260328010
Short name T1785
Test name
Test status
Simulation time 37526000 ps
CPU time 0.84 seconds
Started Mar 12 01:10:52 PM PDT 24
Finished Mar 12 01:10:53 PM PDT 24
Peak memory 206168 kb
Host smart-882888c0-19ea-45ea-90e7-ea66657e86b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260328010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.4260328010
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.1856985704
Short name T1174
Test name
Test status
Simulation time 3187755202 ps
CPU time 31.27 seconds
Started Mar 12 01:11:07 PM PDT 24
Finished Mar 12 01:11:38 PM PDT 24
Peak memory 244208 kb
Host smart-01285e2f-4abb-43c8-98d3-9458db591dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856985704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1856985704
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3160383771
Short name T872
Test name
Test status
Simulation time 7365726626 ps
CPU time 43.16 seconds
Started Mar 12 03:06:31 PM PDT 24
Finished Mar 12 03:07:15 PM PDT 24
Peak memory 252204 kb
Host smart-ec7a03b0-7efe-4c7e-8174-d637cc126f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160383771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3160383771
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3653870232
Short name T209
Test name
Test status
Simulation time 19476599052 ps
CPU time 234.38 seconds
Started Mar 12 01:11:04 PM PDT 24
Finished Mar 12 01:14:59 PM PDT 24
Peak memory 273464 kb
Host smart-f87a922f-0a7f-40cf-afd3-d1e7950ff99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653870232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3653870232
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3111922926
Short name T1391
Test name
Test status
Simulation time 29259567534 ps
CPU time 108.58 seconds
Started Mar 12 03:06:30 PM PDT 24
Finished Mar 12 03:08:20 PM PDT 24
Peak memory 253652 kb
Host smart-fd2533f3-af3e-4b9b-b3ec-e7c72b51bba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111922926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3111922926
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3672115505
Short name T200
Test name
Test status
Simulation time 103430612585 ps
CPU time 623.89 seconds
Started Mar 12 01:11:03 PM PDT 24
Finished Mar 12 01:21:28 PM PDT 24
Peak memory 257132 kb
Host smart-79f92269-323e-4b34-b2ba-d5024e7fde1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672115505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3672115505
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.4036527222
Short name T490
Test name
Test status
Simulation time 419954606 ps
CPU time 8.48 seconds
Started Mar 12 01:11:07 PM PDT 24
Finished Mar 12 01:11:16 PM PDT 24
Peak memory 232868 kb
Host smart-1f02da32-03bc-4886-a040-3891bb8340fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036527222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.4036527222
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.789728479
Short name T47
Test name
Test status
Simulation time 2631233904 ps
CPU time 9.27 seconds
Started Mar 12 03:06:28 PM PDT 24
Finished Mar 12 03:06:38 PM PDT 24
Peak memory 232396 kb
Host smart-d20c19f0-5ee3-4871-a87b-5722b7145ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789728479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.789728479
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2737139957
Short name T1555
Test name
Test status
Simulation time 596953736 ps
CPU time 2.38 seconds
Started Mar 12 01:11:05 PM PDT 24
Finished Mar 12 01:11:07 PM PDT 24
Peak memory 224068 kb
Host smart-2a6adce2-fdba-4ebb-9903-547e6d4d5410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737139957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2737139957
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_intercept.4108509226
Short name T775
Test name
Test status
Simulation time 1302054451 ps
CPU time 6.02 seconds
Started Mar 12 03:06:29 PM PDT 24
Finished Mar 12 03:06:35 PM PDT 24
Peak memory 233440 kb
Host smart-b4955627-250a-46fb-a258-241b387b0305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108509226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.4108509226
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2354176678
Short name T230
Test name
Test status
Simulation time 29954651657 ps
CPU time 27.62 seconds
Started Mar 12 01:11:12 PM PDT 24
Finished Mar 12 01:11:40 PM PDT 24
Peak memory 247512 kb
Host smart-c1f431f1-5824-429b-aea2-4f3afc93bd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354176678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2354176678
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3878614657
Short name T201
Test name
Test status
Simulation time 652151269 ps
CPU time 7.47 seconds
Started Mar 12 03:06:28 PM PDT 24
Finished Mar 12 03:06:35 PM PDT 24
Peak memory 224224 kb
Host smart-92ce5f69-df62-4e29-a1fa-37f3e2470bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878614657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3878614657
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.3464610642
Short name T1479
Test name
Test status
Simulation time 14299709 ps
CPU time 1.06 seconds
Started Mar 12 03:06:27 PM PDT 24
Finished Mar 12 03:06:28 PM PDT 24
Peak memory 216348 kb
Host smart-007559e6-2c97-4c6b-a4b6-82e52fd9f78a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464610642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.3464610642
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.3940569601
Short name T985
Test name
Test status
Simulation time 114140318 ps
CPU time 1.16 seconds
Started Mar 12 01:10:50 PM PDT 24
Finished Mar 12 01:10:51 PM PDT 24
Peak memory 216344 kb
Host smart-f6e803f0-7abf-4422-b789-15edd861158b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940569601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.3940569601
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1703927156
Short name T1422
Test name
Test status
Simulation time 50422673556 ps
CPU time 34.28 seconds
Started Mar 12 01:11:19 PM PDT 24
Finished Mar 12 01:11:53 PM PDT 24
Peak memory 233492 kb
Host smart-650d151e-e5ad-474a-a01e-429c44b2f105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703927156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1703927156
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.418556930
Short name T1121
Test name
Test status
Simulation time 386516710 ps
CPU time 4.97 seconds
Started Mar 12 03:06:29 PM PDT 24
Finished Mar 12 03:06:34 PM PDT 24
Peak memory 217744 kb
Host smart-61720abe-b71c-49f4-8af0-9237dbbe6a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418556930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
418556930
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.115101451
Short name T1017
Test name
Test status
Simulation time 15761728399 ps
CPU time 15.45 seconds
Started Mar 12 03:06:31 PM PDT 24
Finished Mar 12 03:06:47 PM PDT 24
Peak memory 233392 kb
Host smart-54f06d46-a137-4038-8d6e-2dac50d6ef35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115101451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.115101451
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.4022772900
Short name T1752
Test name
Test status
Simulation time 1428332250 ps
CPU time 12.02 seconds
Started Mar 12 01:11:00 PM PDT 24
Finished Mar 12 01:11:13 PM PDT 24
Peak memory 238340 kb
Host smart-9944f38d-7d11-4644-a8b3-fd8834150ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022772900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.4022772900
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.2702089139
Short name T949
Test name
Test status
Simulation time 38830874 ps
CPU time 0.78 seconds
Started Mar 12 01:10:52 PM PDT 24
Finished Mar 12 01:10:53 PM PDT 24
Peak memory 215956 kb
Host smart-f0894291-235f-4e1a-b690-5dff9b172fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702089139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.2702089139
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.3910221993
Short name T2
Test name
Test status
Simulation time 38308605 ps
CPU time 0.72 seconds
Started Mar 12 03:06:28 PM PDT 24
Finished Mar 12 03:06:29 PM PDT 24
Peak memory 215968 kb
Host smart-3824588e-794e-4133-929a-cdf9871c10c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910221993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.3910221993
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2517382172
Short name T147
Test name
Test status
Simulation time 1755147981 ps
CPU time 6.24 seconds
Started Mar 12 01:11:04 PM PDT 24
Finished Mar 12 01:11:11 PM PDT 24
Peak memory 222368 kb
Host smart-d322a9c7-f384-4047-9937-0c103cba165e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2517382172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2517382172
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3138875167
Short name T1410
Test name
Test status
Simulation time 25749298070 ps
CPU time 7.83 seconds
Started Mar 12 03:06:28 PM PDT 24
Finished Mar 12 03:06:37 PM PDT 24
Peak memory 216248 kb
Host smart-e5e86737-33fb-45d7-846b-ffd744533323
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3138875167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3138875167
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1225995678
Short name T275
Test name
Test status
Simulation time 366848829732 ps
CPU time 624.91 seconds
Started Mar 12 03:06:29 PM PDT 24
Finished Mar 12 03:16:55 PM PDT 24
Peak memory 272800 kb
Host smart-a25d6539-ce55-4b3d-ad5d-35edd8e9a0b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225995678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1225995678
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.4094731552
Short name T52
Test name
Test status
Simulation time 250246368145 ps
CPU time 592.45 seconds
Started Mar 12 01:11:05 PM PDT 24
Finished Mar 12 01:20:57 PM PDT 24
Peak memory 272908 kb
Host smart-748bfd54-51dc-4cb2-8065-9e9f8f62b7c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094731552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.4094731552
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1758949660
Short name T614
Test name
Test status
Simulation time 16043042617 ps
CPU time 39 seconds
Started Mar 12 03:06:27 PM PDT 24
Finished Mar 12 03:07:06 PM PDT 24
Peak memory 216044 kb
Host smart-9f3b1121-3ad5-4224-94ee-cbb7abc389de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758949660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1758949660
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.758848376
Short name T710
Test name
Test status
Simulation time 4463453389 ps
CPU time 26.95 seconds
Started Mar 12 01:10:55 PM PDT 24
Finished Mar 12 01:11:22 PM PDT 24
Peak memory 216168 kb
Host smart-c33ef463-83c7-40e3-abbb-21981d9eac43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758848376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.758848376
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1790963299
Short name T1411
Test name
Test status
Simulation time 14237513062 ps
CPU time 12.41 seconds
Started Mar 12 03:06:37 PM PDT 24
Finished Mar 12 03:06:50 PM PDT 24
Peak memory 216104 kb
Host smart-238000fc-87db-4112-a171-90d10b1605c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790963299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1790963299
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3528480443
Short name T1143
Test name
Test status
Simulation time 17879288230 ps
CPU time 29.3 seconds
Started Mar 12 01:10:55 PM PDT 24
Finished Mar 12 01:11:24 PM PDT 24
Peak memory 216104 kb
Host smart-4c352891-3561-4605-aa5f-c55c617f2112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528480443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3528480443
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1378632768
Short name T458
Test name
Test status
Simulation time 61480442 ps
CPU time 0.71 seconds
Started Mar 12 01:10:53 PM PDT 24
Finished Mar 12 01:10:54 PM PDT 24
Peak memory 205248 kb
Host smart-e30a8bd6-5117-4f3f-b909-0d78e537674b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378632768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1378632768
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.375265044
Short name T448
Test name
Test status
Simulation time 20138408 ps
CPU time 0.85 seconds
Started Mar 12 03:06:30 PM PDT 24
Finished Mar 12 03:06:32 PM PDT 24
Peak memory 206040 kb
Host smart-cf1d6b02-e5d8-4c29-9cc1-3c09841a52b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375265044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.375265044
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1145061225
Short name T1307
Test name
Test status
Simulation time 762569305 ps
CPU time 1.1 seconds
Started Mar 12 01:10:56 PM PDT 24
Finished Mar 12 01:10:57 PM PDT 24
Peak memory 206248 kb
Host smart-e3fecf4a-6b12-4c20-819a-35eced95822c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145061225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1145061225
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.321361693
Short name T370
Test name
Test status
Simulation time 130333651 ps
CPU time 0.81 seconds
Started Mar 12 03:06:28 PM PDT 24
Finished Mar 12 03:06:29 PM PDT 24
Peak memory 205228 kb
Host smart-0468383c-5caa-4236-b99e-381d6de07018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321361693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.321361693
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.1458587285
Short name T1501
Test name
Test status
Simulation time 873056925 ps
CPU time 4.56 seconds
Started Mar 12 03:06:30 PM PDT 24
Finished Mar 12 03:06:36 PM PDT 24
Peak memory 218704 kb
Host smart-036eeb82-6d89-47d9-af5a-97f645b2ef6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458587285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1458587285
Directory /workspace/9.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_upload.2594970724
Short name T1558
Test name
Test status
Simulation time 8394344859 ps
CPU time 29.01 seconds
Started Mar 12 01:11:07 PM PDT 24
Finished Mar 12 01:11:37 PM PDT 24
Peak memory 232364 kb
Host smart-d26fe1ac-c376-474d-a825-0a8e81c21343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594970724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2594970724
Directory /workspace/9.spi_device_upload/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%