Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5504787	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6115054

1

T20

9255

T21

881

T22

1071

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7509132	1			T20	3948		T21	5		T22	354
values[0x0]	2056913	1			T20	4192		T21	436		T22	443
values[0x1]	2053796	1			T20	4248		T21	445		T22	462

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4015288	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

7604553

1

T20

10135

T21

882

T22

1112

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	50936	1			T20	436		T21	12		T22	5
valid_sources[0x01]	44798	1			T20	104		T22	3		T23	10
valid_sources[0x02]	44028	1			T20	1		T21	6		T22	4
valid_sources[0x03]	43231	1			T20	2		T21	4		T22	6
valid_sources[0x04]	40902	1			T20	1		T21	3		T22	7
valid_sources[0x05]	44666	1			T20	311		T21	4		T22	6
valid_sources[0x06]	44164	1			T20	2		T21	6		T22	4
valid_sources[0x07]	43377	1			T20	13		T21	2		T22	5
valid_sources[0x08]	42438	1			T21	6		T22	3		T23	42
valid_sources[0x09]	47842	1			T20	3		T21	4		T22	2
valid_sources[0x0a]	43652	1			T20	37		T21	14		T22	7
valid_sources[0x0b]	43980	1			T21	1		T22	7		T23	10
valid_sources[0x0c]	46853	1			T20	1		T21	3		T22	5
valid_sources[0x0d]	41450	1			T20	68		T21	5		T22	1
valid_sources[0x0e]	47641	1			T20	69		T21	3		T22	3
valid_sources[0x0f]	45501	1			T20	127		T22	4		T24	3
valid_sources[0x10]	45366	1			T20	1		T21	6		T22	4
valid_sources[0x11]	44873	1			T21	1		T22	3		T24	4
valid_sources[0x12]	43039	1			T20	33		T22	1		T24	5
valid_sources[0x13]	46631	1			T20	510		T21	6		T22	4
valid_sources[0x14]	45175	1			T21	4		T22	9		T24	6
valid_sources[0x15]	43500	1			T20	2		T21	4		T22	5
valid_sources[0x16]	43850	1			T21	4		T22	3		T23	10
valid_sources[0x17]	48698	1			T20	33		T21	3		T22	11
valid_sources[0x18]	46804	1			T20	3		T21	3		T22	2
valid_sources[0x19]	46945	1			T20	226		T21	1		T22	4
valid_sources[0x1a]	47270	1			T20	2		T22	6		T24	6
valid_sources[0x1b]	42697	1			T20	92		T21	2		T22	2
valid_sources[0x1c]	41560	1			T20	13		T22	4		T23	4
valid_sources[0x1d]	43751	1			T20	83		T21	6		T22	6
valid_sources[0x1e]	50682	1			T20	1		T22	5		T23	12
valid_sources[0x1f]	43641	1			T20	36		T21	2		T22	1
valid_sources[0x20]	43062	1			T21	4		T22	1		T23	6
valid_sources[0x21]	43687	1			T20	12		T21	2		T22	2
valid_sources[0x22]	43708	1			T20	2		T21	7		T22	3
valid_sources[0x23]	43695	1			T20	1		T21	2		T22	5
valid_sources[0x24]	44675	1			T20	2		T22	5		T24	6
valid_sources[0x25]	43513	1			T20	2		T21	2		T22	6
valid_sources[0x26]	47323	1			T20	1		T21	8		T22	4
valid_sources[0x27]	43815	1			T21	7		T23	20		T24	3
valid_sources[0x28]	48441	1			T21	5		T22	2		T24	4
valid_sources[0x29]	44585	1			T20	5		T21	3		T22	2
valid_sources[0x2a]	47913	1			T20	453		T21	9		T22	2
valid_sources[0x2b]	43450	1			T20	2		T21	3		T22	5
valid_sources[0x2c]	44196	1			T21	5		T22	6		T24	2
valid_sources[0x2d]	44686	1			T20	148		T21	2		T22	7
valid_sources[0x2e]	45369	1			T20	142		T21	1		T22	8
valid_sources[0x2f]	51148	1			T21	4		T22	4		T24	3
valid_sources[0x30]	43519	1			T20	58		T21	2		T22	2
valid_sources[0x31]	44907	1			T20	33		T21	3		T22	10
valid_sources[0x32]	45740	1			T20	73		T22	5		T23	15
valid_sources[0x33]	48956	1			T20	11		T22	8		T23	10
valid_sources[0x34]	44965	1			T20	62		T21	6		T22	4
valid_sources[0x35]	45400	1			T20	1		T21	5		T22	5
valid_sources[0x36]	43810	1			T21	3		T22	10		T23	44
valid_sources[0x37]	42342	1			T21	7		T22	9		T23	56
valid_sources[0x38]	44561	1			T20	3		T21	2		T22	4
valid_sources[0x39]	44812	1			T21	1		T22	2		T24	7
valid_sources[0x3a]	45661	1			T20	22		T22	9		T24	7
valid_sources[0x3b]	48485	1			T21	4		T22	7		T23	4
valid_sources[0x3c]	46809	1			T21	1		T22	3		T24	4
valid_sources[0x3d]	46439	1			T22	4		T24	1		T27	17
valid_sources[0x3e]	46197	1			T20	1		T21	4		T22	3
valid_sources[0x3f]	46999	1			T21	2		T22	3		T23	12
valid_sources[0x40]	41247	1			T20	1		T21	8		T22	3
valid_sources[0x41]	43888	1			T21	10		T22	3		T24	1
valid_sources[0x42]	42762	1			T20	173		T22	5		T24	3
valid_sources[0x43]	42832	1			T21	3		T22	5		T24	2
valid_sources[0x44]	48474	1			T20	3		T21	5		T22	7
valid_sources[0x45]	54257	1			T22	3		T24	1		T26	1
valid_sources[0x46]	42372	1			T20	55		T21	2		T22	4
valid_sources[0x47]	43102	1			T20	1		T21	9		T22	2
valid_sources[0x48]	47090	1			T21	1		T22	3		T23	67
valid_sources[0x49]	41009	1			T20	1		T21	5		T22	6
valid_sources[0x4a]	55025	1			T20	100		T21	4		T22	5
valid_sources[0x4b]	42109	1			T20	28		T21	2		T22	7
valid_sources[0x4c]	44938	1			T22	5		T24	3		T28	2
valid_sources[0x4d]	47426	1			T20	1		T21	7		T22	4
valid_sources[0x4e]	42607	1			T20	1		T21	3		T22	3
valid_sources[0x4f]	44325	1			T20	72		T22	6		T23	3
valid_sources[0x50]	50033	1			T20	77		T21	11		T22	6
valid_sources[0x51]	42168	1			T20	1		T21	4		T22	10
valid_sources[0x52]	43256	1			T22	5		T24	7		T26	1
valid_sources[0x53]	42986	1			T21	4		T22	2		T24	3
valid_sources[0x54]	45633	1			T20	3		T22	7		T24	4
valid_sources[0x55]	44007	1			T20	4		T21	8		T22	4
valid_sources[0x56]	45665	1			T20	15		T21	2		T22	5
valid_sources[0x57]	43268	1			T20	133		T22	7		T24	5
valid_sources[0x58]	45233	1			T22	6		T23	10		T24	7
valid_sources[0x59]	49693	1			T20	233		T21	3		T22	2
valid_sources[0x5a]	55741	1			T20	71		T21	13		T22	4
valid_sources[0x5b]	46167	1			T20	34		T21	4		T22	3
valid_sources[0x5c]	44411	1			T20	10		T21	1		T22	2
valid_sources[0x5d]	44411	1			T21	5		T22	3		T24	3
valid_sources[0x5e]	49593	1			T21	2		T22	3		T24	8
valid_sources[0x5f]	44796	1			T20	38		T21	1		T22	6
valid_sources[0x60]	45922	1			T20	28		T22	2		T24	4
valid_sources[0x61]	44518	1			T20	1		T21	7		T22	6
valid_sources[0x62]	46049	1			T20	36		T21	6		T22	4
valid_sources[0x63]	46497	1			T20	108		T21	3		T22	6
valid_sources[0x64]	43846	1			T20	2		T21	1		T22	10
valid_sources[0x65]	44455	1			T20	92		T21	1		T22	3
valid_sources[0x66]	49845	1			T20	1		T22	8		T23	19
valid_sources[0x67]	43855	1			T21	2		T22	2		T24	2
valid_sources[0x68]	42907	1			T20	40		T21	2		T22	6
valid_sources[0x69]	43042	1			T21	10		T22	10		T24	4
valid_sources[0x6a]	45360	1			T20	8		T22	5		T24	1
valid_sources[0x6b]	44144	1			T20	19		T21	1		T22	5
valid_sources[0x6c]	42764	1			T21	13		T22	6		T24	5
valid_sources[0x6d]	44421	1			T20	365		T21	7		T22	4
valid_sources[0x6e]	45326	1			T21	10		T22	1		T24	7
valid_sources[0x6f]	44729	1			T20	68		T22	4		T24	1
valid_sources[0x70]	50419	1			T20	28		T21	6		T24	3
valid_sources[0x71]	42454	1			T20	267		T22	5		T24	5
valid_sources[0x72]	44811	1			T20	41		T21	7		T22	7
valid_sources[0x73]	43647	1			T20	18		T21	1		T22	6
valid_sources[0x74]	43013	1			T20	9		T21	5		T22	10
valid_sources[0x75]	50663	1			T20	2		T21	7		T22	6
valid_sources[0x76]	49319	1			T20	50		T21	1		T22	9
valid_sources[0x77]	43289	1			T20	2		T22	9		T24	1
valid_sources[0x78]	46973	1			T20	10		T21	6		T22	8
valid_sources[0x79]	44451	1			T20	34		T21	5		T22	5
valid_sources[0x7a]	45940	1			T20	3		T21	3		T22	5
valid_sources[0x7b]	46616	1			T20	156		T21	4		T22	7
valid_sources[0x7c]	45733	1			T21	3		T22	1		T24	4
valid_sources[0x7d]	43934	1			T20	112		T21	8		T22	5
valid_sources[0x7e]	44539	1			T20	29		T21	4		T22	6
valid_sources[0x7f]	44217	1			T20	1		T21	3		T22	9
valid_sources[0x80]	53042	1			T20	152		T21	7		T22	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2421740

1

T20

1440

T21

1

T22

170

values[0x0]

all_enables

biggest_size

1861906

1

T20

3917

T21

436

T22

441

values[0x1]

all_enables

biggest_size

1831408

1

T20

3898

T21

444

T22

460