Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
37.50 37.50 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block] 37.50 1 100 1 64 64



Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
37.50 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 3 5 62.50
Crosses 16 12 4 25.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 3 1 25.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 12 4 25.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
partial 5502965 1 T20 3133 T21 5 T22 188
full_word 6112856 1 T20 9255 T21 881 T22 1071


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 3 1 25.00


Automatically Generated Bins for cp_tl_intg_err_type

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[TlIntgErrCmd] 0 1 1
auto[TlIntgErrData] 0 1 1
auto[TlIntgErrBoth] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 11615821 1 T20 12388 T21 886 T22 1259


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7507112 1 T20 3948 T21 5 T22 354
auto[1] 4108709 1 T20 8440 T21 881 T22 905


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 12 4 25.00 12


Automatically Generated Cross Bins for cr_all

Element holes
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTNUMBERSTATUS
[auto[TlIntgErrCmd] , auto[TlIntgErrData] , auto[TlIntgErrBoth]] * * -- -- 12


Covered bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 5085570 1 T20 2508 T21 4 T22 184
auto[TlIntgErrNone] partial auto[1] 417395 1 T20 625 T21 1 T22 4
auto[TlIntgErrNone] full_word auto[0] 2421542 1 T20 1440 T21 1 T22 170
auto[TlIntgErrNone] full_word auto[1] 3691314 1 T20 7815 T21 880 T22 901

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%