Unified Coverage Report :: Module :: prim_secded_inv_64_57_dec

Module : prim_secded_inv_64_57_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.14			99.14

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_chk.u_chk	99.14			99.14

---

Module Instance : tb.dut.u_reg.u_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.14			99.14

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.14			99.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : prim_secded_inv_64_57_dec

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	232	230	99.14
Total Bits 0->1	116	115	99.14
Total Bits 1->0	116	115	99.14

Ports	4	3	75.00
Port Bits	232	230	99.14
Port Bits 0->1	116	115	99.14
Port Bits 1->0	116	115	99.14

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[4:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_i[5]	No	No		No		INPUT
data_i[42:6]	Yes	Yes	*T20,*T21,T22	Yes	T20,T21,T22	INPUT
data_i[56:43]	Unreachable	Unreachable		Unreachable		INPUT
data_i[63:57]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
data_o[56:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
syndrome_o[6:0]	Yes	Yes	T22,T26,T32	Yes	T22,T26,T32	OUTPUT
err_o[1:0]	Yes	Yes	T22,T26,T32	Yes	T22,T26,T32	OUTPUT

*Tests covering at least one bit in the range