Unified Coverage Report :: Module :: prim_intr_hw

Module : prim_intr_hw

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_intr_tpm_rdfifo_drop	97.92	100.00	91.67			100.00	100.00
tb.dut.u_intr_cmdfifo_not_empty	100.00	100.00	100.00			100.00	100.00
tb.dut.u_intr_payload_not_empty	100.00	100.00	100.00			100.00	100.00
tb.dut.u_intr_payload_overflow	100.00	100.00	100.00			100.00	100.00
tb.dut.u_intr_readbuf_watermark	100.00	100.00	100.00			100.00	100.00
tb.dut.u_intr_readbuf_flip	100.00	100.00	100.00			100.00	100.00
tb.dut.u_intr_tpm_cmdaddr_notempty	100.00	100.00	100.00			100.00	100.00
tb.dut.u_intr_tpm_rdfifo_cmd_end	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_intr_tpm_rdfifo_drop

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.60	94.25	84.31	96.51		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_intr_cmdfifo_not_empty

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.60	94.25	84.31	96.51		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_intr_payload_not_empty

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.60	94.25	84.31	96.51		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_intr_payload_overflow

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.60	94.25	84.31	96.51		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_intr_readbuf_watermark

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.60	94.25	84.31	96.51		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_intr_readbuf_flip

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.60	94.25	84.31	96.51		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_intr_tpm_cmdaddr_notempty

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.60	94.25	84.31	96.51		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_intr_tpm_rdfifo_cmd_end

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.60	94.25	84.31	96.51		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_intr_cmdfifo_not_empty

SCORE	LINE
100.00	100.00

tb.dut.u_intr_payload_not_empty

SCORE	LINE
100.00	100.00

tb.dut.u_intr_payload_overflow

SCORE	LINE
100.00	100.00

tb.dut.u_intr_readbuf_watermark

SCORE	LINE
100.00	100.00

tb.dut.u_intr_readbuf_flip

SCORE	LINE
100.00	100.00

tb.dut.u_intr_tpm_rdfifo_cmd_end

SCORE	LINE
97.92	100.00

tb.dut.u_intr_tpm_rdfifo_drop

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
ALWAYS	95	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	1	1
64	1	1
67	1	1
69	1	1
95	1	1
96	1	1
98	1	1

---

Line Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_intr_tpm_cmdaddr_notempty

	Line No.	Total	Covered	Percent
TOTAL		10	10	100.00
ALWAYS	75	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
ALWAYS	95	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
75	2	2
76	2	2
			MISSING_ELSE
81	1	1
83	1	1
88	1	1
95	1	1
96	1	1
98	1	1

---

Cond Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_intr_cmdfifo_not_empty

SCORE	COND
100.00	100.00

tb.dut.u_intr_payload_not_empty

SCORE	COND
100.00	100.00

tb.dut.u_intr_payload_overflow

SCORE	COND
100.00	100.00

tb.dut.u_intr_readbuf_watermark

SCORE	COND
100.00	100.00

tb.dut.u_intr_readbuf_flip

SCORE	COND
100.00	100.00

tb.dut.u_intr_tpm_rdfifo_cmd_end

SCORE	COND
97.92	91.67

tb.dut.u_intr_tpm_rdfifo_drop

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T20,T30,T31
1	0	Covered	T28,T1,T2

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T28,T1,T2
1	1	Covered	T28,T1,T2

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T20,T28,T30
1	0	Covered	T20,T28,T30

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T2
1	0	Covered	T20,T28,T30
1	1	Covered	T28,T1,T2

---

Cond Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_intr_tpm_cmdaddr_notempty

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T28,T1,T2
1	0	Covered	T20,T30,T33

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T28,T1,T2
1	0	Covered	T20,T30,T33

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T56
1	0	Covered	T20,T28,T30
1	1	Covered	T28,T1,T56

---

Branch Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Branch Coverage for Module self-instances :

SCORE	BRANCH
100.00	100.00

tb.dut.u_intr_cmdfifo_not_empty

SCORE	BRANCH
100.00	100.00

tb.dut.u_intr_payload_not_empty

SCORE	BRANCH
100.00	100.00

tb.dut.u_intr_payload_overflow

SCORE	BRANCH
100.00	100.00

tb.dut.u_intr_readbuf_watermark

SCORE	BRANCH
100.00	100.00

tb.dut.u_intr_readbuf_flip

SCORE	BRANCH
100.00	100.00

tb.dut.u_intr_tpm_rdfifo_cmd_end

SCORE	BRANCH
97.92	100.00

tb.dut.u_intr_tpm_rdfifo_drop

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	95	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	95	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T20,T21,T22

---

Branch Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Branch Coverage for Module self-instances :

SCORE	BRANCH
100.00	100.00

tb.dut.u_intr_tpm_cmdaddr_notempty

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	75	3	3	100.00
IF	95	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	if ((!rst_ni))
-2-:	76	if (reg2hw_intr_test_qe_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T20,T21,T22
0	1	Covered	T28,T1,T2
0	0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	95	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T20,T21,T22

---

Assert Coverage for Module : prim_intr_hw

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	7512	7512	0	0

IntrTKind_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7512	7512	0	0
T20	8	8	0	0
T21	8	8	0	0
T22	8	8	0	0
T23	8	8	0	0
T24	8	8	0	0
T25	8	8	0	0
T26	8	8	0	0
T27	8	8	0	0
T28	8	8	0	0
T29	8	8	0	0

Line Coverage for Instance : tb.dut.u_intr_tpm_rdfifo_drop

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
ALWAYS	95	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	1	1
64	1	1
67	1	1
69	1	1
95	1	1
96	1	1
98	1	1

---

Cond Coverage for Instance : tb.dut.u_intr_tpm_rdfifo_drop

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Not Covered
1	0	Covered	T28,T1,T2

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T28,T1,T2
1	1	Covered	T28,T1,T2

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T28,T1,T2
1	0	Covered	T28,T1,T2

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T28,T2,T56
1	0	Covered	T28,T1,T2
1	1	Covered	T28,T1,T2

---

Branch Coverage for Instance : tb.dut.u_intr_tpm_rdfifo_drop

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	95	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	95	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T20,T21,T22

---

Assert Coverage for Instance : tb.dut.u_intr_tpm_rdfifo_drop

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	939	939	0	0

IntrTKind_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939	939	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0

Line Coverage for Instance : tb.dut.u_intr_cmdfifo_not_empty

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
ALWAYS	95	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	1	1
64	1	1
67	1	1
69	1	1
95	1	1
96	1	1
98	1	1

---

Cond Coverage for Instance : tb.dut.u_intr_cmdfifo_not_empty

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T20,T30,T34
1	0	Covered	T28,T1,T2

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T28,T1,T2
1	1	Covered	T28,T1,T2

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T20,T28,T30
1	0	Covered	T20,T28,T30

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T2
1	0	Covered	T20,T28,T30
1	1	Covered	T28,T1,T2

---

Branch Coverage for Instance : tb.dut.u_intr_cmdfifo_not_empty

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	95	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	95	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T20,T21,T22

---

Assert Coverage for Instance : tb.dut.u_intr_cmdfifo_not_empty

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	939	939	0	0

IntrTKind_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939	939	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0

Line Coverage for Instance : tb.dut.u_intr_payload_not_empty

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
ALWAYS	95	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	1	1
64	1	1
67	1	1
69	1	1
95	1	1
96	1	1
98	1	1

---

Cond Coverage for Instance : tb.dut.u_intr_payload_not_empty

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T20,T30,T34
1	0	Covered	T28,T1,T2

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T28,T1,T2
1	1	Covered	T28,T1,T2

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T20,T28,T30
1	0	Covered	T20,T28,T30

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T2
1	0	Covered	T20,T28,T30
1	1	Covered	T28,T1,T2

---

Branch Coverage for Instance : tb.dut.u_intr_payload_not_empty

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	95	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	95	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T20,T21,T22

---

Assert Coverage for Instance : tb.dut.u_intr_payload_not_empty

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	939	939	0	0

IntrTKind_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939	939	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0

Line Coverage for Instance : tb.dut.u_intr_payload_overflow

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
ALWAYS	95	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	1	1
64	1	1
67	1	1
69	1	1
95	1	1
96	1	1
98	1	1

---

Cond Coverage for Instance : tb.dut.u_intr_payload_overflow

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T20,T30,T34
1	0	Covered	T28,T1,T2

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T28,T1,T2
1	1	Covered	T28,T1,T2

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T20,T28,T30
1	0	Covered	T20,T28,T30

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T56
1	0	Covered	T20,T28,T30
1	1	Covered	T28,T1,T2

---

Branch Coverage for Instance : tb.dut.u_intr_payload_overflow

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	95	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	95	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T20,T21,T22

---

Assert Coverage for Instance : tb.dut.u_intr_payload_overflow

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	939	939	0	0

IntrTKind_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939	939	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0

Line Coverage for Instance : tb.dut.u_intr_readbuf_watermark

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
ALWAYS	95	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	1	1
64	1	1
67	1	1
69	1	1
95	1	1
96	1	1
98	1	1

---

Cond Coverage for Instance : tb.dut.u_intr_readbuf_watermark

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T31,T52,T53
1	0	Covered	T28,T1,T2

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T28,T1,T2
1	1	Covered	T28,T1,T2

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T28,T31,T52
1	0	Covered	T28,T31,T52

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T56
1	0	Covered	T28,T31,T52
1	1	Covered	T28,T1,T56

---

Branch Coverage for Instance : tb.dut.u_intr_readbuf_watermark

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	95	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	95	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T20,T21,T22

---

Assert Coverage for Instance : tb.dut.u_intr_readbuf_watermark

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	939	939	0	0

IntrTKind_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939	939	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0

Line Coverage for Instance : tb.dut.u_intr_readbuf_flip

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
ALWAYS	95	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	1	1
64	1	1
67	1	1
69	1	1
95	1	1
96	1	1
98	1	1

---

Cond Coverage for Instance : tb.dut.u_intr_readbuf_flip

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T31,T52,T53
1	0	Covered	T28,T1,T2

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T28,T1,T2
1	1	Covered	T28,T1,T2

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T28,T31,T52
1	0	Covered	T28,T31,T52

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T28,T56,T65
1	0	Covered	T28,T31,T52
1	1	Covered	T28,T1,T56

---

Branch Coverage for Instance : tb.dut.u_intr_readbuf_flip

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	95	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	95	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T20,T21,T22

---

Assert Coverage for Instance : tb.dut.u_intr_readbuf_flip

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	939	939	0	0

IntrTKind_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939	939	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0

Line Coverage for Instance : tb.dut.u_intr_tpm_cmdaddr_notempty

	Line No.	Total	Covered	Percent
TOTAL		10	10	100.00
ALWAYS	75	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
ALWAYS	95	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
75	2	2
76	2	2
			MISSING_ELSE
81	1	1
83	1	1
88	1	1
95	1	1
96	1	1
98	1	1

---

Cond Coverage for Instance : tb.dut.u_intr_tpm_cmdaddr_notempty

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T28,T1,T2
1	0	Covered	T20,T30,T33

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T28,T1,T2
1	0	Covered	T20,T30,T33

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T56
1	0	Covered	T20,T28,T30
1	1	Covered	T28,T1,T56

---

Branch Coverage for Instance : tb.dut.u_intr_tpm_cmdaddr_notempty

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	75	3	3	100.00
IF	95	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	75	if ((!rst_ni))
-2-:	76	if (reg2hw_intr_test_qe_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T20,T21,T22
0	1	Covered	T28,T1,T2
0	0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	95	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T20,T21,T22

---

Assert Coverage for Instance : tb.dut.u_intr_tpm_cmdaddr_notempty

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	939	939	0	0

IntrTKind_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939	939	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0

Line Coverage for Instance : tb.dut.u_intr_tpm_rdfifo_cmd_end

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
ALWAYS	95	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	1	1
64	1	1
67	1	1
69	1	1
95	1	1
96	1	1
98	1	1

---

Cond Coverage for Instance : tb.dut.u_intr_tpm_rdfifo_cmd_end

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T20,T30,T33
1	0	Covered	T28,T1,T2

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T28,T1,T2
1	1	Covered	T28,T1,T2

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T20,T28,T30
1	0	Covered	T20,T28,T30

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T2
1	0	Covered	T20,T28,T30
1	1	Covered	T28,T1,T2

---

Branch Coverage for Instance : tb.dut.u_intr_tpm_rdfifo_cmd_end

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	95	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	95	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T20,T21,T22

---

Assert Coverage for Instance : tb.dut.u_intr_tpm_rdfifo_cmd_end

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	939	939	0	0

IntrTKind_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939	939	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0