Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_upload.u_payloadptr_clr_psync	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.60	94.25	84.31	96.51		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.60	94.25	84.31	96.51		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.37	100.00	86.11		100.00	95.74	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T20,T30,T31
1	0	Covered	T20,T30,T31
1	1	Covered	T20,T30,T31

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T20,T30,T31
1	0	Covered	T20,T30,T31
1	1	Covered	T20,T30,T31

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T20,T21,T22

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1650138210	3137	0	0
SrcPulseCheck_M	536073144	3137	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1650138210	3137	0	0
T2	0	15	0	0
T20	153662	3	0	0
T21	47823	0	0	0
T22	234327	0	0	0
T23	430130	0	0	0
T24	60345	0	0	0
T25	18557	0	0	0
T26	2258	0	0	0
T27	30778	0	0	0
T28	4961	0	0	0
T29	95760	0	0	0
T30	0	21	0	0
T31	180676	7	0	0
T32	226706	0	0	0
T33	302748	0	0	0
T34	747972	18	0	0
T35	130438	0	0	0
T43	0	17	0	0
T52	202750	7	0	0
T53	209270	19	0	0
T56	0	11	0	0
T57	3596	0	0	0
T65	0	19	0	0
T66	0	9	0	0
T73	0	38	0	0
T74	0	2	0	0
T75	0	2	0	0
T96	52776	0	0	0
T99	1908222	0	0	0
T100	0	3	0	0
T101	0	7	0	0
T108	0	12	0	0
T109	0	1	0	0
T110	0	7	0	0
T111	0	21	0	0
T112	0	9	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	536073144	3137	0	0
T2	0	15	0	0
T20	530293	3	0	0
T21	44652	0	0	0
T22	73802	0	0	0
T23	106866	0	0	0
T24	224107	0	0	0
T25	41220	0	0	0
T27	55472	0	0	0
T29	11568	0	0	0
T30	803168	21	0	0
T31	49848	7	0	0
T32	73948	0	0	0
T33	141628	0	0	0
T34	1983762	18	0	0
T35	175080	0	0	0
T43	0	17	0	0
T44	307140	0	0	0
T52	32558	7	0	0
T53	296930	19	0	0
T56	0	11	0	0
T65	0	19	0	0
T66	0	9	0	0
T73	0	38	0	0
T74	0	2	0	0
T75	0	2	0	0
T96	6272	0	0	0
T99	236564	0	0	0
T100	0	3	0	0
T101	0	7	0	0
T108	0	12	0	0
T109	0	1	0	0
T110	0	7	0	0
T111	0	21	0	0
T112	0	9	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T31,T52,T53
1	0	Covered	T31,T52,T53
1	1	Covered	T31,T52,T53

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T31,T52,T53
1	0	Covered	T31,T52,T53
1	1	Covered	T31,T52,T53

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T20,T21,T22

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	550046070	297	0	0
SrcPulseCheck_M	178691048	297	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	297	0	0
T31	90338	2	0	0
T32	113353	0	0	0
T33	151374	0	0	0
T34	373986	0	0	0
T35	65219	0	0	0
T52	101375	2	0	0
T53	104635	10	0	0
T57	1798	0	0	0
T66	0	5	0	0
T96	26388	0	0	0
T99	954111	0	0	0
T100	0	2	0	0
T101	0	2	0	0
T108	0	6	0	0
T109	0	1	0	0
T110	0	2	0	0
T111	0	11	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	178691048	297	0	0
T31	16616	2	0	0
T32	36974	0	0	0
T33	70814	0	0	0
T34	991881	0	0	0
T35	87540	0	0	0
T44	153570	0	0	0
T52	16279	2	0	0
T53	148465	10	0	0
T66	0	5	0	0
T96	3136	0	0	0
T99	118282	0	0	0
T100	0	2	0	0
T101	0	2	0	0
T108	0	6	0	0
T109	0	1	0	0
T110	0	2	0	0
T111	0	11	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T31,T52,T53
1	0	Covered	T31,T52,T53
1	1	Covered	T31,T52,T53

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T31,T52,T53
1	0	Covered	T31,T52,T53
1	1	Covered	T31,T52,T53

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T20,T21,T22

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	550046070	496	0	0
SrcPulseCheck_M	178691048	496	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	496	0	0
T31	90338	5	0	0
T32	113353	0	0	0
T33	151374	0	0	0
T34	373986	0	0	0
T35	65219	0	0	0
T52	101375	5	0	0
T53	104635	9	0	0
T57	1798	0	0	0
T66	0	4	0	0
T96	26388	0	0	0
T99	954111	0	0	0
T100	0	1	0	0
T101	0	5	0	0
T108	0	6	0	0
T110	0	5	0	0
T111	0	10	0	0
T112	0	9	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	178691048	496	0	0
T31	16616	5	0	0
T32	36974	0	0	0
T33	70814	0	0	0
T34	991881	0	0	0
T35	87540	0	0	0
T44	153570	0	0	0
T52	16279	5	0	0
T53	148465	9	0	0
T66	0	4	0	0
T96	3136	0	0	0
T99	118282	0	0	0
T100	0	1	0	0
T101	0	5	0	0
T108	0	6	0	0
T110	0	5	0	0
T111	0	10	0	0
T112	0	9	0	0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T20,T30,T34
1	0	Covered	T20,T30,T34
1	1	Covered	T20,T30,T34

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T20,T30,T34
1	0	Covered	T20,T30,T34
1	1	Covered	T20,T30,T34

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T20,T21,T22

---

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	550046070	2344	0	0
SrcPulseCheck_M	178691048	2344	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	2344	0	0
T2	0	15	0	0
T20	153662	3	0	0
T21	47823	0	0	0
T22	234327	0	0	0
T23	430130	0	0	0
T24	60345	0	0	0
T25	18557	0	0	0
T26	2258	0	0	0
T27	30778	0	0	0
T28	4961	0	0	0
T29	95760	0	0	0
T30	0	21	0	0
T34	0	18	0	0
T43	0	17	0	0
T56	0	11	0	0
T65	0	19	0	0
T73	0	38	0	0
T74	0	2	0	0
T75	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	178691048	2344	0	0
T2	0	15	0	0
T20	530293	3	0	0
T21	44652	0	0	0
T22	73802	0	0	0
T23	106866	0	0	0
T24	224107	0	0	0
T25	41220	0	0	0
T27	55472	0	0	0
T29	11568	0	0	0
T30	803168	21	0	0
T31	16616	0	0	0
T34	0	18	0	0
T43	0	17	0	0
T56	0	11	0	0
T65	0	19	0	0
T73	0	38	0	0
T74	0	2	0	0
T75	0	2	0	0