Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.fifo_h.reqfifo

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
62.50		75.00			50.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
62.50		75.00			50.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	550046070	13413366	0	0
DepthKnown_A	550046070	549960837	0	0
RvalidKnown_A	550046070	549960837	0	0
WreadyKnown_A	550046070	549960837	0	0
gen_passthru_fifo.paramCheckPass	939	939	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	13413366	0	0
T20	153662	18414	0	0
T21	47823	1717	0	0
T22	234327	1272	0	0
T23	430130	898	0	0
T24	60345	1751	0	0
T25	18557	113	0	0
T26	2258	201	0	0
T27	30778	1761	0	0
T28	4961	269	0	0
T29	95760	1710	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	549960837	0	0
T20	153662	153581	0	0
T21	47823	47766	0	0
T22	234327	234259	0	0
T23	430130	430065	0	0
T24	60345	60256	0	0
T25	18557	18499	0	0
T26	2258	2198	0	0
T27	30778	30719	0	0
T28	4961	4664	0	0
T29	95760	95703	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	549960837	0	0
T20	153662	153581	0	0
T21	47823	47766	0	0
T22	234327	234259	0	0
T23	430130	430065	0	0
T24	60345	60256	0	0
T25	18557	18499	0	0
T26	2258	2198	0	0
T27	30778	30719	0	0
T28	4961	4664	0	0
T29	95760	95703	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	549960837	0	0
T20	153662	153581	0	0
T21	47823	47766	0	0
T22	234327	234259	0	0
T23	430130	430065	0	0
T24	60345	60256	0	0
T25	18557	18499	0	0
T26	2258	2198	0	0
T27	30778	30719	0	0
T28	4961	4664	0	0
T29	95760	95703	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	939	939	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	550046070	26444244	0	0
DepthKnown_A	550046070	549960837	0	0
RvalidKnown_A	550046070	549960837	0	0
WreadyKnown_A	550046070	549960837	0	0
gen_passthru_fifo.paramCheckPass	939	939	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	26444244	0	0
T20	153662	30355	0	0
T21	47823	886	0	0
T22	234327	3877	0	0
T23	430130	898	0	0
T24	60345	1232	0	0
T25	18557	506	0	0
T26	2258	201	0	0
T27	30778	929	0	0
T28	4961	269	0	0
T29	95760	1048	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	549960837	0	0
T20	153662	153581	0	0
T21	47823	47766	0	0
T22	234327	234259	0	0
T23	430130	430065	0	0
T24	60345	60256	0	0
T25	18557	18499	0	0
T26	2258	2198	0	0
T27	30778	30719	0	0
T28	4961	4664	0	0
T29	95760	95703	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	549960837	0	0
T20	153662	153581	0	0
T21	47823	47766	0	0
T22	234327	234259	0	0
T23	430130	430065	0	0
T24	60345	60256	0	0
T25	18557	18499	0	0
T26	2258	2198	0	0
T27	30778	30719	0	0
T28	4961	4664	0	0
T29	95760	95703	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	549960837	0	0
T20	153662	153581	0	0
T21	47823	47766	0	0
T22	234327	234259	0	0
T23	430130	430065	0	0
T24	60345	60256	0	0
T25	18557	18499	0	0
T26	2258	2198	0	0
T27	30778	30719	0	0
T28	4961	4664	0	0
T29	95760	95703	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	939	939	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	550046070	3204925	0	0
DepthKnown_A	550046070	549960837	0	0
RvalidKnown_A	550046070	549960837	0	0
WreadyKnown_A	550046070	549960837	0	0
gen_passthru_fifo.paramCheckPass	939	939	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	3204925	0	0
T20	153662	8317	0	0
T21	47823	1663	0	0
T22	234327	832	0	0
T23	430130	832	0	0
T24	60345	1669	0	0
T25	18557	0	0	0
T26	2258	100	0	0
T27	30778	1663	0	0
T28	4961	0	0	0
T29	95760	1663	0	0
T30	0	20793	0	0
T31	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	549960837	0	0
T20	153662	153581	0	0
T21	47823	47766	0	0
T22	234327	234259	0	0
T23	430130	430065	0	0
T24	60345	60256	0	0
T25	18557	18499	0	0
T26	2258	2198	0	0
T27	30778	30719	0	0
T28	4961	4664	0	0
T29	95760	95703	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	549960837	0	0
T20	153662	153581	0	0
T21	47823	47766	0	0
T22	234327	234259	0	0
T23	430130	430065	0	0
T24	60345	60256	0	0
T25	18557	18499	0	0
T26	2258	2198	0	0
T27	30778	30719	0	0
T28	4961	4664	0	0
T29	95760	95703	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	549960837	0	0
T20	153662	153581	0	0
T21	47823	47766	0	0
T22	234327	234259	0	0
T23	430130	430065	0	0
T24	60345	60256	0	0
T25	18557	18499	0	0
T26	2258	2198	0	0
T27	30778	30719	0	0
T28	4961	4664	0	0
T29	95760	95703	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	939	939	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	550046070	3643126	0	0
DepthKnown_A	550046070	549960837	0	0
RvalidKnown_A	550046070	549960837	0	0
WreadyKnown_A	550046070	549960837	0	0
gen_passthru_fifo.paramCheckPass	939	939	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	3643126	0	0
T20	153662	8979	0	0
T21	47823	832	0	0
T22	234327	2594	0	0
T23	430130	832	0	0
T24	60345	838	0	0
T25	18557	0	0	0
T26	2258	100	0	0
T27	30778	832	0	0
T28	4961	0	0	0
T29	95760	832	0	0
T30	0	14976	0	0
T31	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	549960837	0	0
T20	153662	153581	0	0
T21	47823	47766	0	0
T22	234327	234259	0	0
T23	430130	430065	0	0
T24	60345	60256	0	0
T25	18557	18499	0	0
T26	2258	2198	0	0
T27	30778	30719	0	0
T28	4961	4664	0	0
T29	95760	95703	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	549960837	0	0
T20	153662	153581	0	0
T21	47823	47766	0	0
T22	234327	234259	0	0
T23	430130	430065	0	0
T24	60345	60256	0	0
T25	18557	18499	0	0
T26	2258	2198	0	0
T27	30778	30719	0	0
T28	4961	4664	0	0
T29	95760	95703	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	549960837	0	0
T20	153662	153581	0	0
T21	47823	47766	0	0
T22	234327	234259	0	0
T23	430130	430065	0	0
T24	60345	60256	0	0
T25	18557	18499	0	0
T26	2258	2198	0	0
T27	30778	30719	0	0
T28	4961	4664	0	0
T29	95760	95703	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	939	939	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	550046070	209099	0	0
DepthKnown_A	550046070	549960837	0	0
RvalidKnown_A	550046070	549960837	0	0
WreadyKnown_A	550046070	549960837	0	0
gen_passthru_fifo.paramCheckPass	939	939	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	209099	0	0
T11	0	31	0	0
T17	0	23	0	0
T20	153662	588	0	0
T21	47823	0	0	0
T22	234327	0	0	0
T23	430130	0	0	0
T24	60345	0	0	0
T25	18557	0	0	0
T26	2258	100	0	0
T27	30778	0	0	0
T28	4961	0	0	0
T29	95760	0	0	0
T30	0	1101	0	0
T33	0	435	0	0
T34	0	3075	0	0
T36	0	1136	0	0
T37	0	1589	0	0
T43	0	258	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	549960837	0	0
T20	153662	153581	0	0
T21	47823	47766	0	0
T22	234327	234259	0	0
T23	430130	430065	0	0
T24	60345	60256	0	0
T25	18557	18499	0	0
T26	2258	2198	0	0
T27	30778	30719	0	0
T28	4961	4664	0	0
T29	95760	95703	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	549960837	0	0
T20	153662	153581	0	0
T21	47823	47766	0	0
T22	234327	234259	0	0
T23	430130	430065	0	0
T24	60345	60256	0	0
T25	18557	18499	0	0
T26	2258	2198	0	0
T27	30778	30719	0	0
T28	4961	4664	0	0
T29	95760	95703	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	549960837	0	0
T20	153662	153581	0	0
T21	47823	47766	0	0
T22	234327	234259	0	0
T23	430130	430065	0	0
T24	60345	60256	0	0
T25	18557	18499	0	0
T26	2258	2198	0	0
T27	30778	30719	0	0
T28	4961	4664	0	0
T29	95760	95703	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	939	939	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	550046070	487076	0	0
DepthKnown_A	550046070	549960837	0	0
RvalidKnown_A	550046070	549960837	0	0
WreadyKnown_A	550046070	549960837	0	0
gen_passthru_fifo.paramCheckPass	939	939	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	487076	0	0
T11	0	31	0	0
T17	0	23	0	0
T20	153662	2200	0	0
T21	47823	0	0	0
T22	234327	0	0	0
T23	430130	0	0	0
T24	60345	0	0	0
T25	18557	0	0	0
T26	2258	100	0	0
T27	30778	0	0	0
T28	4961	0	0	0
T29	95760	0	0	0
T30	0	1100	0	0
T33	0	435	0	0
T34	0	3073	0	0
T36	0	5163	0	0
T37	0	1589	0	0
T43	0	258	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	549960837	0	0
T20	153662	153581	0	0
T21	47823	47766	0	0
T22	234327	234259	0	0
T23	430130	430065	0	0
T24	60345	60256	0	0
T25	18557	18499	0	0
T26	2258	2198	0	0
T27	30778	30719	0	0
T28	4961	4664	0	0
T29	95760	95703	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	549960837	0	0
T20	153662	153581	0	0
T21	47823	47766	0	0
T22	234327	234259	0	0
T23	430130	430065	0	0
T24	60345	60256	0	0
T25	18557	18499	0	0
T26	2258	2198	0	0
T27	30778	30719	0	0
T28	4961	4664	0	0
T29	95760	95703	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	549960837	0	0
T20	153662	153581	0	0
T21	47823	47766	0	0
T22	234327	234259	0	0
T23	430130	430065	0	0
T24	60345	60256	0	0
T25	18557	18499	0	0
T26	2258	2198	0	0
T27	30778	30719	0	0
T28	4961	4664	0	0
T29	95760	95703	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	939	939	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0