Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	550046070	9686499	0	0
DepthKnown_A	550046070	549960837	0	0
RvalidKnown_A	550046070	549960837	0	0
WreadyKnown_A	550046070	549960837	0	0
gen_passthru_fifo.paramCheckPass	939	939	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	9686499	0	0
T20	153662	7156	0	0
T21	47823	54	0	0
T22	234327	428	0	0
T23	430130	66	0	0
T24	60345	82	0	0
T25	18557	113	0	0
T26	2258	1	0	0
T27	30778	97	0	0
T28	4961	269	0	0
T29	95760	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	549960837	0	0
T20	153662	153581	0	0
T21	47823	47766	0	0
T22	234327	234259	0	0
T23	430130	430065	0	0
T24	60345	60256	0	0
T25	18557	18499	0	0
T26	2258	2198	0	0
T27	30778	30719	0	0
T28	4961	4664	0	0
T29	95760	95703	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	549960837	0	0
T20	153662	153581	0	0
T21	47823	47766	0	0
T22	234327	234259	0	0
T23	430130	430065	0	0
T24	60345	60256	0	0
T25	18557	18499	0	0
T26	2258	2198	0	0
T27	30778	30719	0	0
T28	4961	4664	0	0
T29	95760	95703	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	549960837	0	0
T20	153662	153581	0	0
T21	47823	47766	0	0
T22	234327	234259	0	0
T23	430130	430065	0	0
T24	60345	60256	0	0
T25	18557	18499	0	0
T26	2258	2198	0	0
T27	30778	30719	0	0
T28	4961	4664	0	0
T29	95760	95703	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	939	939	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	550046070	22314042	0	0
DepthKnown_A	550046070	549960837	0	0
RvalidKnown_A	550046070	549960837	0	0
WreadyKnown_A	550046070	549960837	0	0
gen_passthru_fifo.paramCheckPass	939	939	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	22314042	0	0
T20	153662	19176	0	0
T21	47823	54	0	0
T22	234327	1283	0	0
T23	430130	66	0	0
T24	60345	394	0	0
T25	18557	506	0	0
T26	2258	1	0	0
T27	30778	97	0	0
T28	4961	269	0	0
T29	95760	216	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	549960837	0	0
T20	153662	153581	0	0
T21	47823	47766	0	0
T22	234327	234259	0	0
T23	430130	430065	0	0
T24	60345	60256	0	0
T25	18557	18499	0	0
T26	2258	2198	0	0
T27	30778	30719	0	0
T28	4961	4664	0	0
T29	95760	95703	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	549960837	0	0
T20	153662	153581	0	0
T21	47823	47766	0	0
T22	234327	234259	0	0
T23	430130	430065	0	0
T24	60345	60256	0	0
T25	18557	18499	0	0
T26	2258	2198	0	0
T27	30778	30719	0	0
T28	4961	4664	0	0
T29	95760	95703	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	549960837	0	0
T20	153662	153581	0	0
T21	47823	47766	0	0
T22	234327	234259	0	0
T23	430130	430065	0	0
T24	60345	60256	0	0
T25	18557	18499	0	0
T26	2258	2198	0	0
T27	30778	30719	0	0
T28	4961	4664	0	0
T29	95760	95703	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	939	939	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0