Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T20,T30,T33
1	0	Covered	T20,T30,T33

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T20,T21,T22

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T20,T25,T30
1	0	Unreachable
1	1	Covered	T20,T30,T33

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T20,T30,T34

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T20,T30,T34
1	0	Covered	T20,T30,T34

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T20,T21,T22

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Unreachable
1	1	Covered	T20,T30,T34

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T20,T26,T30

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T20,T26,T30
1	0	Covered	T20,T21,T22

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T20,T21,T22

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Unreachable
1	1	Covered	T20,T21,T22

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T26,T30
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T20,T21,T22
0	1	-	Covered	T20,T21,T22
0	0	1	Unreachable
0	0	0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T20,T21,T22

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	907428166	726883204	0	0
CheckNGreaterZero_A	2817	2817	0	0
GntImpliesReady_A	907428166	4155397	0	0
GntImpliesValid_A	907428166	4155397	0	0
GrantKnown_A	907428166	726883204	0	0
IdxKnown_A	907428166	726883204	0	0
IndexIsCorrect_A	907428166	4155397	0	0
LockArbDecision_A	907428166	0	0	0
NoReadyValidNoGrant_A	907428166	0	0	0
ReadyAndValidImplyGrant_A	907428166	4155397	0	0
ReqAndReadyImplyGrant_A	907428166	4155397	0	0
ReqImpliesValid_A	907428166	4155397	0	0
ReqStaysHighUntilGranted0_M	907428166	0	0	0
RoundRobin_A	907428166	5	0	939
ValidKnown_A	907428166	726883204	0	0
gen_data_port_assertion.DataFlow_A	907428166	4155397	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	907428166	726883204	0	0
T11	0	3968	0	0
T17	0	2744	0	0
T20	1214248	677665	0	0
T21	137127	92418	0	0
T22	381931	307715	0	0
T23	643862	536931	0	0
T24	508559	284244	0	0
T25	100997	57683	0	0
T26	2258	2198	0	0
T27	141722	86191	0	0
T28	4961	4664	0	0
T29	118896	107271	0	0
T30	1606336	794475	0	0
T31	33232	16616	0	0
T32	0	36974	0	0
T33	0	69088	0	0
T34	0	341224	0	0
T35	0	83736	0	0
T36	0	180344	0	0
T37	0	195432	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2817	2817	0	0
T20	3	3	0	0
T21	3	3	0	0
T22	3	3	0	0
T23	3	3	0	0
T24	3	3	0	0
T25	3	3	0	0
T26	3	3	0	0
T27	3	3	0	0
T28	3	3	0	0
T29	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	907428166	4155397	0	0
T2	0	9211	0	0
T11	0	159	0	0
T17	0	137	0	0
T19	0	3206	0	0
T20	1214248	11055	0	0
T21	137127	832	0	0
T22	381931	832	0	0
T23	643862	832	0	0
T24	508559	832	0	0
T25	100997	0	0	0
T26	2258	200	0	0
T27	141722	832	0	0
T28	4961	0	0	0
T29	118896	832	0	0
T30	1606336	24466	0	0
T31	33232	832	0	0
T33	0	2441	0	0
T34	0	17789	0	0
T36	0	7369	0	0
T37	0	9245	0	0
T43	0	3242	0	0
T56	0	788	0	0
T73	0	8542	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	907428166	4155397	0	0
T2	0	9211	0	0
T11	0	159	0	0
T17	0	137	0	0
T19	0	3206	0	0
T20	1214248	11055	0	0
T21	137127	832	0	0
T22	381931	832	0	0
T23	643862	832	0	0
T24	508559	832	0	0
T25	100997	0	0	0
T26	2258	200	0	0
T27	141722	832	0	0
T28	4961	0	0	0
T29	118896	832	0	0
T30	1606336	24466	0	0
T31	33232	832	0	0
T33	0	2441	0	0
T34	0	17789	0	0
T36	0	7369	0	0
T37	0	9245	0	0
T43	0	3242	0	0
T56	0	788	0	0
T73	0	8542	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	907428166	726883204	0	0
T11	0	3968	0	0
T17	0	2744	0	0
T20	1214248	677665	0	0
T21	137127	92418	0	0
T22	381931	307715	0	0
T23	643862	536931	0	0
T24	508559	284244	0	0
T25	100997	57683	0	0
T26	2258	2198	0	0
T27	141722	86191	0	0
T28	4961	4664	0	0
T29	118896	107271	0	0
T30	1606336	794475	0	0
T31	33232	16616	0	0
T32	0	36974	0	0
T33	0	69088	0	0
T34	0	341224	0	0
T35	0	83736	0	0
T36	0	180344	0	0
T37	0	195432	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	907428166	726883204	0	0
T11	0	3968	0	0
T17	0	2744	0	0
T20	1214248	677665	0	0
T21	137127	92418	0	0
T22	381931	307715	0	0
T23	643862	536931	0	0
T24	508559	284244	0	0
T25	100997	57683	0	0
T26	2258	2198	0	0
T27	141722	86191	0	0
T28	4961	4664	0	0
T29	118896	107271	0	0
T30	1606336	794475	0	0
T31	33232	16616	0	0
T32	0	36974	0	0
T33	0	69088	0	0
T34	0	341224	0	0
T35	0	83736	0	0
T36	0	180344	0	0
T37	0	195432	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	907428166	4155397	0	0
T2	0	9211	0	0
T11	0	159	0	0
T17	0	137	0	0
T19	0	3206	0	0
T20	1214248	11055	0	0
T21	137127	832	0	0
T22	381931	832	0	0
T23	643862	832	0	0
T24	508559	832	0	0
T25	100997	0	0	0
T26	2258	200	0	0
T27	141722	832	0	0
T28	4961	0	0	0
T29	118896	832	0	0
T30	1606336	24466	0	0
T31	33232	832	0	0
T33	0	2441	0	0
T34	0	17789	0	0
T36	0	7369	0	0
T37	0	9245	0	0
T43	0	3242	0	0
T56	0	788	0	0
T73	0	8542	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	907428166	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	907428166	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	907428166	4155397	0	0
T2	0	9211	0	0
T11	0	159	0	0
T17	0	137	0	0
T19	0	3206	0	0
T20	1214248	11055	0	0
T21	137127	832	0	0
T22	381931	832	0	0
T23	643862	832	0	0
T24	508559	832	0	0
T25	100997	0	0	0
T26	2258	200	0	0
T27	141722	832	0	0
T28	4961	0	0	0
T29	118896	832	0	0
T30	1606336	24466	0	0
T31	33232	832	0	0
T33	0	2441	0	0
T34	0	17789	0	0
T36	0	7369	0	0
T37	0	9245	0	0
T43	0	3242	0	0
T56	0	788	0	0
T73	0	8542	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	907428166	4155397	0	0
T2	0	9211	0	0
T11	0	159	0	0
T17	0	137	0	0
T19	0	3206	0	0
T20	1214248	11055	0	0
T21	137127	832	0	0
T22	381931	832	0	0
T23	643862	832	0	0
T24	508559	832	0	0
T25	100997	0	0	0
T26	2258	200	0	0
T27	141722	832	0	0
T28	4961	0	0	0
T29	118896	832	0	0
T30	1606336	24466	0	0
T31	33232	832	0	0
T33	0	2441	0	0
T34	0	17789	0	0
T36	0	7369	0	0
T37	0	9245	0	0
T43	0	3242	0	0
T56	0	788	0	0
T73	0	8542	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	907428166	4155397	0	0
T2	0	9211	0	0
T11	0	159	0	0
T17	0	137	0	0
T19	0	3206	0	0
T20	1214248	11055	0	0
T21	137127	832	0	0
T22	381931	832	0	0
T23	643862	832	0	0
T24	508559	832	0	0
T25	100997	0	0	0
T26	2258	200	0	0
T27	141722	832	0	0
T28	4961	0	0	0
T29	118896	832	0	0
T30	1606336	24466	0	0
T31	33232	832	0	0
T33	0	2441	0	0
T34	0	17789	0	0
T36	0	7369	0	0
T37	0	9245	0	0
T43	0	3242	0	0
T56	0	788	0	0
T73	0	8542	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	907428166	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	907428166	5	0	939
T76	271394	1	0	1
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	565820	0	0	1
T82	54509	0	0	1
T83	331863	0	0	1
T84	519939	0	0	1
T85	4144	0	0	1
T86	28099	0	0	1
T87	232120	0	0	1
T88	3632	0	0	1
T89	491036	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	907428166	726883204	0	0
T11	0	3968	0	0
T17	0	2744	0	0
T20	1214248	677665	0	0
T21	137127	92418	0	0
T22	381931	307715	0	0
T23	643862	536931	0	0
T24	508559	284244	0	0
T25	100997	57683	0	0
T26	2258	2198	0	0
T27	141722	86191	0	0
T28	4961	4664	0	0
T29	118896	107271	0	0
T30	1606336	794475	0	0
T31	33232	16616	0	0
T32	0	36974	0	0
T33	0	69088	0	0
T34	0	341224	0	0
T35	0	83736	0	0
T36	0	180344	0	0
T37	0	195432	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	907428166	4155397	0	0
T2	0	9211	0	0
T11	0	159	0	0
T17	0	137	0	0
T19	0	3206	0	0
T20	1214248	11055	0	0
T21	137127	832	0	0
T22	381931	832	0	0
T23	643862	832	0	0
T24	508559	832	0	0
T25	100997	0	0	0
T26	2258	200	0	0
T27	141722	832	0	0
T28	4961	0	0	0
T29	118896	832	0	0
T30	1606336	24466	0	0
T31	33232	832	0	0
T33	0	2441	0	0
T34	0	17789	0	0
T36	0	7369	0	0
T37	0	9245	0	0
T43	0	3242	0	0
T56	0	788	0	0
T73	0	8542	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T20,T30,T33
1	0	Covered	T20,T30,T33

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T20,T21,T22

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T20,T25,T30
1	0	Unreachable
1	1	Covered	T20,T30,T33

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T20,T21,T22
0	1	-	Covered	T20,T30,T33
0	0	1	Unreachable
0	0	0	Covered	T20,T25,T30

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T20,T30,T33
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T20,T30,T33
0	Covered	T20,T21,T22

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	178691048	38985718	0	0
CheckNGreaterZero_A	939	939	0	0
GntImpliesReady_A	178691048	883322	0	0
GntImpliesValid_A	178691048	883322	0	0
GrantKnown_A	178691048	38985718	0	0
IdxKnown_A	178691048	38985718	0	0
IndexIsCorrect_A	178691048	883322	0	0
LockArbDecision_A	178691048	0	0	0
NoReadyValidNoGrant_A	178691048	0	0	0
ReadyAndValidImplyGrant_A	178691048	883322	0	0
ReqAndReadyImplyGrant_A	178691048	883322	0	0
ReqImpliesValid_A	178691048	883322	0	0
ReqStaysHighUntilGranted0_M	178691048	0	0	0
RoundRobin_A	178691048	0	0	0
ValidKnown_A	178691048	38985718	0	0
gen_data_port_assertion.DataFlow_A	178691048	883322	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178691048	38985718	0	0
T11	0	3968	0	0
T17	0	2744	0	0
T20	530293	269720	0	0
T21	44652	0	0	0
T22	73802	0	0	0
T23	106866	0	0	0
T24	224107	0	0	0
T25	41220	39184	0	0
T27	55472	0	0	0
T29	11568	0	0	0
T30	803168	116168	0	0
T31	16616	0	0	0
T33	0	69088	0	0
T34	0	341224	0	0
T35	0	83736	0	0
T36	0	180344	0	0
T37	0	195432	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939	939	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178691048	883322	0	0
T2	0	6884	0	0
T11	0	159	0	0
T17	0	137	0	0
T19	0	3206	0	0
T20	530293	2888	0	0
T21	44652	0	0	0
T22	73802	0	0	0
T23	106866	0	0	0
T24	224107	0	0	0
T25	41220	0	0	0
T27	55472	0	0	0
T29	11568	0	0	0
T30	803168	4831	0	0
T31	16616	0	0	0
T33	0	2441	0	0
T34	0	14540	0	0
T36	0	7369	0	0
T37	0	9245	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178691048	883322	0	0
T2	0	6884	0	0
T11	0	159	0	0
T17	0	137	0	0
T19	0	3206	0	0
T20	530293	2888	0	0
T21	44652	0	0	0
T22	73802	0	0	0
T23	106866	0	0	0
T24	224107	0	0	0
T25	41220	0	0	0
T27	55472	0	0	0
T29	11568	0	0	0
T30	803168	4831	0	0
T31	16616	0	0	0
T33	0	2441	0	0
T34	0	14540	0	0
T36	0	7369	0	0
T37	0	9245	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178691048	38985718	0	0
T11	0	3968	0	0
T17	0	2744	0	0
T20	530293	269720	0	0
T21	44652	0	0	0
T22	73802	0	0	0
T23	106866	0	0	0
T24	224107	0	0	0
T25	41220	39184	0	0
T27	55472	0	0	0
T29	11568	0	0	0
T30	803168	116168	0	0
T31	16616	0	0	0
T33	0	69088	0	0
T34	0	341224	0	0
T35	0	83736	0	0
T36	0	180344	0	0
T37	0	195432	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178691048	38985718	0	0
T11	0	3968	0	0
T17	0	2744	0	0
T20	530293	269720	0	0
T21	44652	0	0	0
T22	73802	0	0	0
T23	106866	0	0	0
T24	224107	0	0	0
T25	41220	39184	0	0
T27	55472	0	0	0
T29	11568	0	0	0
T30	803168	116168	0	0
T31	16616	0	0	0
T33	0	69088	0	0
T34	0	341224	0	0
T35	0	83736	0	0
T36	0	180344	0	0
T37	0	195432	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178691048	883322	0	0
T2	0	6884	0	0
T11	0	159	0	0
T17	0	137	0	0
T19	0	3206	0	0
T20	530293	2888	0	0
T21	44652	0	0	0
T22	73802	0	0	0
T23	106866	0	0	0
T24	224107	0	0	0
T25	41220	0	0	0
T27	55472	0	0	0
T29	11568	0	0	0
T30	803168	4831	0	0
T31	16616	0	0	0
T33	0	2441	0	0
T34	0	14540	0	0
T36	0	7369	0	0
T37	0	9245	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178691048	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178691048	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178691048	883322	0	0
T2	0	6884	0	0
T11	0	159	0	0
T17	0	137	0	0
T19	0	3206	0	0
T20	530293	2888	0	0
T21	44652	0	0	0
T22	73802	0	0	0
T23	106866	0	0	0
T24	224107	0	0	0
T25	41220	0	0	0
T27	55472	0	0	0
T29	11568	0	0	0
T30	803168	4831	0	0
T31	16616	0	0	0
T33	0	2441	0	0
T34	0	14540	0	0
T36	0	7369	0	0
T37	0	9245	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178691048	883322	0	0
T2	0	6884	0	0
T11	0	159	0	0
T17	0	137	0	0
T19	0	3206	0	0
T20	530293	2888	0	0
T21	44652	0	0	0
T22	73802	0	0	0
T23	106866	0	0	0
T24	224107	0	0	0
T25	41220	0	0	0
T27	55472	0	0	0
T29	11568	0	0	0
T30	803168	4831	0	0
T31	16616	0	0	0
T33	0	2441	0	0
T34	0	14540	0	0
T36	0	7369	0	0
T37	0	9245	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178691048	883322	0	0
T2	0	6884	0	0
T11	0	159	0	0
T17	0	137	0	0
T19	0	3206	0	0
T20	530293	2888	0	0
T21	44652	0	0	0
T22	73802	0	0	0
T23	106866	0	0	0
T24	224107	0	0	0
T25	41220	0	0	0
T27	55472	0	0	0
T29	11568	0	0	0
T30	803168	4831	0	0
T31	16616	0	0	0
T33	0	2441	0	0
T34	0	14540	0	0
T36	0	7369	0	0
T37	0	9245	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	178691048	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178691048	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178691048	38985718	0	0
T11	0	3968	0	0
T17	0	2744	0	0
T20	530293	269720	0	0
T21	44652	0	0	0
T22	73802	0	0	0
T23	106866	0	0	0
T24	224107	0	0	0
T25	41220	39184	0	0
T27	55472	0	0	0
T29	11568	0	0	0
T30	803168	116168	0	0
T31	16616	0	0	0
T33	0	69088	0	0
T34	0	341224	0	0
T35	0	83736	0	0
T36	0	180344	0	0
T37	0	195432	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178691048	883322	0	0
T2	0	6884	0	0
T11	0	159	0	0
T17	0	137	0	0
T19	0	3206	0	0
T20	530293	2888	0	0
T21	44652	0	0	0
T22	73802	0	0	0
T23	106866	0	0	0
T24	224107	0	0	0
T25	41220	0	0	0
T27	55472	0	0	0
T29	11568	0	0	0
T30	803168	4831	0	0
T31	16616	0	0	0
T33	0	2441	0	0
T34	0	14540	0	0
T36	0	7369	0	0
T37	0	9245	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T20,T30,T34

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T20,T30,T34
1	0	Covered	T20,T30,T34

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T20,T21,T22

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Unreachable
1	1	Covered	T20,T30,T34

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T30,T34
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T20,T21,T22
0	1	-	Covered	T20,T30,T34
0	0	1	Unreachable
0	0	0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T20,T30,T34
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T20,T30,T34
0	Covered	T20,T21,T22

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	178691048	137936649	0	0
CheckNGreaterZero_A	939	939	0	0
GntImpliesReady_A	178691048	652491	0	0
GntImpliesValid_A	178691048	652491	0	0
GrantKnown_A	178691048	137936649	0	0
IdxKnown_A	178691048	137936649	0	0
IndexIsCorrect_A	178691048	652491	0	0
LockArbDecision_A	178691048	0	0	0
NoReadyValidNoGrant_A	178691048	0	0	0
ReadyAndValidImplyGrant_A	178691048	652491	0	0
ReqAndReadyImplyGrant_A	178691048	652491	0	0
ReqImpliesValid_A	178691048	652491	0	0
ReqStaysHighUntilGranted0_M	178691048	0	0	0
RoundRobin_A	178691048	0	0	0
ValidKnown_A	178691048	137936649	0	0
gen_data_port_assertion.DataFlow_A	178691048	652491	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178691048	137936649	0	0
T20	530293	254364	0	0
T21	44652	44652	0	0
T22	73802	73456	0	0
T23	106866	106866	0	0
T24	224107	223988	0	0
T25	41220	0	0	0
T27	55472	55472	0	0
T29	11568	11568	0	0
T30	803168	678307	0	0
T31	16616	16616	0	0
T32	0	36974	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939	939	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178691048	652491	0	0
T2	0	2327	0	0
T20	530293	941	0	0
T21	44652	0	0	0
T22	73802	0	0	0
T23	106866	0	0	0
T24	224107	0	0	0
T25	41220	0	0	0
T27	55472	0	0	0
T29	11568	0	0	0
T30	803168	1848	0	0
T31	16616	0	0	0
T34	0	3249	0	0
T43	0	3242	0	0
T56	0	788	0	0
T65	0	4178	0	0
T73	0	8542	0	0
T74	0	137	0	0
T75	0	260	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178691048	652491	0	0
T2	0	2327	0	0
T20	530293	941	0	0
T21	44652	0	0	0
T22	73802	0	0	0
T23	106866	0	0	0
T24	224107	0	0	0
T25	41220	0	0	0
T27	55472	0	0	0
T29	11568	0	0	0
T30	803168	1848	0	0
T31	16616	0	0	0
T34	0	3249	0	0
T43	0	3242	0	0
T56	0	788	0	0
T65	0	4178	0	0
T73	0	8542	0	0
T74	0	137	0	0
T75	0	260	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178691048	137936649	0	0
T20	530293	254364	0	0
T21	44652	44652	0	0
T22	73802	73456	0	0
T23	106866	106866	0	0
T24	224107	223988	0	0
T25	41220	0	0	0
T27	55472	55472	0	0
T29	11568	11568	0	0
T30	803168	678307	0	0
T31	16616	16616	0	0
T32	0	36974	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178691048	137936649	0	0
T20	530293	254364	0	0
T21	44652	44652	0	0
T22	73802	73456	0	0
T23	106866	106866	0	0
T24	224107	223988	0	0
T25	41220	0	0	0
T27	55472	55472	0	0
T29	11568	11568	0	0
T30	803168	678307	0	0
T31	16616	16616	0	0
T32	0	36974	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178691048	652491	0	0
T2	0	2327	0	0
T20	530293	941	0	0
T21	44652	0	0	0
T22	73802	0	0	0
T23	106866	0	0	0
T24	224107	0	0	0
T25	41220	0	0	0
T27	55472	0	0	0
T29	11568	0	0	0
T30	803168	1848	0	0
T31	16616	0	0	0
T34	0	3249	0	0
T43	0	3242	0	0
T56	0	788	0	0
T65	0	4178	0	0
T73	0	8542	0	0
T74	0	137	0	0
T75	0	260	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178691048	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178691048	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178691048	652491	0	0
T2	0	2327	0	0
T20	530293	941	0	0
T21	44652	0	0	0
T22	73802	0	0	0
T23	106866	0	0	0
T24	224107	0	0	0
T25	41220	0	0	0
T27	55472	0	0	0
T29	11568	0	0	0
T30	803168	1848	0	0
T31	16616	0	0	0
T34	0	3249	0	0
T43	0	3242	0	0
T56	0	788	0	0
T65	0	4178	0	0
T73	0	8542	0	0
T74	0	137	0	0
T75	0	260	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178691048	652491	0	0
T2	0	2327	0	0
T20	530293	941	0	0
T21	44652	0	0	0
T22	73802	0	0	0
T23	106866	0	0	0
T24	224107	0	0	0
T25	41220	0	0	0
T27	55472	0	0	0
T29	11568	0	0	0
T30	803168	1848	0	0
T31	16616	0	0	0
T34	0	3249	0	0
T43	0	3242	0	0
T56	0	788	0	0
T65	0	4178	0	0
T73	0	8542	0	0
T74	0	137	0	0
T75	0	260	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178691048	652491	0	0
T2	0	2327	0	0
T20	530293	941	0	0
T21	44652	0	0	0
T22	73802	0	0	0
T23	106866	0	0	0
T24	224107	0	0	0
T25	41220	0	0	0
T27	55472	0	0	0
T29	11568	0	0	0
T30	803168	1848	0	0
T31	16616	0	0	0
T34	0	3249	0	0
T43	0	3242	0	0
T56	0	788	0	0
T65	0	4178	0	0
T73	0	8542	0	0
T74	0	137	0	0
T75	0	260	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	178691048	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178691048	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178691048	137936649	0	0
T20	530293	254364	0	0
T21	44652	44652	0	0
T22	73802	73456	0	0
T23	106866	106866	0	0
T24	224107	223988	0	0
T25	41220	0	0	0
T27	55472	55472	0	0
T29	11568	11568	0	0
T30	803168	678307	0	0
T31	16616	16616	0	0
T32	0	36974	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178691048	652491	0	0
T2	0	2327	0	0
T20	530293	941	0	0
T21	44652	0	0	0
T22	73802	0	0	0
T23	106866	0	0	0
T24	224107	0	0	0
T25	41220	0	0	0
T27	55472	0	0	0
T29	11568	0	0	0
T30	803168	1848	0	0
T31	16616	0	0	0
T34	0	3249	0	0
T43	0	3242	0	0
T56	0	788	0	0
T65	0	4178	0	0
T73	0	8542	0	0
T74	0	137	0	0
T75	0	260	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T20,T26,T30

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T22
0	1	Covered	T20,T26,T30
1	0	Covered	T20,T21,T22

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T20,T21,T22

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Unreachable
1	1	Covered	T20,T21,T22

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T26,T30
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T20,T21,T22
0	1	-	Covered	T20,T21,T22
0	0	1	Unreachable
0	0	0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T20,T21,T22

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	550046070	549960837	0	0
CheckNGreaterZero_A	939	939	0	0
GntImpliesReady_A	550046070	2619584	0	0
GntImpliesValid_A	550046070	2619584	0	0
GrantKnown_A	550046070	549960837	0	0
IdxKnown_A	550046070	549960837	0	0
IndexIsCorrect_A	550046070	2619584	0	0
LockArbDecision_A	550046070	0	0	0
NoReadyValidNoGrant_A	550046070	0	0	0
ReadyAndValidImplyGrant_A	550046070	2619584	0	0
ReqAndReadyImplyGrant_A	550046070	2619584	0	0
ReqImpliesValid_A	550046070	2619584	0	0
ReqStaysHighUntilGranted0_M	550046070	0	0	0
RoundRobin_A	550046070	5	0	939
ValidKnown_A	550046070	549960837	0	0
gen_data_port_assertion.DataFlow_A	550046070	2619584	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	549960837	0	0
T20	153662	153581	0	0
T21	47823	47766	0	0
T22	234327	234259	0	0
T23	430130	430065	0	0
T24	60345	60256	0	0
T25	18557	18499	0	0
T26	2258	2198	0	0
T27	30778	30719	0	0
T28	4961	4664	0	0
T29	95760	95703	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	939	939	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	2619584	0	0
T20	153662	7226	0	0
T21	47823	832	0	0
T22	234327	832	0	0
T23	430130	832	0	0
T24	60345	832	0	0
T25	18557	0	0	0
T26	2258	200	0	0
T27	30778	832	0	0
T28	4961	0	0	0
T29	95760	832	0	0
T30	0	17787	0	0
T31	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	2619584	0	0
T20	153662	7226	0	0
T21	47823	832	0	0
T22	234327	832	0	0
T23	430130	832	0	0
T24	60345	832	0	0
T25	18557	0	0	0
T26	2258	200	0	0
T27	30778	832	0	0
T28	4961	0	0	0
T29	95760	832	0	0
T30	0	17787	0	0
T31	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	549960837	0	0
T20	153662	153581	0	0
T21	47823	47766	0	0
T22	234327	234259	0	0
T23	430130	430065	0	0
T24	60345	60256	0	0
T25	18557	18499	0	0
T26	2258	2198	0	0
T27	30778	30719	0	0
T28	4961	4664	0	0
T29	95760	95703	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	549960837	0	0
T20	153662	153581	0	0
T21	47823	47766	0	0
T22	234327	234259	0	0
T23	430130	430065	0	0
T24	60345	60256	0	0
T25	18557	18499	0	0
T26	2258	2198	0	0
T27	30778	30719	0	0
T28	4961	4664	0	0
T29	95760	95703	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	2619584	0	0
T20	153662	7226	0	0
T21	47823	832	0	0
T22	234327	832	0	0
T23	430130	832	0	0
T24	60345	832	0	0
T25	18557	0	0	0
T26	2258	200	0	0
T27	30778	832	0	0
T28	4961	0	0	0
T29	95760	832	0	0
T30	0	17787	0	0
T31	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	2619584	0	0
T20	153662	7226	0	0
T21	47823	832	0	0
T22	234327	832	0	0
T23	430130	832	0	0
T24	60345	832	0	0
T25	18557	0	0	0
T26	2258	200	0	0
T27	30778	832	0	0
T28	4961	0	0	0
T29	95760	832	0	0
T30	0	17787	0	0
T31	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	2619584	0	0
T20	153662	7226	0	0
T21	47823	832	0	0
T22	234327	832	0	0
T23	430130	832	0	0
T24	60345	832	0	0
T25	18557	0	0	0
T26	2258	200	0	0
T27	30778	832	0	0
T28	4961	0	0	0
T29	95760	832	0	0
T30	0	17787	0	0
T31	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	2619584	0	0
T20	153662	7226	0	0
T21	47823	832	0	0
T22	234327	832	0	0
T23	430130	832	0	0
T24	60345	832	0	0
T25	18557	0	0	0
T26	2258	200	0	0
T27	30778	832	0	0
T28	4961	0	0	0
T29	95760	832	0	0
T30	0	17787	0	0
T31	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	5	0	939
T76	271394	1	0	1
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	565820	0	0	1
T82	54509	0	0	1
T83	331863	0	0	1
T84	519939	0	0	1
T85	4144	0	0	1
T86	28099	0	0	1
T87	232120	0	0	1
T88	3632	0	0	1
T89	491036	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	549960837	0	0
T20	153662	153581	0	0
T21	47823	47766	0	0
T22	234327	234259	0	0
T23	430130	430065	0	0
T24	60345	60256	0	0
T25	18557	18499	0	0
T26	2258	2198	0	0
T27	30778	30719	0	0
T28	4961	4664	0	0
T29	95760	95703	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550046070	2619584	0	0
T20	153662	7226	0	0
T21	47823	832	0	0
T22	234327	832	0	0
T23	430130	832	0	0
T24	60345	832	0	0
T25	18557	0	0	0
T26	2258	200	0	0
T27	30778	832	0	0
T28	4961	0	0	0
T29	95760	832	0	0
T30	0	17787	0	0
T31	0	832	0	0