Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6491050	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6800819

1

T1

12652

T2

42451

T3

433

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8550089	1			T1	8953		T2	77596		T3	1
values[0x0]	2369593	1			T1	4015		T2	14192		T3	251
values[0x1]	2372187	1			T1	3921		T2	14205		T3	278

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4695267	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

8596602

1

T1

13504

T2

61068

T3

456

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52817	1			T1	1		T2	459		T3	4
valid_sources[0x01]	51384	1			T1	1		T2	398		T3	8
valid_sources[0x02]	49955	1			T1	1		T2	339		T3	3
valid_sources[0x03]	48597	1			T1	4		T2	357		T5	9
valid_sources[0x04]	53924	1			T1	1		T2	381		T5	1
valid_sources[0x05]	51784	1			T1	5		T2	359		T3	2
valid_sources[0x06]	54397	1			T1	1		T2	321		T6	7
valid_sources[0x07]	52449	1			T1	1		T2	489		T3	3
valid_sources[0x08]	54155	1			T1	11		T2	459		T3	3
valid_sources[0x09]	49286	1			T2	369		T3	4		T5	3
valid_sources[0x0a]	48703	1			T2	383		T5	6		T7	164
valid_sources[0x0b]	51820	1			T1	17		T2	384		T3	4
valid_sources[0x0c]	49392	1			T1	12		T2	473		T3	1
valid_sources[0x0d]	56477	1			T1	2		T2	346		T3	1
valid_sources[0x0e]	48807	1			T1	139		T2	517		T3	9
valid_sources[0x0f]	51084	1			T1	48		T2	402		T3	1
valid_sources[0x10]	50535	1			T1	35		T2	408		T3	4
valid_sources[0x11]	52752	1			T1	1		T2	435		T3	1
valid_sources[0x12]	52096	1			T1	1425		T2	450		T3	3
valid_sources[0x13]	56950	1			T1	1425		T2	408		T3	3
valid_sources[0x14]	52028	1			T1	145		T2	440		T3	1
valid_sources[0x15]	53171	1			T1	1		T2	435		T3	4
valid_sources[0x16]	51241	1			T1	44		T2	376		T3	2
valid_sources[0x17]	51375	1			T1	58		T2	460		T3	1
valid_sources[0x18]	60118	1			T1	1		T2	607		T3	3
valid_sources[0x19]	52820	1			T1	2		T2	492		T3	6
valid_sources[0x1a]	50064	1			T1	2		T2	527		T3	1
valid_sources[0x1b]	50335	1			T1	2		T2	410		T3	4
valid_sources[0x1c]	52529	1			T1	1178		T2	317		T3	2
valid_sources[0x1d]	50305	1			T2	407		T3	1		T5	1
valid_sources[0x1e]	56003	1			T1	3		T2	448		T3	3
valid_sources[0x1f]	50712	1			T1	5		T2	398		T3	2
valid_sources[0x20]	48455	1			T1	2		T2	406		T5	8
valid_sources[0x21]	51541	1			T1	3		T2	392		T3	2
valid_sources[0x22]	50332	1			T1	1		T2	438		T5	5
valid_sources[0x23]	52504	1			T1	1		T2	360		T5	3
valid_sources[0x24]	51660	1			T1	3		T2	378		T3	1
valid_sources[0x25]	50474	1			T1	32		T2	427		T3	2
valid_sources[0x26]	50407	1			T1	654		T2	308		T3	1
valid_sources[0x27]	49608	1			T1	2		T2	474		T3	2
valid_sources[0x28]	49985	1			T1	6		T2	334		T3	2
valid_sources[0x29]	51081	1			T1	3		T2	402		T3	4
valid_sources[0x2a]	49504	1			T1	206		T2	414		T3	2
valid_sources[0x2b]	54688	1			T2	362		T3	1		T5	7
valid_sources[0x2c]	51879	1			T1	2		T2	449		T3	6
valid_sources[0x2d]	50248	1			T1	2		T2	385		T3	6
valid_sources[0x2e]	53070	1			T1	8		T2	360		T3	4
valid_sources[0x2f]	51202	1			T1	1		T2	421		T3	2
valid_sources[0x30]	51372	1			T1	1		T2	447		T3	1
valid_sources[0x31]	50768	1			T1	16		T2	460		T3	2
valid_sources[0x32]	51222	1			T2	433		T3	1		T5	3
valid_sources[0x33]	50051	1			T1	6		T2	319		T3	1
valid_sources[0x34]	48592	1			T1	1		T2	432		T3	1
valid_sources[0x35]	52476	1			T1	2		T2	367		T3	7
valid_sources[0x36]	52111	1			T2	380		T5	3		T7	203
valid_sources[0x37]	56784	1			T1	5		T2	302		T6	6
valid_sources[0x38]	56831	1			T2	410		T3	4		T5	6
valid_sources[0x39]	50372	1			T1	1		T2	439		T3	3
valid_sources[0x3a]	52602	1			T1	470		T2	445		T3	2
valid_sources[0x3b]	52559	1			T2	380		T3	3		T6	2
valid_sources[0x3c]	50710	1			T1	1		T2	413		T5	2
valid_sources[0x3d]	51848	1			T1	1		T2	407		T3	4
valid_sources[0x3e]	53398	1			T1	2		T2	474		T3	5
valid_sources[0x3f]	48195	1			T1	1		T2	417		T3	1
valid_sources[0x40]	51335	1			T1	1		T2	318		T5	5
valid_sources[0x41]	51984	1			T2	438		T3	3		T4	2
valid_sources[0x42]	53258	1			T2	480		T3	1		T5	3
valid_sources[0x43]	49834	1			T1	2		T2	429		T3	2
valid_sources[0x44]	50891	1			T1	1		T2	429		T3	1
valid_sources[0x45]	53539	1			T2	467		T3	2		T5	1
valid_sources[0x46]	51666	1			T2	523		T3	1		T5	1
valid_sources[0x47]	54144	1			T2	453		T3	2		T6	3
valid_sources[0x48]	49632	1			T1	167		T2	376		T3	4
valid_sources[0x49]	50881	1			T1	1		T2	440		T3	3
valid_sources[0x4a]	53413	1			T2	483		T3	1		T4	4
valid_sources[0x4b]	49150	1			T1	6		T2	325		T5	5
valid_sources[0x4c]	52639	1			T1	766		T2	443		T3	2
valid_sources[0x4d]	53851	1			T1	419		T2	435		T5	8
valid_sources[0x4e]	50356	1			T1	3		T2	387		T3	4
valid_sources[0x4f]	50912	1			T1	2		T2	411		T5	3
valid_sources[0x50]	49008	1			T1	1		T2	365		T3	4
valid_sources[0x51]	57713	1			T1	1		T2	295		T5	3
valid_sources[0x52]	51534	1			T1	471		T2	448		T3	2
valid_sources[0x53]	50591	1			T2	467		T4	1		T5	1
valid_sources[0x54]	53682	1			T1	2		T2	453		T3	3
valid_sources[0x55]	48735	1			T2	404		T5	2		T7	141
valid_sources[0x56]	50279	1			T1	842		T2	536		T5	10
valid_sources[0x57]	51140	1			T2	307		T3	2		T5	3
valid_sources[0x58]	53704	1			T1	5		T2	410		T3	2
valid_sources[0x59]	51648	1			T1	1		T2	454		T3	4
valid_sources[0x5a]	52760	1			T1	35		T2	447		T3	5
valid_sources[0x5b]	50285	1			T2	324		T3	4		T5	11
valid_sources[0x5c]	53105	1			T2	435		T3	1		T5	2
valid_sources[0x5d]	51794	1			T1	1		T2	417		T3	1
valid_sources[0x5e]	49598	1			T1	7		T2	398		T5	8
valid_sources[0x5f]	51991	1			T1	1		T2	431		T3	1
valid_sources[0x60]	54370	1			T1	2		T2	402		T3	1
valid_sources[0x61]	51426	1			T2	460		T3	3		T5	4
valid_sources[0x62]	51883	1			T1	1		T2	413		T3	7
valid_sources[0x63]	50843	1			T1	1		T2	435		T4	1
valid_sources[0x64]	51614	1			T1	4		T2	390		T3	1
valid_sources[0x65]	52484	1			T1	34		T2	402		T3	3
valid_sources[0x66]	50890	1			T1	5		T2	454		T3	2
valid_sources[0x67]	56817	1			T1	3		T2	381		T3	1
valid_sources[0x68]	49353	1			T1	4		T2	447		T3	3
valid_sources[0x69]	54699	1			T2	545		T3	1		T5	4
valid_sources[0x6a]	51477	1			T1	1		T2	371		T3	2
valid_sources[0x6b]	52221	1			T1	1		T2	485		T3	4
valid_sources[0x6c]	51301	1			T2	376		T3	1		T6	1
valid_sources[0x6d]	50868	1			T1	58		T2	392		T3	1
valid_sources[0x6e]	50508	1			T1	617		T2	452		T3	1
valid_sources[0x6f]	52609	1			T2	495		T3	1		T6	5
valid_sources[0x70]	49356	1			T1	2		T2	391		T3	3
valid_sources[0x71]	52273	1			T1	4		T2	479		T3	1
valid_sources[0x72]	49814	1			T1	2		T2	352		T3	2
valid_sources[0x73]	54117	1			T1	95		T2	358		T3	1
valid_sources[0x74]	52555	1			T1	1		T2	413		T6	18
valid_sources[0x75]	53780	1			T1	46		T2	460		T3	1
valid_sources[0x76]	53782	1			T1	1		T2	406		T3	3
valid_sources[0x77]	51174	1			T1	1		T2	478		T3	1
valid_sources[0x78]	51943	1			T1	2		T2	362		T3	2
valid_sources[0x79]	51066	1			T1	2		T2	444		T3	2
valid_sources[0x7a]	56048	1			T2	335		T3	1		T5	5
valid_sources[0x7b]	53654	1			T1	321		T2	485		T3	4
valid_sources[0x7c]	50297	1			T1	1		T2	390		T3	2
valid_sources[0x7d]	50174	1			T1	232		T2	368		T3	1
valid_sources[0x7e]	50869	1			T1	2		T2	356		T3	5
valid_sources[0x7f]	53319	1			T1	853		T2	419		T3	1
valid_sources[0x80]	52949	1			T1	27		T2	470		T3	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2551952

1

T1

4755

T2

18615

T3

1

values[0x0]

all_enables

biggest_size

2140036

1

T1

4005

T2

11980

T3

202

values[0x1]

all_enables

biggest_size

2108831

1

T1

3892

T2

11856

T3

230