Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

6509912

1

T1

4237

T2

63542

T3

97

full_word

6801907

1

T1

12652

T2

42451

T3

433

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	13311369	1			T1	16889		T2	105993		T3	530
auto[TlIntgErrCmd]	147	1			T65	10		T67	5		T103	9
auto[TlIntgErrData]	165	1			T65	4		T67	12		T103	11
auto[TlIntgErrBoth]	138	1			T65	6		T67	3		T103	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8553321

1

T1

8953

T2

77596

T3

1

auto[1]

4758498

1

T1

7936

T2

28397

T3

529

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6000933	1			T1	4198		T2	58981		T4	69
auto[TlIntgErrNone]	partial	auto[1]	508563	1			T1	39		T2	4561		T3	97
auto[TlIntgErrNone]	full_word	auto[0]	2552194	1			T1	4755		T2	18615		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	4249679	1			T1	7897		T2	23836		T3	432
auto[TlIntgErrCmd]	partial	auto[0]	51	1			T65	4		T67	2		T103	3
auto[TlIntgErrCmd]	partial	auto[1]	83	1			T65	3		T67	3		T103	6
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T149	2		T245	1		T246	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T65	3		T119	1		T247	1
auto[TlIntgErrData]	partial	auto[0]	77	1			T65	1		T67	7		T103	5
auto[TlIntgErrData]	partial	auto[1]	76	1			T65	2		T67	3		T103	6
auto[TlIntgErrData]	full_word	auto[0]	6	1			T67	1		T119	2		T152	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T65	1		T67	1		T248	1
auto[TlIntgErrBoth]	partial	auto[0]	52	1			T65	1		T67	2		T103	8
auto[TlIntgErrBoth]	partial	auto[1]	77	1			T65	4		T67	1		T103	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T103	1		T249	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T65	1		T120	1		T119	1