Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.fifo_h.reqfifo

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	579622571	15764911	0	0
DepthKnown_A	579622571	579489704	0	0
RvalidKnown_A	579622571	579489704	0	0
WreadyKnown_A	579622571	579489704	0	0
gen_passthru_fifo.paramCheckPass	1092	1092	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579622571	15764911	0	0
T1	812839	22653	0	0
T2	399596	117716	0	0
T3	97472	530	0	0
T4	1031	69	0	0
T5	16839	1733	0	0
T6	95809	895	0	0
T7	265900	38118	0	0
T8	730117	920	0	0
T9	33683	1745	0	0
T10	669460	1725	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579622571	579489704	0	0
T1	812839	812784	0	0
T2	399596	399589	0	0
T3	97472	97411	0	0
T4	1031	980	0	0
T5	16839	16779	0	0
T6	95809	95713	0	0
T7	265900	265894	0	0
T8	730117	730028	0	0
T9	33683	33586	0	0
T10	669460	669368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579622571	579489704	0	0
T1	812839	812784	0	0
T2	399596	399589	0	0
T3	97472	97411	0	0
T4	1031	980	0	0
T5	16839	16779	0	0
T6	95809	95713	0	0
T7	265900	265894	0	0
T8	730117	730028	0	0
T9	33683	33586	0	0
T10	669460	669368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579622571	579489704	0	0
T1	812839	812784	0	0
T2	399596	399589	0	0
T3	97472	97411	0	0
T4	1031	980	0	0
T5	16839	16779	0	0
T6	95809	95713	0	0
T7	265900	265894	0	0
T8	730117	730028	0	0
T9	33683	33586	0	0
T10	669460	669368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1092	1092	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	579622571	31951532	0	0
DepthKnown_A	579622571	579489704	0	0
RvalidKnown_A	579622571	579489704	0	0
WreadyKnown_A	579622571	579489704	0	0
gen_passthru_fifo.paramCheckPass	1092	1092	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579622571	31951532	0	0
T1	812839	57049	0	0
T2	399596	324781	0	0
T3	97472	530	0	0
T4	1031	69	0	0
T5	16839	1056	0	0
T6	95809	895	0	0
T7	265900	34735	0	0
T8	730117	920	0	0
T9	33683	1016	0	0
T10	669460	894	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579622571	579489704	0	0
T1	812839	812784	0	0
T2	399596	399589	0	0
T3	97472	97411	0	0
T4	1031	980	0	0
T5	16839	16779	0	0
T6	95809	95713	0	0
T7	265900	265894	0	0
T8	730117	730028	0	0
T9	33683	33586	0	0
T10	669460	669368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579622571	579489704	0	0
T1	812839	812784	0	0
T2	399596	399589	0	0
T3	97472	97411	0	0
T4	1031	980	0	0
T5	16839	16779	0	0
T6	95809	95713	0	0
T7	265900	265894	0	0
T8	730117	730028	0	0
T9	33683	33586	0	0
T10	669460	669368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579622571	579489704	0	0
T1	812839	812784	0	0
T2	399596	399589	0	0
T3	97472	97411	0	0
T4	1031	980	0	0
T5	16839	16779	0	0
T6	95809	95713	0	0
T7	265900	265894	0	0
T8	730117	730028	0	0
T9	33683	33586	0	0
T10	669460	669368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1092	1092	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	579622571	3564134	0	0
DepthKnown_A	579622571	579489704	0	0
RvalidKnown_A	579622571	579489704	0	0
WreadyKnown_A	579622571	579489704	0	0
gen_passthru_fifo.paramCheckPass	1092	1092	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579622571	3564134	0	0
T1	812839	12497	0	0
T2	399596	7487	0	0
T3	97472	0	0	0
T4	1031	0	0	0
T5	16839	1667	0	0
T6	95809	832	0	0
T7	265900	9980	0	0
T8	730117	832	0	0
T9	33683	1663	0	0
T10	669460	1663	0	0
T11	0	1663	0	0
T12	0	1668	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579622571	579489704	0	0
T1	812839	812784	0	0
T2	399596	399589	0	0
T3	97472	97411	0	0
T4	1031	980	0	0
T5	16839	16779	0	0
T6	95809	95713	0	0
T7	265900	265894	0	0
T8	730117	730028	0	0
T9	33683	33586	0	0
T10	669460	669368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579622571	579489704	0	0
T1	812839	812784	0	0
T2	399596	399589	0	0
T3	97472	97411	0	0
T4	1031	980	0	0
T5	16839	16779	0	0
T6	95809	95713	0	0
T7	265900	265894	0	0
T8	730117	730028	0	0
T9	33683	33586	0	0
T10	669460	669368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579622571	579489704	0	0
T1	812839	812784	0	0
T2	399596	399589	0	0
T3	97472	97411	0	0
T4	1031	980	0	0
T5	16839	16779	0	0
T6	95809	95713	0	0
T7	265900	265894	0	0
T8	730117	730028	0	0
T9	33683	33586	0	0
T10	669460	669368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1092	1092	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	579622571	4108081	0	0
DepthKnown_A	579622571	579489704	0	0
RvalidKnown_A	579622571	579489704	0	0
WreadyKnown_A	579622571	579489704	0	0
gen_passthru_fifo.paramCheckPass	1092	1092	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579622571	4108081	0	0
T1	812839	15962	0	0
T2	399596	10626	0	0
T3	97472	0	0	0
T4	1031	0	0	0
T5	16839	837	0	0
T6	95809	832	0	0
T7	265900	6656	0	0
T8	730117	832	0	0
T9	33683	832	0	0
T10	669460	832	0	0
T11	0	832	0	0
T12	0	837	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579622571	579489704	0	0
T1	812839	812784	0	0
T2	399596	399589	0	0
T3	97472	97411	0	0
T4	1031	980	0	0
T5	16839	16779	0	0
T6	95809	95713	0	0
T7	265900	265894	0	0
T8	730117	730028	0	0
T9	33683	33586	0	0
T10	669460	669368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579622571	579489704	0	0
T1	812839	812784	0	0
T2	399596	399589	0	0
T3	97472	97411	0	0
T4	1031	980	0	0
T5	16839	16779	0	0
T6	95809	95713	0	0
T7	265900	265894	0	0
T8	730117	730028	0	0
T9	33683	33586	0	0
T10	669460	669368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579622571	579489704	0	0
T1	812839	812784	0	0
T2	399596	399589	0	0
T3	97472	97411	0	0
T4	1031	980	0	0
T5	16839	16779	0	0
T6	95809	95713	0	0
T7	265900	265894	0	0
T8	730117	730028	0	0
T9	33683	33586	0	0
T10	669460	669368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1092	1092	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	579622571	213654	0	0
DepthKnown_A	579622571	579489704	0	0
RvalidKnown_A	579622571	579489704	0	0
WreadyKnown_A	579622571	579489704	0	0
gen_passthru_fifo.paramCheckPass	1092	1092	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579622571	213654	0	0
T1	812839	577	0	0
T2	399596	1190	0	0
T3	97472	0	0	0
T4	1031	0	0	0
T5	16839	0	0	0
T6	95809	0	0	0
T7	265900	236	0	0
T8	730117	0	0	0
T9	33683	0	0	0
T10	669460	0	0	0
T13	0	250	0	0
T15	0	450	0	0
T18	0	36	0	0
T23	0	514	0	0
T24	0	57	0	0
T25	0	875	0	0
T26	0	258	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579622571	579489704	0	0
T1	812839	812784	0	0
T2	399596	399589	0	0
T3	97472	97411	0	0
T4	1031	980	0	0
T5	16839	16779	0	0
T6	95809	95713	0	0
T7	265900	265894	0	0
T8	730117	730028	0	0
T9	33683	33586	0	0
T10	669460	669368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579622571	579489704	0	0
T1	812839	812784	0	0
T2	399596	399589	0	0
T3	97472	97411	0	0
T4	1031	980	0	0
T5	16839	16779	0	0
T6	95809	95713	0	0
T7	265900	265894	0	0
T8	730117	730028	0	0
T9	33683	33586	0	0
T10	669460	669368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579622571	579489704	0	0
T1	812839	812784	0	0
T2	399596	399589	0	0
T3	97472	97411	0	0
T4	1031	980	0	0
T5	16839	16779	0	0
T6	95809	95713	0	0
T7	265900	265894	0	0
T8	730117	730028	0	0
T9	33683	33586	0	0
T10	669460	669368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1092	1092	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	579622571	551218	0	0
DepthKnown_A	579622571	579489704	0	0
RvalidKnown_A	579622571	579489704	0	0
WreadyKnown_A	579622571	579489704	0	0
gen_passthru_fifo.paramCheckPass	1092	1092	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579622571	551218	0	0
T1	812839	2583	0	0
T2	399596	3845	0	0
T3	97472	0	0	0
T4	1031	0	0	0
T5	16839	0	0	0
T6	95809	0	0	0
T7	265900	236	0	0
T8	730117	0	0	0
T9	33683	0	0	0
T10	669460	0	0	0
T13	0	1118	0	0
T15	0	450	0	0
T18	0	36	0	0
T23	0	514	0	0
T24	0	57	0	0
T25	0	2788	0	0
T26	0	1118	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579622571	579489704	0	0
T1	812839	812784	0	0
T2	399596	399589	0	0
T3	97472	97411	0	0
T4	1031	980	0	0
T5	16839	16779	0	0
T6	95809	95713	0	0
T7	265900	265894	0	0
T8	730117	730028	0	0
T9	33683	33586	0	0
T10	669460	669368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579622571	579489704	0	0
T1	812839	812784	0	0
T2	399596	399589	0	0
T3	97472	97411	0	0
T4	1031	980	0	0
T5	16839	16779	0	0
T6	95809	95713	0	0
T7	265900	265894	0	0
T8	730117	730028	0	0
T9	33683	33586	0	0
T10	669460	669368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579622571	579489704	0	0
T1	812839	812784	0	0
T2	399596	399589	0	0
T3	97472	97411	0	0
T4	1031	980	0	0
T5	16839	16779	0	0
T6	95809	95713	0	0
T7	265900	265894	0	0
T8	730117	730028	0	0
T9	33683	33586	0	0
T10	669460	669368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1092	1092	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0