Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	579622571	11590351	0	0
DepthKnown_A	579622571	579489704	0	0
RvalidKnown_A	579622571	579489704	0	0
WreadyKnown_A	579622571	579489704	0	0
gen_passthru_fifo.paramCheckPass	1092	1092	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579622571	11590351	0	0
T1	812839	8963	0	0
T2	399596	107418	0	0
T3	97472	530	0	0
T4	1031	69	0	0
T5	16839	66	0	0
T6	95809	63	0	0
T7	265900	27850	0	0
T8	730117	88	0	0
T9	33683	82	0	0
T10	669460	62	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579622571	579489704	0	0
T1	812839	812784	0	0
T2	399596	399589	0	0
T3	97472	97411	0	0
T4	1031	980	0	0
T5	16839	16779	0	0
T6	95809	95713	0	0
T7	265900	265894	0	0
T8	730117	730028	0	0
T9	33683	33586	0	0
T10	669460	669368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579622571	579489704	0	0
T1	812839	812784	0	0
T2	399596	399589	0	0
T3	97472	97411	0	0
T4	1031	980	0	0
T5	16839	16779	0	0
T6	95809	95713	0	0
T7	265900	265894	0	0
T8	730117	730028	0	0
T9	33683	33586	0	0
T10	669460	669368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579622571	579489704	0	0
T1	812839	812784	0	0
T2	399596	399589	0	0
T3	97472	97411	0	0
T4	1031	980	0	0
T5	16839	16779	0	0
T6	95809	95713	0	0
T7	265900	265894	0	0
T8	730117	730028	0	0
T9	33683	33586	0	0
T10	669460	669368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1092	1092	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	579622571	27292233	0	0
DepthKnown_A	579622571	579489704	0	0
RvalidKnown_A	579622571	579489704	0	0
WreadyKnown_A	579622571	579489704	0	0
gen_passthru_fifo.paramCheckPass	1092	1092	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579622571	27292233	0	0
T1	812839	38504	0	0
T2	399596	310310	0	0
T3	97472	530	0	0
T4	1031	69	0	0
T5	16839	219	0	0
T6	95809	63	0	0
T7	265900	27843	0	0
T8	730117	88	0	0
T9	33683	184	0	0
T10	669460	62	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579622571	579489704	0	0
T1	812839	812784	0	0
T2	399596	399589	0	0
T3	97472	97411	0	0
T4	1031	980	0	0
T5	16839	16779	0	0
T6	95809	95713	0	0
T7	265900	265894	0	0
T8	730117	730028	0	0
T9	33683	33586	0	0
T10	669460	669368	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579622571	579489704	0	0
T1	812839	812784	0	0
T2	399596	399589	0	0
T3	97472	97411	0	0
T4	1031	980	0	0
T5	16839	16779	0	0
T6	95809	95713	0	0
T7	265900	265894	0	0
T8	730117	730028	0	0
T9	33683	33586	0	0
T10	669460	669368	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579622571	579489704	0	0
T1	812839	812784	0	0
T2	399596	399589	0	0
T3	97472	97411	0	0
T4	1031	980	0	0
T5	16839	16779	0	0
T6	95809	95713	0	0
T7	265900	265894	0	0
T8	730117	730028	0	0
T9	33683	33586	0	0
T10	669460	669368	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1092	1092	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0