Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T13,T15
1	0	Covered	T2,T13,T15

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T13
1	0	Unreachable
1	1	Covered	T2,T13,T15

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	947446644	760484109	0	0
CheckNGreaterZero_A	2751	2751	0	0
GntImpliesReady_A	947446644	4369016	0	0
GntImpliesValid_A	947446644	4369016	0	0
GrantKnown_A	947446644	760484109	0	0
IdxKnown_A	947446644	760484109	0	0
IndexIsCorrect_A	947446644	4369016	0	0
LockArbDecision_A	947446644	0	0	0
NoReadyValidNoGrant_A	947446644	0	0	0
ReadyAndValidImplyGrant_A	947446644	4369016	0	0
ReqAndReadyImplyGrant_A	947446644	4369016	0	0
ReqImpliesValid_A	947446644	4369016	0	0
ReqStaysHighUntilGranted0_M	947446644	0	0	0
RoundRobin_A	947446644	6	0	917
ValidKnown_A	947446644	760484109	0	0
gen_data_port_assertion.DataFlow_A	947446644	4369016	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	947446644	760484109	0	0
T1	1555112	1554005	0	0
T2	1406768	895477	0	0
T3	302984	196026	0	0
T4	1031	980	0	0
T5	43927	30323	0	0
T6	281937	188759	0	0
T7	1014284	637762	0	0
T8	910157	819112	0	0
T9	63775	48632	0	0
T10	935988	802632	0	0
T11	13536	6768	0	0
T12	86078	0	0	0
T13	0	24048	0	0
T14	0	216	0	0
T15	0	50768	0	0
T16	0	123968	0	0
T18	0	3880	0	0
T24	0	3800	0	0
T39	0	74656	0	0
T40	0	1080	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2751	2751	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	947446644	4369016	0	0
T1	1555112	12063	0	0
T2	1406768	17797	0	0
T3	302984	0	0	0
T4	1031	0	0	0
T5	43927	832	0	0
T6	281937	832	0	0
T7	1014284	8608	0	0
T8	910157	832	0	0
T9	63775	832	0	0
T10	935988	832	0	0
T11	13536	832	0	0
T12	86078	832	0	0
T13	0	1484	0	0
T15	0	2402	0	0
T18	0	213	0	0
T23	0	7030	0	0
T24	0	260	0	0
T25	0	6391	0	0
T26	0	1906	0	0
T41	0	2121	0	0
T42	0	3833	0	0
T43	0	3690	0	0
T44	0	2634	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	947446644	4369016	0	0
T1	1555112	12063	0	0
T2	1406768	17797	0	0
T3	302984	0	0	0
T4	1031	0	0	0
T5	43927	832	0	0
T6	281937	832	0	0
T7	1014284	8608	0	0
T8	910157	832	0	0
T9	63775	832	0	0
T10	935988	832	0	0
T11	13536	832	0	0
T12	86078	832	0	0
T13	0	1484	0	0
T15	0	2402	0	0
T18	0	213	0	0
T23	0	7030	0	0
T24	0	260	0	0
T25	0	6391	0	0
T26	0	1906	0	0
T41	0	2121	0	0
T42	0	3833	0	0
T43	0	3690	0	0
T44	0	2634	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	947446644	760484109	0	0
T1	1555112	1554005	0	0
T2	1406768	895477	0	0
T3	302984	196026	0	0
T4	1031	980	0	0
T5	43927	30323	0	0
T6	281937	188759	0	0
T7	1014284	637762	0	0
T8	910157	819112	0	0
T9	63775	48632	0	0
T10	935988	802632	0	0
T11	13536	6768	0	0
T12	86078	0	0	0
T13	0	24048	0	0
T14	0	216	0	0
T15	0	50768	0	0
T16	0	123968	0	0
T18	0	3880	0	0
T24	0	3800	0	0
T39	0	74656	0	0
T40	0	1080	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	947446644	760484109	0	0
T1	1555112	1554005	0	0
T2	1406768	895477	0	0
T3	302984	196026	0	0
T4	1031	980	0	0
T5	43927	30323	0	0
T6	281937	188759	0	0
T7	1014284	637762	0	0
T8	910157	819112	0	0
T9	63775	48632	0	0
T10	935988	802632	0	0
T11	13536	6768	0	0
T12	86078	0	0	0
T13	0	24048	0	0
T14	0	216	0	0
T15	0	50768	0	0
T16	0	123968	0	0
T18	0	3880	0	0
T24	0	3800	0	0
T39	0	74656	0	0
T40	0	1080	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	947446644	4369016	0	0
T1	1555112	12063	0	0
T2	1406768	17797	0	0
T3	302984	0	0	0
T4	1031	0	0	0
T5	43927	832	0	0
T6	281937	832	0	0
T7	1014284	8608	0	0
T8	910157	832	0	0
T9	63775	832	0	0
T10	935988	832	0	0
T11	13536	832	0	0
T12	86078	832	0	0
T13	0	1484	0	0
T15	0	2402	0	0
T18	0	213	0	0
T23	0	7030	0	0
T24	0	260	0	0
T25	0	6391	0	0
T26	0	1906	0	0
T41	0	2121	0	0
T42	0	3833	0	0
T43	0	3690	0	0
T44	0	2634	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	947446644	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	947446644	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	947446644	4369016	0	0
T1	1555112	12063	0	0
T2	1406768	17797	0	0
T3	302984	0	0	0
T4	1031	0	0	0
T5	43927	832	0	0
T6	281937	832	0	0
T7	1014284	8608	0	0
T8	910157	832	0	0
T9	63775	832	0	0
T10	935988	832	0	0
T11	13536	832	0	0
T12	86078	832	0	0
T13	0	1484	0	0
T15	0	2402	0	0
T18	0	213	0	0
T23	0	7030	0	0
T24	0	260	0	0
T25	0	6391	0	0
T26	0	1906	0	0
T41	0	2121	0	0
T42	0	3833	0	0
T43	0	3690	0	0
T44	0	2634	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	947446644	4369016	0	0
T1	1555112	12063	0	0
T2	1406768	17797	0	0
T3	302984	0	0	0
T4	1031	0	0	0
T5	43927	832	0	0
T6	281937	832	0	0
T7	1014284	8608	0	0
T8	910157	832	0	0
T9	63775	832	0	0
T10	935988	832	0	0
T11	13536	832	0	0
T12	86078	832	0	0
T13	0	1484	0	0
T15	0	2402	0	0
T18	0	213	0	0
T23	0	7030	0	0
T24	0	260	0	0
T25	0	6391	0	0
T26	0	1906	0	0
T41	0	2121	0	0
T42	0	3833	0	0
T43	0	3690	0	0
T44	0	2634	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	947446644	4369016	0	0
T1	1555112	12063	0	0
T2	1406768	17797	0	0
T3	302984	0	0	0
T4	1031	0	0	0
T5	43927	832	0	0
T6	281937	832	0	0
T7	1014284	8608	0	0
T8	910157	832	0	0
T9	63775	832	0	0
T10	935988	832	0	0
T11	13536	832	0	0
T12	86078	832	0	0
T13	0	1484	0	0
T15	0	2402	0	0
T18	0	213	0	0
T23	0	7030	0	0
T24	0	260	0	0
T25	0	6391	0	0
T26	0	1906	0	0
T41	0	2121	0	0
T42	0	3833	0	0
T43	0	3690	0	0
T44	0	2634	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	947446644	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	947446644	6	0	917
T45	411409	1	0	1
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	452381	0	0	1
T52	679956	0	0	1
T53	366286	0	0	1
T54	6259	0	0	1
T55	102322	0	0	1
T56	125277	0	0	1
T57	11862	0	0	1
T58	57846	0	0	1
T59	1734	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	947446644	760484109	0	0
T1	1555112	1554005	0	0
T2	1406768	895477	0	0
T3	302984	196026	0	0
T4	1031	980	0	0
T5	43927	30323	0	0
T6	281937	188759	0	0
T7	1014284	637762	0	0
T8	910157	819112	0	0
T9	63775	48632	0	0
T10	935988	802632	0	0
T11	13536	6768	0	0
T12	86078	0	0	0
T13	0	24048	0	0
T14	0	216	0	0
T15	0	50768	0	0
T16	0	123968	0	0
T18	0	3880	0	0
T24	0	3800	0	0
T39	0	74656	0	0
T40	0	1080	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	947446644	4369016	0	0
T1	1555112	12063	0	0
T2	1406768	17797	0	0
T3	302984	0	0	0
T4	1031	0	0	0
T5	43927	832	0	0
T6	281937	832	0	0
T7	1014284	8608	0	0
T8	910157	832	0	0
T9	63775	832	0	0
T10	935988	832	0	0
T11	13536	832	0	0
T12	86078	832	0	0
T13	0	1484	0	0
T15	0	2402	0	0
T18	0	213	0	0
T23	0	7030	0	0
T24	0	260	0	0
T25	0	6391	0	0
T26	0	1906	0	0
T41	0	2121	0	0
T42	0	3833	0	0
T43	0	3690	0	0
T44	0	2634	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T13,T15
1	0	Covered	T2,T13,T15

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T13
1	0	Unreachable
1	1	Covered	T2,T13,T15

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T13,T15
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T13

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T13,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T13,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	185051749	36596602	0	0
CheckNGreaterZero_A	917	917	0	0
GntImpliesReady_A	185051749	870194	0	0
GntImpliesValid_A	185051749	870194	0	0
GrantKnown_A	185051749	36596602	0	0
IdxKnown_A	185051749	36596602	0	0
IndexIsCorrect_A	185051749	870194	0	0
LockArbDecision_A	185051749	0	0	0
NoReadyValidNoGrant_A	185051749	0	0	0
ReadyAndValidImplyGrant_A	185051749	870194	0	0
ReqAndReadyImplyGrant_A	185051749	870194	0	0
ReqImpliesValid_A	185051749	870194	0	0
ReqStaysHighUntilGranted0_M	185051749	0	0	0
RoundRobin_A	185051749	0	0	0
ValidKnown_A	185051749	36596602	0	0
gen_data_port_assertion.DataFlow_A	185051749	870194	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185051749	36596602	0	0
T2	503586	109171	0	0
T3	102756	98608	0	0
T5	13544	0	0	0
T6	93064	0	0	0
T7	374192	0	0	0
T8	90020	0	0	0
T9	15046	0	0	0
T10	133264	0	0	0
T11	6768	0	0	0
T12	86078	0	0	0
T13	0	24048	0	0
T14	0	216	0	0
T15	0	50768	0	0
T16	0	123968	0	0
T18	0	3880	0	0
T24	0	3800	0	0
T39	0	74656	0	0
T40	0	1080	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	917	917	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185051749	870194	0	0
T2	503586	5259	0	0
T3	102756	0	0	0
T5	13544	0	0	0
T6	93064	0	0	0
T7	374192	0	0	0
T8	90020	0	0	0
T9	15046	0	0	0
T10	133264	0	0	0
T11	6768	0	0	0
T12	86078	0	0	0
T13	0	698	0	0
T15	0	2402	0	0
T18	0	213	0	0
T24	0	260	0	0
T25	0	4226	0	0
T41	0	2121	0	0
T42	0	610	0	0
T43	0	924	0	0
T44	0	2634	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185051749	870194	0	0
T2	503586	5259	0	0
T3	102756	0	0	0
T5	13544	0	0	0
T6	93064	0	0	0
T7	374192	0	0	0
T8	90020	0	0	0
T9	15046	0	0	0
T10	133264	0	0	0
T11	6768	0	0	0
T12	86078	0	0	0
T13	0	698	0	0
T15	0	2402	0	0
T18	0	213	0	0
T24	0	260	0	0
T25	0	4226	0	0
T41	0	2121	0	0
T42	0	610	0	0
T43	0	924	0	0
T44	0	2634	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185051749	36596602	0	0
T2	503586	109171	0	0
T3	102756	98608	0	0
T5	13544	0	0	0
T6	93064	0	0	0
T7	374192	0	0	0
T8	90020	0	0	0
T9	15046	0	0	0
T10	133264	0	0	0
T11	6768	0	0	0
T12	86078	0	0	0
T13	0	24048	0	0
T14	0	216	0	0
T15	0	50768	0	0
T16	0	123968	0	0
T18	0	3880	0	0
T24	0	3800	0	0
T39	0	74656	0	0
T40	0	1080	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185051749	36596602	0	0
T2	503586	109171	0	0
T3	102756	98608	0	0
T5	13544	0	0	0
T6	93064	0	0	0
T7	374192	0	0	0
T8	90020	0	0	0
T9	15046	0	0	0
T10	133264	0	0	0
T11	6768	0	0	0
T12	86078	0	0	0
T13	0	24048	0	0
T14	0	216	0	0
T15	0	50768	0	0
T16	0	123968	0	0
T18	0	3880	0	0
T24	0	3800	0	0
T39	0	74656	0	0
T40	0	1080	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185051749	870194	0	0
T2	503586	5259	0	0
T3	102756	0	0	0
T5	13544	0	0	0
T6	93064	0	0	0
T7	374192	0	0	0
T8	90020	0	0	0
T9	15046	0	0	0
T10	133264	0	0	0
T11	6768	0	0	0
T12	86078	0	0	0
T13	0	698	0	0
T15	0	2402	0	0
T18	0	213	0	0
T24	0	260	0	0
T25	0	4226	0	0
T41	0	2121	0	0
T42	0	610	0	0
T43	0	924	0	0
T44	0	2634	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185051749	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185051749	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185051749	870194	0	0
T2	503586	5259	0	0
T3	102756	0	0	0
T5	13544	0	0	0
T6	93064	0	0	0
T7	374192	0	0	0
T8	90020	0	0	0
T9	15046	0	0	0
T10	133264	0	0	0
T11	6768	0	0	0
T12	86078	0	0	0
T13	0	698	0	0
T15	0	2402	0	0
T18	0	213	0	0
T24	0	260	0	0
T25	0	4226	0	0
T41	0	2121	0	0
T42	0	610	0	0
T43	0	924	0	0
T44	0	2634	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185051749	870194	0	0
T2	503586	5259	0	0
T3	102756	0	0	0
T5	13544	0	0	0
T6	93064	0	0	0
T7	374192	0	0	0
T8	90020	0	0	0
T9	15046	0	0	0
T10	133264	0	0	0
T11	6768	0	0	0
T12	86078	0	0	0
T13	0	698	0	0
T15	0	2402	0	0
T18	0	213	0	0
T24	0	260	0	0
T25	0	4226	0	0
T41	0	2121	0	0
T42	0	610	0	0
T43	0	924	0	0
T44	0	2634	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185051749	870194	0	0
T2	503586	5259	0	0
T3	102756	0	0	0
T5	13544	0	0	0
T6	93064	0	0	0
T7	374192	0	0	0
T8	90020	0	0	0
T9	15046	0	0	0
T10	133264	0	0	0
T11	6768	0	0	0
T12	86078	0	0	0
T13	0	698	0	0
T15	0	2402	0	0
T18	0	213	0	0
T24	0	260	0	0
T25	0	4226	0	0
T41	0	2121	0	0
T42	0	610	0	0
T43	0	924	0	0
T44	0	2634	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	185051749	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185051749	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185051749	36596602	0	0
T2	503586	109171	0	0
T3	102756	98608	0	0
T5	13544	0	0	0
T6	93064	0	0	0
T7	374192	0	0	0
T8	90020	0	0	0
T9	15046	0	0	0
T10	133264	0	0	0
T11	6768	0	0	0
T12	86078	0	0	0
T13	0	24048	0	0
T14	0	216	0	0
T15	0	50768	0	0
T16	0	123968	0	0
T18	0	3880	0	0
T24	0	3800	0	0
T39	0	74656	0	0
T40	0	1080	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185051749	870194	0	0
T2	503586	5259	0	0
T3	102756	0	0	0
T5	13544	0	0	0
T6	93064	0	0	0
T7	374192	0	0	0
T8	90020	0	0	0
T9	15046	0	0	0
T10	133264	0	0	0
T11	6768	0	0	0
T12	86078	0	0	0
T13	0	698	0	0
T15	0	2402	0	0
T18	0	213	0	0
T24	0	260	0	0
T25	0	4226	0	0
T41	0	2121	0	0
T42	0	610	0	0
T43	0	924	0	0
T44	0	2634	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	185051749	146629619	0	0
CheckNGreaterZero_A	917	917	0	0
GntImpliesReady_A	185051749	702056	0	0
GntImpliesValid_A	185051749	702056	0	0
GrantKnown_A	185051749	146629619	0	0
IdxKnown_A	185051749	146629619	0	0
IndexIsCorrect_A	185051749	702056	0	0
LockArbDecision_A	185051749	0	0	0
NoReadyValidNoGrant_A	185051749	0	0	0
ReadyAndValidImplyGrant_A	185051749	702056	0	0
ReqAndReadyImplyGrant_A	185051749	702056	0	0
ReqImpliesValid_A	185051749	702056	0	0
ReqStaysHighUntilGranted0_M	185051749	0	0	0
RoundRobin_A	185051749	0	0	0
ValidKnown_A	185051749	146629619	0	0
gen_data_port_assertion.DataFlow_A	185051749	702056	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185051749	146629619	0	0
T1	742273	741221	0	0
T2	503586	386717	0	0
T3	102756	7	0	0
T5	13544	13544	0	0
T6	93064	93046	0	0
T7	374192	371868	0	0
T8	90020	89084	0	0
T9	15046	15046	0	0
T10	133264	133264	0	0
T11	6768	6768	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	917	917	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185051749	702056	0	0
T1	742273	3974	0	0
T2	503586	4747	0	0
T3	102756	0	0	0
T5	13544	0	0	0
T6	93064	0	0	0
T7	374192	1709	0	0
T8	90020	0	0	0
T9	15046	0	0	0
T10	133264	0	0	0
T11	6768	0	0	0
T13	0	786	0	0
T23	0	7030	0	0
T25	0	2165	0	0
T26	0	1906	0	0
T42	0	3223	0	0
T43	0	2766	0	0
T60	0	132	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185051749	702056	0	0
T1	742273	3974	0	0
T2	503586	4747	0	0
T3	102756	0	0	0
T5	13544	0	0	0
T6	93064	0	0	0
T7	374192	1709	0	0
T8	90020	0	0	0
T9	15046	0	0	0
T10	133264	0	0	0
T11	6768	0	0	0
T13	0	786	0	0
T23	0	7030	0	0
T25	0	2165	0	0
T26	0	1906	0	0
T42	0	3223	0	0
T43	0	2766	0	0
T60	0	132	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185051749	146629619	0	0
T1	742273	741221	0	0
T2	503586	386717	0	0
T3	102756	7	0	0
T5	13544	13544	0	0
T6	93064	93046	0	0
T7	374192	371868	0	0
T8	90020	89084	0	0
T9	15046	15046	0	0
T10	133264	133264	0	0
T11	6768	6768	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185051749	146629619	0	0
T1	742273	741221	0	0
T2	503586	386717	0	0
T3	102756	7	0	0
T5	13544	13544	0	0
T6	93064	93046	0	0
T7	374192	371868	0	0
T8	90020	89084	0	0
T9	15046	15046	0	0
T10	133264	133264	0	0
T11	6768	6768	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185051749	702056	0	0
T1	742273	3974	0	0
T2	503586	4747	0	0
T3	102756	0	0	0
T5	13544	0	0	0
T6	93064	0	0	0
T7	374192	1709	0	0
T8	90020	0	0	0
T9	15046	0	0	0
T10	133264	0	0	0
T11	6768	0	0	0
T13	0	786	0	0
T23	0	7030	0	0
T25	0	2165	0	0
T26	0	1906	0	0
T42	0	3223	0	0
T43	0	2766	0	0
T60	0	132	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185051749	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185051749	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185051749	702056	0	0
T1	742273	3974	0	0
T2	503586	4747	0	0
T3	102756	0	0	0
T5	13544	0	0	0
T6	93064	0	0	0
T7	374192	1709	0	0
T8	90020	0	0	0
T9	15046	0	0	0
T10	133264	0	0	0
T11	6768	0	0	0
T13	0	786	0	0
T23	0	7030	0	0
T25	0	2165	0	0
T26	0	1906	0	0
T42	0	3223	0	0
T43	0	2766	0	0
T60	0	132	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185051749	702056	0	0
T1	742273	3974	0	0
T2	503586	4747	0	0
T3	102756	0	0	0
T5	13544	0	0	0
T6	93064	0	0	0
T7	374192	1709	0	0
T8	90020	0	0	0
T9	15046	0	0	0
T10	133264	0	0	0
T11	6768	0	0	0
T13	0	786	0	0
T23	0	7030	0	0
T25	0	2165	0	0
T26	0	1906	0	0
T42	0	3223	0	0
T43	0	2766	0	0
T60	0	132	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185051749	702056	0	0
T1	742273	3974	0	0
T2	503586	4747	0	0
T3	102756	0	0	0
T5	13544	0	0	0
T6	93064	0	0	0
T7	374192	1709	0	0
T8	90020	0	0	0
T9	15046	0	0	0
T10	133264	0	0	0
T11	6768	0	0	0
T13	0	786	0	0
T23	0	7030	0	0
T25	0	2165	0	0
T26	0	1906	0	0
T42	0	3223	0	0
T43	0	2766	0	0
T60	0	132	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	185051749	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185051749	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185051749	146629619	0	0
T1	742273	741221	0	0
T2	503586	386717	0	0
T3	102756	7	0	0
T5	13544	13544	0	0
T6	93064	93046	0	0
T7	374192	371868	0	0
T8	90020	89084	0	0
T9	15046	15046	0	0
T10	133264	133264	0	0
T11	6768	6768	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185051749	702056	0	0
T1	742273	3974	0	0
T2	503586	4747	0	0
T3	102756	0	0	0
T5	13544	0	0	0
T6	93064	0	0	0
T7	374192	1709	0	0
T8	90020	0	0	0
T9	15046	0	0	0
T10	133264	0	0	0
T11	6768	0	0	0
T13	0	786	0	0
T23	0	7030	0	0
T25	0	2165	0	0
T26	0	1906	0	0
T42	0	3223	0	0
T43	0	2766	0	0
T60	0	132	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	577343146	577257888	0	0
CheckNGreaterZero_A	917	917	0	0
GntImpliesReady_A	577343146	2796766	0	0
GntImpliesValid_A	577343146	2796766	0	0
GrantKnown_A	577343146	577257888	0	0
IdxKnown_A	577343146	577257888	0	0
IndexIsCorrect_A	577343146	2796766	0	0
LockArbDecision_A	577343146	0	0	0
NoReadyValidNoGrant_A	577343146	0	0	0
ReadyAndValidImplyGrant_A	577343146	2796766	0	0
ReqAndReadyImplyGrant_A	577343146	2796766	0	0
ReqImpliesValid_A	577343146	2796766	0	0
ReqStaysHighUntilGranted0_M	577343146	0	0	0
RoundRobin_A	577343146	6	0	917
ValidKnown_A	577343146	577257888	0	0
gen_data_port_assertion.DataFlow_A	577343146	2796766	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577343146	577257888	0	0
T1	812839	812784	0	0
T2	399596	399589	0	0
T3	97472	97411	0	0
T4	1031	980	0	0
T5	16839	16779	0	0
T6	95809	95713	0	0
T7	265900	265894	0	0
T8	730117	730028	0	0
T9	33683	33586	0	0
T10	669460	669368	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	917	917	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577343146	2796766	0	0
T1	812839	8089	0	0
T2	399596	7791	0	0
T3	97472	0	0	0
T4	1031	0	0	0
T5	16839	832	0	0
T6	95809	832	0	0
T7	265900	6899	0	0
T8	730117	832	0	0
T9	33683	832	0	0
T10	669460	832	0	0
T11	0	832	0	0
T12	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577343146	2796766	0	0
T1	812839	8089	0	0
T2	399596	7791	0	0
T3	97472	0	0	0
T4	1031	0	0	0
T5	16839	832	0	0
T6	95809	832	0	0
T7	265900	6899	0	0
T8	730117	832	0	0
T9	33683	832	0	0
T10	669460	832	0	0
T11	0	832	0	0
T12	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577343146	577257888	0	0
T1	812839	812784	0	0
T2	399596	399589	0	0
T3	97472	97411	0	0
T4	1031	980	0	0
T5	16839	16779	0	0
T6	95809	95713	0	0
T7	265900	265894	0	0
T8	730117	730028	0	0
T9	33683	33586	0	0
T10	669460	669368	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577343146	577257888	0	0
T1	812839	812784	0	0
T2	399596	399589	0	0
T3	97472	97411	0	0
T4	1031	980	0	0
T5	16839	16779	0	0
T6	95809	95713	0	0
T7	265900	265894	0	0
T8	730117	730028	0	0
T9	33683	33586	0	0
T10	669460	669368	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577343146	2796766	0	0
T1	812839	8089	0	0
T2	399596	7791	0	0
T3	97472	0	0	0
T4	1031	0	0	0
T5	16839	832	0	0
T6	95809	832	0	0
T7	265900	6899	0	0
T8	730117	832	0	0
T9	33683	832	0	0
T10	669460	832	0	0
T11	0	832	0	0
T12	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577343146	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577343146	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577343146	2796766	0	0
T1	812839	8089	0	0
T2	399596	7791	0	0
T3	97472	0	0	0
T4	1031	0	0	0
T5	16839	832	0	0
T6	95809	832	0	0
T7	265900	6899	0	0
T8	730117	832	0	0
T9	33683	832	0	0
T10	669460	832	0	0
T11	0	832	0	0
T12	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577343146	2796766	0	0
T1	812839	8089	0	0
T2	399596	7791	0	0
T3	97472	0	0	0
T4	1031	0	0	0
T5	16839	832	0	0
T6	95809	832	0	0
T7	265900	6899	0	0
T8	730117	832	0	0
T9	33683	832	0	0
T10	669460	832	0	0
T11	0	832	0	0
T12	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577343146	2796766	0	0
T1	812839	8089	0	0
T2	399596	7791	0	0
T3	97472	0	0	0
T4	1031	0	0	0
T5	16839	832	0	0
T6	95809	832	0	0
T7	265900	6899	0	0
T8	730117	832	0	0
T9	33683	832	0	0
T10	669460	832	0	0
T11	0	832	0	0
T12	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	577343146	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577343146	6	0	917
T45	411409	1	0	1
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	452381	0	0	1
T52	679956	0	0	1
T53	366286	0	0	1
T54	6259	0	0	1
T55	102322	0	0	1
T56	125277	0	0	1
T57	11862	0	0	1
T58	57846	0	0	1
T59	1734	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577343146	577257888	0	0
T1	812839	812784	0	0
T2	399596	399589	0	0
T3	97472	97411	0	0
T4	1031	980	0	0
T5	16839	16779	0	0
T6	95809	95713	0	0
T7	265900	265894	0	0
T8	730117	730028	0	0
T9	33683	33586	0	0
T10	669460	669368	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577343146	2796766	0	0
T1	812839	8089	0	0
T2	399596	7791	0	0
T3	97472	0	0	0
T4	1031	0	0	0
T5	16839	832	0	0
T6	95809	832	0	0
T7	265900	6899	0	0
T8	730117	832	0	0
T9	33683	832	0	0
T10	669460	832	0	0
T11	0	832	0	0
T12	0	832	0	0