| T808 |
/workspace/coverage/default/49.spi_device_mailbox.96493237 |
|
|
Mar 19 01:19:54 PM PDT 24 |
Mar 19 01:20:11 PM PDT 24 |
17406860903 ps |
| T809 |
/workspace/coverage/default/41.spi_device_flash_all.26904583 |
|
|
Mar 19 01:19:01 PM PDT 24 |
Mar 19 01:21:37 PM PDT 24 |
99417707466 ps |
| T810 |
/workspace/coverage/default/6.spi_device_flash_mode.2660283473 |
|
|
Mar 19 01:14:04 PM PDT 24 |
Mar 19 01:14:58 PM PDT 24 |
11003638077 ps |
| T811 |
/workspace/coverage/default/14.spi_device_ram_cfg.1374419346 |
|
|
Mar 19 01:15:27 PM PDT 24 |
Mar 19 01:15:27 PM PDT 24 |
16465991 ps |
| T812 |
/workspace/coverage/default/17.spi_device_tpm_sts_read.2673482042 |
|
|
Mar 19 01:15:59 PM PDT 24 |
Mar 19 01:16:00 PM PDT 24 |
115789659 ps |
| T813 |
/workspace/coverage/default/7.spi_device_tpm_sts_read.3399293929 |
|
|
Mar 19 01:14:13 PM PDT 24 |
Mar 19 01:14:14 PM PDT 24 |
60800526 ps |
| T814 |
/workspace/coverage/default/16.spi_device_csb_read.1633086553 |
|
|
Mar 19 01:15:55 PM PDT 24 |
Mar 19 01:15:57 PM PDT 24 |
37306160 ps |
| T815 |
/workspace/coverage/default/42.spi_device_tpm_read_hw_reg.503977892 |
|
|
Mar 19 01:19:09 PM PDT 24 |
Mar 19 01:19:14 PM PDT 24 |
3603956495 ps |
| T816 |
/workspace/coverage/default/8.spi_device_flash_all.419444370 |
|
|
Mar 19 01:14:30 PM PDT 24 |
Mar 19 01:14:54 PM PDT 24 |
6927223169 ps |
| T817 |
/workspace/coverage/default/32.spi_device_tpm_sts_read.1853407641 |
|
|
Mar 19 01:18:00 PM PDT 24 |
Mar 19 01:18:01 PM PDT 24 |
121084691 ps |
| T818 |
/workspace/coverage/default/33.spi_device_mailbox.3888596789 |
|
|
Mar 19 01:18:05 PM PDT 24 |
Mar 19 01:18:15 PM PDT 24 |
5152308934 ps |
| T819 |
/workspace/coverage/default/19.spi_device_tpm_rw.3271572512 |
|
|
Mar 19 01:16:27 PM PDT 24 |
Mar 19 01:16:27 PM PDT 24 |
13283898 ps |
| T820 |
/workspace/coverage/default/30.spi_device_intercept.320937771 |
|
|
Mar 19 01:17:41 PM PDT 24 |
Mar 19 01:17:46 PM PDT 24 |
424687934 ps |
| T821 |
/workspace/coverage/default/16.spi_device_mailbox.1412140406 |
|
|
Mar 19 01:15:52 PM PDT 24 |
Mar 19 01:15:55 PM PDT 24 |
232408530 ps |
| T822 |
/workspace/coverage/default/39.spi_device_csb_read.2602969561 |
|
|
Mar 19 01:18:44 PM PDT 24 |
Mar 19 01:18:45 PM PDT 24 |
18764291 ps |
| T823 |
/workspace/coverage/default/15.spi_device_intercept.3530515655 |
|
|
Mar 19 01:15:34 PM PDT 24 |
Mar 19 01:15:40 PM PDT 24 |
900345494 ps |
| T824 |
/workspace/coverage/default/2.spi_device_tpm_all.2166388707 |
|
|
Mar 19 01:13:07 PM PDT 24 |
Mar 19 01:13:39 PM PDT 24 |
7720033960 ps |
| T825 |
/workspace/coverage/default/35.spi_device_flash_mode.1839004755 |
|
|
Mar 19 01:18:22 PM PDT 24 |
Mar 19 01:18:32 PM PDT 24 |
1344201762 ps |
| T826 |
/workspace/coverage/default/17.spi_device_upload.2663143666 |
|
|
Mar 19 01:15:59 PM PDT 24 |
Mar 19 01:16:05 PM PDT 24 |
1459452378 ps |
| T827 |
/workspace/coverage/default/2.spi_device_tpm_rw.4061380559 |
|
|
Mar 19 01:13:07 PM PDT 24 |
Mar 19 01:13:09 PM PDT 24 |
441000145 ps |
| T828 |
/workspace/coverage/default/21.spi_device_stress_all.2810101568 |
|
|
Mar 19 01:16:42 PM PDT 24 |
Mar 19 01:16:43 PM PDT 24 |
55103101 ps |
| T829 |
/workspace/coverage/default/45.spi_device_cfg_cmd.1907728304 |
|
|
Mar 19 01:19:23 PM PDT 24 |
Mar 19 01:19:28 PM PDT 24 |
492223477 ps |
| T830 |
/workspace/coverage/default/12.spi_device_stress_all.2910541933 |
|
|
Mar 19 01:15:19 PM PDT 24 |
Mar 19 01:17:29 PM PDT 24 |
20045858240 ps |
| T831 |
/workspace/coverage/default/8.spi_device_upload.1407926772 |
|
|
Mar 19 01:14:23 PM PDT 24 |
Mar 19 01:14:32 PM PDT 24 |
1471782778 ps |
| T832 |
/workspace/coverage/default/18.spi_device_upload.2181792920 |
|
|
Mar 19 01:16:15 PM PDT 24 |
Mar 19 01:16:40 PM PDT 24 |
8728908046 ps |
| T833 |
/workspace/coverage/default/24.spi_device_tpm_all.2355032425 |
|
|
Mar 19 01:16:47 PM PDT 24 |
Mar 19 01:16:53 PM PDT 24 |
836381868 ps |
| T834 |
/workspace/coverage/default/28.spi_device_csb_read.1303466941 |
|
|
Mar 19 01:17:23 PM PDT 24 |
Mar 19 01:17:24 PM PDT 24 |
19909710 ps |
| T835 |
/workspace/coverage/default/1.spi_device_upload.3212566067 |
|
|
Mar 19 01:12:51 PM PDT 24 |
Mar 19 01:12:54 PM PDT 24 |
433578516 ps |
| T836 |
/workspace/coverage/default/27.spi_device_pass_cmd_filtering.4098206187 |
|
|
Mar 19 01:17:23 PM PDT 24 |
Mar 19 01:18:25 PM PDT 24 |
217451698345 ps |
| T837 |
/workspace/coverage/default/21.spi_device_alert_test.759121503 |
|
|
Mar 19 01:16:43 PM PDT 24 |
Mar 19 01:16:44 PM PDT 24 |
13199650 ps |
| T838 |
/workspace/coverage/default/45.spi_device_pass_cmd_filtering.4217521573 |
|
|
Mar 19 01:19:23 PM PDT 24 |
Mar 19 01:19:42 PM PDT 24 |
24291736749 ps |
| T839 |
/workspace/coverage/default/17.spi_device_flash_mode.3438781940 |
|
|
Mar 19 01:16:01 PM PDT 24 |
Mar 19 01:16:17 PM PDT 24 |
2635469662 ps |
| T840 |
/workspace/coverage/default/2.spi_device_alert_test.3739384128 |
|
|
Mar 19 01:13:18 PM PDT 24 |
Mar 19 01:13:19 PM PDT 24 |
30654020 ps |
| T841 |
/workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2766639584 |
|
|
Mar 19 01:19:49 PM PDT 24 |
Mar 19 01:19:52 PM PDT 24 |
1322608051 ps |
| T842 |
/workspace/coverage/default/26.spi_device_csb_read.2003555297 |
|
|
Mar 19 01:17:03 PM PDT 24 |
Mar 19 01:17:05 PM PDT 24 |
38732368 ps |
| T97 |
/workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.258628639 |
|
|
Mar 19 01:19:22 PM PDT 24 |
Mar 19 01:20:54 PM PDT 24 |
89467826750 ps |
| T843 |
/workspace/coverage/default/18.spi_device_tpm_rw.1252661823 |
|
|
Mar 19 01:16:05 PM PDT 24 |
Mar 19 01:16:07 PM PDT 24 |
116356284 ps |
| T844 |
/workspace/coverage/default/45.spi_device_flash_mode.1833566853 |
|
|
Mar 19 01:19:24 PM PDT 24 |
Mar 19 01:19:36 PM PDT 24 |
4990601292 ps |
| T845 |
/workspace/coverage/default/24.spi_device_mailbox.4091136627 |
|
|
Mar 19 01:16:57 PM PDT 24 |
Mar 19 01:17:19 PM PDT 24 |
5591175582 ps |
| T846 |
/workspace/coverage/default/29.spi_device_mailbox.4126863739 |
|
|
Mar 19 01:17:38 PM PDT 24 |
Mar 19 01:17:56 PM PDT 24 |
10383152587 ps |
| T847 |
/workspace/coverage/default/42.spi_device_tpm_sts_read.873505428 |
|
|
Mar 19 01:19:07 PM PDT 24 |
Mar 19 01:19:08 PM PDT 24 |
92938033 ps |
| T848 |
/workspace/coverage/default/48.spi_device_alert_test.2239917292 |
|
|
Mar 19 01:19:54 PM PDT 24 |
Mar 19 01:19:55 PM PDT 24 |
29777006 ps |
| T849 |
/workspace/coverage/default/24.spi_device_upload.297781719 |
|
|
Mar 19 01:16:58 PM PDT 24 |
Mar 19 01:17:45 PM PDT 24 |
28700963929 ps |
| T850 |
/workspace/coverage/default/14.spi_device_pass_addr_payload_swap.942260768 |
|
|
Mar 19 01:15:26 PM PDT 24 |
Mar 19 01:15:43 PM PDT 24 |
5904979278 ps |
| T851 |
/workspace/coverage/default/17.spi_device_intercept.140229430 |
|
|
Mar 19 01:15:55 PM PDT 24 |
Mar 19 01:16:05 PM PDT 24 |
2333999599 ps |
| T852 |
/workspace/coverage/default/34.spi_device_mailbox.3699029853 |
|
|
Mar 19 01:18:13 PM PDT 24 |
Mar 19 01:18:16 PM PDT 24 |
123675976 ps |
| T853 |
/workspace/coverage/default/34.spi_device_read_buffer_direct.1649067475 |
|
|
Mar 19 01:18:14 PM PDT 24 |
Mar 19 01:18:18 PM PDT 24 |
392602318 ps |
| T854 |
/workspace/coverage/default/22.spi_device_csb_read.3950777674 |
|
|
Mar 19 01:16:41 PM PDT 24 |
Mar 19 01:16:42 PM PDT 24 |
14210197 ps |
| T855 |
/workspace/coverage/default/32.spi_device_read_buffer_direct.4284814301 |
|
|
Mar 19 01:17:55 PM PDT 24 |
Mar 19 01:17:58 PM PDT 24 |
427551707 ps |
| T856 |
/workspace/coverage/default/25.spi_device_tpm_sts_read.2094825757 |
|
|
Mar 19 01:17:05 PM PDT 24 |
Mar 19 01:17:06 PM PDT 24 |
211772358 ps |
| T857 |
/workspace/coverage/default/9.spi_device_pass_cmd_filtering.2609674766 |
|
|
Mar 19 01:14:47 PM PDT 24 |
Mar 19 01:14:54 PM PDT 24 |
1775159121 ps |
| T858 |
/workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2415283595 |
|
|
Mar 19 01:19:09 PM PDT 24 |
Mar 19 01:19:17 PM PDT 24 |
1695672440 ps |
| T859 |
/workspace/coverage/default/42.spi_device_tpm_all.828430037 |
|
|
Mar 19 01:19:06 PM PDT 24 |
Mar 19 01:19:40 PM PDT 24 |
13437617618 ps |
| T860 |
/workspace/coverage/default/14.spi_device_intercept.3908294640 |
|
|
Mar 19 01:15:27 PM PDT 24 |
Mar 19 01:15:32 PM PDT 24 |
393270359 ps |
| T861 |
/workspace/coverage/default/45.spi_device_tpm_all.3390259389 |
|
|
Mar 19 01:19:23 PM PDT 24 |
Mar 19 01:19:42 PM PDT 24 |
4034059468 ps |
| T862 |
/workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2211089143 |
|
|
Mar 19 01:13:48 PM PDT 24 |
Mar 19 01:13:49 PM PDT 24 |
1426035283 ps |
| T863 |
/workspace/coverage/default/47.spi_device_read_buffer_direct.2060402238 |
|
|
Mar 19 01:19:52 PM PDT 24 |
Mar 19 01:19:57 PM PDT 24 |
4525605194 ps |
| T864 |
/workspace/coverage/default/10.spi_device_flash_and_tpm.266429325 |
|
|
Mar 19 01:14:59 PM PDT 24 |
Mar 19 01:23:21 PM PDT 24 |
72469583838 ps |
| T865 |
/workspace/coverage/default/28.spi_device_tpm_rw.1890193119 |
|
|
Mar 19 01:17:34 PM PDT 24 |
Mar 19 01:17:40 PM PDT 24 |
580728675 ps |
| T866 |
/workspace/coverage/default/38.spi_device_tpm_all.3123762570 |
|
|
Mar 19 01:18:38 PM PDT 24 |
Mar 19 01:19:58 PM PDT 24 |
29111698505 ps |
| T867 |
/workspace/coverage/default/48.spi_device_upload.198566182 |
|
|
Mar 19 01:19:42 PM PDT 24 |
Mar 19 01:19:48 PM PDT 24 |
2993207818 ps |
| T868 |
/workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1803312987 |
|
|
Mar 19 01:12:50 PM PDT 24 |
Mar 19 01:13:12 PM PDT 24 |
1400683936 ps |
| T869 |
/workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1165630082 |
|
|
Mar 19 01:19:52 PM PDT 24 |
Mar 19 01:20:07 PM PDT 24 |
11028410808 ps |
| T870 |
/workspace/coverage/default/27.spi_device_pass_addr_payload_swap.647122626 |
|
|
Mar 19 01:17:26 PM PDT 24 |
Mar 19 01:17:31 PM PDT 24 |
3195770982 ps |
| T871 |
/workspace/coverage/default/2.spi_device_tpm_sts_read.2159217586 |
|
|
Mar 19 01:13:05 PM PDT 24 |
Mar 19 01:13:06 PM PDT 24 |
307129279 ps |
| T872 |
/workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3582371321 |
|
|
Mar 19 01:19:00 PM PDT 24 |
Mar 19 01:20:05 PM PDT 24 |
15519167673 ps |
| T873 |
/workspace/coverage/default/7.spi_device_flash_all.3331888897 |
|
|
Mar 19 01:14:11 PM PDT 24 |
Mar 19 01:15:24 PM PDT 24 |
13125900084 ps |
| T874 |
/workspace/coverage/default/30.spi_device_stress_all.3485369596 |
|
|
Mar 19 01:17:48 PM PDT 24 |
Mar 19 01:17:49 PM PDT 24 |
101672583 ps |
| T875 |
/workspace/coverage/default/37.spi_device_flash_and_tpm.3864090939 |
|
|
Mar 19 01:18:31 PM PDT 24 |
Mar 19 01:26:06 PM PDT 24 |
122485760382 ps |
| T876 |
/workspace/coverage/default/29.spi_device_flash_mode.1630617190 |
|
|
Mar 19 01:17:36 PM PDT 24 |
Mar 19 01:17:57 PM PDT 24 |
10497397989 ps |
| T877 |
/workspace/coverage/default/2.spi_device_stress_all.3103663505 |
|
|
Mar 19 01:13:16 PM PDT 24 |
Mar 19 01:22:04 PM PDT 24 |
73671213190 ps |
| T878 |
/workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2324309336 |
|
|
Mar 19 01:16:17 PM PDT 24 |
Mar 19 01:16:24 PM PDT 24 |
996590838 ps |
| T879 |
/workspace/coverage/default/23.spi_device_cfg_cmd.3181155159 |
|
|
Mar 19 01:16:48 PM PDT 24 |
Mar 19 01:16:52 PM PDT 24 |
1164271602 ps |
| T880 |
/workspace/coverage/default/45.spi_device_tpm_sts_read.1070841316 |
|
|
Mar 19 01:19:25 PM PDT 24 |
Mar 19 01:19:26 PM PDT 24 |
303266818 ps |
| T881 |
/workspace/coverage/default/28.spi_device_upload.3082586627 |
|
|
Mar 19 01:17:35 PM PDT 24 |
Mar 19 01:17:40 PM PDT 24 |
1066203244 ps |
| T882 |
/workspace/coverage/default/30.spi_device_mailbox.1822827910 |
|
|
Mar 19 01:17:40 PM PDT 24 |
Mar 19 01:17:56 PM PDT 24 |
2150008806 ps |
| T883 |
/workspace/coverage/default/38.spi_device_flash_mode.3384378341 |
|
|
Mar 19 01:18:39 PM PDT 24 |
Mar 19 01:18:57 PM PDT 24 |
4872635678 ps |
| T884 |
/workspace/coverage/default/25.spi_device_stress_all.322003141 |
|
|
Mar 19 01:17:04 PM PDT 24 |
Mar 19 01:24:48 PM PDT 24 |
256995933817 ps |
| T885 |
/workspace/coverage/default/37.spi_device_read_buffer_direct.385837157 |
|
|
Mar 19 01:18:29 PM PDT 24 |
Mar 19 01:18:32 PM PDT 24 |
126101483 ps |
| T886 |
/workspace/coverage/default/45.spi_device_flash_all.4050531948 |
|
|
Mar 19 01:19:23 PM PDT 24 |
Mar 19 01:19:27 PM PDT 24 |
430186152 ps |
| T887 |
/workspace/coverage/default/5.spi_device_mailbox.57153815 |
|
|
Mar 19 01:13:46 PM PDT 24 |
Mar 19 01:13:56 PM PDT 24 |
2461841118 ps |
| T888 |
/workspace/coverage/default/27.spi_device_tpm_read_hw_reg.4236494177 |
|
|
Mar 19 01:17:24 PM PDT 24 |
Mar 19 01:17:28 PM PDT 24 |
1390660865 ps |
| T889 |
/workspace/coverage/default/6.spi_device_tpm_all.2735382177 |
|
|
Mar 19 01:14:03 PM PDT 24 |
Mar 19 01:14:52 PM PDT 24 |
60446135609 ps |
| T890 |
/workspace/coverage/default/46.spi_device_tpm_rw.2575062071 |
|
|
Mar 19 01:19:34 PM PDT 24 |
Mar 19 01:19:36 PM PDT 24 |
223013159 ps |
| T891 |
/workspace/coverage/default/32.spi_device_tpm_all.3332147338 |
|
|
Mar 19 01:17:55 PM PDT 24 |
Mar 19 01:18:06 PM PDT 24 |
1719734953 ps |
| T231 |
/workspace/coverage/default/10.spi_device_pass_addr_payload_swap.380964660 |
|
|
Mar 19 01:14:57 PM PDT 24 |
Mar 19 01:15:06 PM PDT 24 |
2355057969 ps |
| T892 |
/workspace/coverage/default/14.spi_device_upload.1685503237 |
|
|
Mar 19 01:15:25 PM PDT 24 |
Mar 19 01:15:28 PM PDT 24 |
3582097276 ps |
| T893 |
/workspace/coverage/default/21.spi_device_cfg_cmd.1139616722 |
|
|
Mar 19 01:16:33 PM PDT 24 |
Mar 19 01:16:35 PM PDT 24 |
154258752 ps |
| T894 |
/workspace/coverage/default/13.spi_device_pass_cmd_filtering.105417969 |
|
|
Mar 19 01:15:29 PM PDT 24 |
Mar 19 01:15:55 PM PDT 24 |
19107593708 ps |
| T895 |
/workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1954946677 |
|
|
Mar 19 01:14:12 PM PDT 24 |
Mar 19 01:14:14 PM PDT 24 |
73679595 ps |
| T896 |
/workspace/coverage/default/13.spi_device_tpm_all.1565308895 |
|
|
Mar 19 01:15:20 PM PDT 24 |
Mar 19 01:15:23 PM PDT 24 |
188976567 ps |
| T897 |
/workspace/coverage/default/27.spi_device_tpm_sts_read.4032844647 |
|
|
Mar 19 01:17:23 PM PDT 24 |
Mar 19 01:17:24 PM PDT 24 |
125515697 ps |
| T898 |
/workspace/coverage/default/7.spi_device_flash_mode.560894296 |
|
|
Mar 19 01:14:13 PM PDT 24 |
Mar 19 01:14:20 PM PDT 24 |
487685341 ps |
| T899 |
/workspace/coverage/default/23.spi_device_mailbox.98767987 |
|
|
Mar 19 01:16:48 PM PDT 24 |
Mar 19 01:17:11 PM PDT 24 |
6421398569 ps |
| T900 |
/workspace/coverage/default/27.spi_device_upload.1388233643 |
|
|
Mar 19 01:17:25 PM PDT 24 |
Mar 19 01:17:32 PM PDT 24 |
1358397753 ps |
| T901 |
/workspace/coverage/default/46.spi_device_stress_all.1938929046 |
|
|
Mar 19 01:19:50 PM PDT 24 |
Mar 19 01:23:28 PM PDT 24 |
17878723270 ps |
| T902 |
/workspace/coverage/default/0.spi_device_ram_cfg.751143125 |
|
|
Mar 19 01:12:23 PM PDT 24 |
Mar 19 01:12:24 PM PDT 24 |
33884719 ps |
| T903 |
/workspace/coverage/default/8.spi_device_alert_test.1096643622 |
|
|
Mar 19 01:14:47 PM PDT 24 |
Mar 19 01:14:47 PM PDT 24 |
61383022 ps |
| T904 |
/workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2935589453 |
|
|
Mar 19 01:16:49 PM PDT 24 |
Mar 19 01:26:14 PM PDT 24 |
72828274254 ps |
| T905 |
/workspace/coverage/default/20.spi_device_read_buffer_direct.4019361696 |
|
|
Mar 19 01:16:27 PM PDT 24 |
Mar 19 01:16:34 PM PDT 24 |
6404456153 ps |
| T906 |
/workspace/coverage/default/6.spi_device_csb_read.3441588305 |
|
|
Mar 19 01:14:04 PM PDT 24 |
Mar 19 01:14:05 PM PDT 24 |
48734643 ps |
| T907 |
/workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2189542192 |
|
|
Mar 19 01:17:44 PM PDT 24 |
Mar 19 01:19:33 PM PDT 24 |
15516553796 ps |
| T908 |
/workspace/coverage/default/33.spi_device_cfg_cmd.4066574165 |
|
|
Mar 19 01:18:08 PM PDT 24 |
Mar 19 01:18:11 PM PDT 24 |
354646543 ps |
| T909 |
/workspace/coverage/default/25.spi_device_cfg_cmd.4143895565 |
|
|
Mar 19 01:17:02 PM PDT 24 |
Mar 19 01:17:08 PM PDT 24 |
446147716 ps |
| T910 |
/workspace/coverage/default/12.spi_device_intercept.1513764905 |
|
|
Mar 19 01:15:12 PM PDT 24 |
Mar 19 01:15:27 PM PDT 24 |
35193662804 ps |
| T911 |
/workspace/coverage/default/7.spi_device_stress_all.986693016 |
|
|
Mar 19 01:14:23 PM PDT 24 |
Mar 19 01:16:05 PM PDT 24 |
5222236269 ps |
| T912 |
/workspace/coverage/default/45.spi_device_stress_all.1824231653 |
|
|
Mar 19 01:19:22 PM PDT 24 |
Mar 19 01:19:24 PM PDT 24 |
262327982 ps |
| T913 |
/workspace/coverage/default/37.spi_device_pass_addr_payload_swap.4123214731 |
|
|
Mar 19 01:18:37 PM PDT 24 |
Mar 19 01:19:00 PM PDT 24 |
43925153631 ps |
| T914 |
/workspace/coverage/default/17.spi_device_pass_addr_payload_swap.499357050 |
|
|
Mar 19 01:15:58 PM PDT 24 |
Mar 19 01:16:28 PM PDT 24 |
19804876393 ps |
| T915 |
/workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2102781246 |
|
|
Mar 19 01:14:04 PM PDT 24 |
Mar 19 01:18:44 PM PDT 24 |
62852437563 ps |
| T916 |
/workspace/coverage/default/15.spi_device_pass_addr_payload_swap.4110562836 |
|
|
Mar 19 01:15:34 PM PDT 24 |
Mar 19 01:15:38 PM PDT 24 |
667790148 ps |
| T917 |
/workspace/coverage/default/46.spi_device_alert_test.2625778229 |
|
|
Mar 19 01:19:42 PM PDT 24 |
Mar 19 01:19:42 PM PDT 24 |
30876666 ps |
| T918 |
/workspace/coverage/default/1.spi_device_ram_cfg.186414963 |
|
|
Mar 19 01:12:42 PM PDT 24 |
Mar 19 01:12:44 PM PDT 24 |
17962194 ps |
| T49 |
/workspace/coverage/default/4.spi_device_flash_and_tpm.2673290253 |
|
|
Mar 19 01:13:37 PM PDT 24 |
Mar 19 01:14:12 PM PDT 24 |
3481689126 ps |
| T919 |
/workspace/coverage/default/2.spi_device_tpm_read_hw_reg.65193984 |
|
|
Mar 19 01:13:05 PM PDT 24 |
Mar 19 01:13:07 PM PDT 24 |
504862436 ps |
| T50 |
/workspace/coverage/default/8.spi_device_stress_all.2880520169 |
|
|
Mar 19 01:14:46 PM PDT 24 |
Mar 19 01:27:45 PM PDT 24 |
1213437642026 ps |
| T920 |
/workspace/coverage/default/26.spi_device_tpm_sts_read.846542397 |
|
|
Mar 19 01:17:11 PM PDT 24 |
Mar 19 01:17:12 PM PDT 24 |
174575978 ps |
| T921 |
/workspace/coverage/default/35.spi_device_cfg_cmd.573753137 |
|
|
Mar 19 01:18:21 PM PDT 24 |
Mar 19 01:18:26 PM PDT 24 |
504524740 ps |
| T922 |
/workspace/coverage/default/27.spi_device_tpm_all.4146497026 |
|
|
Mar 19 01:17:23 PM PDT 24 |
Mar 19 01:18:05 PM PDT 24 |
26519004398 ps |
| T923 |
/workspace/coverage/default/14.spi_device_csb_read.4077540727 |
|
|
Mar 19 01:15:29 PM PDT 24 |
Mar 19 01:15:30 PM PDT 24 |
15418515 ps |
| T924 |
/workspace/coverage/default/37.spi_device_mailbox.1035782061 |
|
|
Mar 19 01:18:38 PM PDT 24 |
Mar 19 01:18:46 PM PDT 24 |
1082899004 ps |
| T925 |
/workspace/coverage/default/10.spi_device_stress_all.976091047 |
|
|
Mar 19 01:14:58 PM PDT 24 |
Mar 19 01:16:53 PM PDT 24 |
49343653002 ps |
| T238 |
/workspace/coverage/default/32.spi_device_flash_and_tpm.2024885412 |
|
|
Mar 19 01:17:59 PM PDT 24 |
Mar 19 01:20:40 PM PDT 24 |
93599977068 ps |
| T926 |
/workspace/coverage/default/29.spi_device_flash_and_tpm.4039740541 |
|
|
Mar 19 01:17:42 PM PDT 24 |
Mar 19 01:19:39 PM PDT 24 |
50388465772 ps |
| T927 |
/workspace/coverage/default/11.spi_device_tpm_sts_read.3639189516 |
|
|
Mar 19 01:14:57 PM PDT 24 |
Mar 19 01:14:57 PM PDT 24 |
46419060 ps |
| T928 |
/workspace/coverage/default/17.spi_device_stress_all.3733430525 |
|
|
Mar 19 01:16:03 PM PDT 24 |
Mar 19 01:16:05 PM PDT 24 |
221964363 ps |
| T929 |
/workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3624814432 |
|
|
Mar 19 01:14:57 PM PDT 24 |
Mar 19 01:15:19 PM PDT 24 |
32406324700 ps |
| T930 |
/workspace/coverage/default/15.spi_device_mailbox.4275013286 |
|
|
Mar 19 01:15:49 PM PDT 24 |
Mar 19 01:16:31 PM PDT 24 |
112042644381 ps |
| T931 |
/workspace/coverage/default/6.spi_device_tpm_rw.3281164882 |
|
|
Mar 19 01:14:04 PM PDT 24 |
Mar 19 01:14:06 PM PDT 24 |
18345579 ps |
| T932 |
/workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3726932661 |
|
|
Mar 19 01:17:39 PM PDT 24 |
Mar 19 01:17:50 PM PDT 24 |
7698925704 ps |
| T933 |
/workspace/coverage/default/35.spi_device_pass_cmd_filtering.1763304818 |
|
|
Mar 19 01:18:21 PM PDT 24 |
Mar 19 01:18:26 PM PDT 24 |
431435089 ps |
| T934 |
/workspace/coverage/default/33.spi_device_flash_and_tpm.1113456606 |
|
|
Mar 19 01:18:11 PM PDT 24 |
Mar 19 01:20:11 PM PDT 24 |
60736450160 ps |
| T935 |
/workspace/coverage/default/0.spi_device_pass_cmd_filtering.3225893029 |
|
|
Mar 19 01:12:24 PM PDT 24 |
Mar 19 01:12:33 PM PDT 24 |
14205078194 ps |
| T936 |
/workspace/coverage/default/25.spi_device_csb_read.131623113 |
|
|
Mar 19 01:17:03 PM PDT 24 |
Mar 19 01:17:04 PM PDT 24 |
36516821 ps |
| T937 |
/workspace/coverage/default/34.spi_device_tpm_all.1266161848 |
|
|
Mar 19 01:18:11 PM PDT 24 |
Mar 19 01:18:41 PM PDT 24 |
17539947657 ps |
| T938 |
/workspace/coverage/default/46.spi_device_read_buffer_direct.1352983045 |
|
|
Mar 19 01:19:50 PM PDT 24 |
Mar 19 01:19:55 PM PDT 24 |
325501641 ps |
| T939 |
/workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.4000159716 |
|
|
Mar 19 01:18:32 PM PDT 24 |
Mar 19 01:19:43 PM PDT 24 |
69580519250 ps |
| T940 |
/workspace/coverage/default/13.spi_device_stress_all.720786296 |
|
|
Mar 19 01:15:29 PM PDT 24 |
Mar 19 01:21:04 PM PDT 24 |
49889201316 ps |
| T941 |
/workspace/coverage/default/27.spi_device_alert_test.3602645443 |
|
|
Mar 19 01:17:24 PM PDT 24 |
Mar 19 01:17:25 PM PDT 24 |
16253777 ps |
| T942 |
/workspace/coverage/default/7.spi_device_tpm_rw.1971816789 |
|
|
Mar 19 01:14:12 PM PDT 24 |
Mar 19 01:14:13 PM PDT 24 |
28153011 ps |
| T943 |
/workspace/coverage/default/49.spi_device_flash_mode.1565336894 |
|
|
Mar 19 01:19:55 PM PDT 24 |
Mar 19 01:20:25 PM PDT 24 |
9639488402 ps |
| T944 |
/workspace/coverage/default/36.spi_device_mailbox.2241052761 |
|
|
Mar 19 01:18:19 PM PDT 24 |
Mar 19 01:18:21 PM PDT 24 |
594909471 ps |
| T945 |
/workspace/coverage/default/13.spi_device_tpm_sts_read.2284590768 |
|
|
Mar 19 01:15:19 PM PDT 24 |
Mar 19 01:15:20 PM PDT 24 |
115281747 ps |
| T946 |
/workspace/coverage/default/1.spi_device_cfg_cmd.1887622664 |
|
|
Mar 19 01:12:52 PM PDT 24 |
Mar 19 01:12:55 PM PDT 24 |
136153808 ps |
| T947 |
/workspace/coverage/default/26.spi_device_mailbox.4178180758 |
|
|
Mar 19 01:17:11 PM PDT 24 |
Mar 19 01:17:26 PM PDT 24 |
7276790604 ps |
| T948 |
/workspace/coverage/default/4.spi_device_tpm_sts_read.943002466 |
|
|
Mar 19 01:13:36 PM PDT 24 |
Mar 19 01:13:38 PM PDT 24 |
28215209 ps |
| T949 |
/workspace/coverage/default/38.spi_device_mailbox.2020503316 |
|
|
Mar 19 01:18:38 PM PDT 24 |
Mar 19 01:18:41 PM PDT 24 |
1174390397 ps |
| T950 |
/workspace/coverage/default/42.spi_device_mailbox.2704213761 |
|
|
Mar 19 01:19:11 PM PDT 24 |
Mar 19 01:19:16 PM PDT 24 |
1992345952 ps |
| T951 |
/workspace/coverage/default/15.spi_device_ram_cfg.950717429 |
|
|
Mar 19 01:15:35 PM PDT 24 |
Mar 19 01:15:36 PM PDT 24 |
16282342 ps |
| T952 |
/workspace/coverage/default/8.spi_device_read_buffer_direct.2633461452 |
|
|
Mar 19 01:14:47 PM PDT 24 |
Mar 19 01:14:51 PM PDT 24 |
2935251553 ps |
| T953 |
/workspace/coverage/default/1.spi_device_alert_test.960309358 |
|
|
Mar 19 01:12:53 PM PDT 24 |
Mar 19 01:12:53 PM PDT 24 |
21060072 ps |
| T954 |
/workspace/coverage/default/19.spi_device_intercept.1226182934 |
|
|
Mar 19 01:16:20 PM PDT 24 |
Mar 19 01:16:24 PM PDT 24 |
849241182 ps |
| T955 |
/workspace/coverage/default/38.spi_device_flash_and_tpm.933284971 |
|
|
Mar 19 01:18:39 PM PDT 24 |
Mar 19 01:22:19 PM PDT 24 |
122954405427 ps |
| T956 |
/workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1344703977 |
|
|
Mar 19 01:16:49 PM PDT 24 |
Mar 19 01:16:55 PM PDT 24 |
10536892053 ps |
| T957 |
/workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.258677224 |
|
|
Mar 19 01:17:34 PM PDT 24 |
Mar 19 01:22:25 PM PDT 24 |
55048218773 ps |
| T958 |
/workspace/coverage/default/20.spi_device_alert_test.926446713 |
|
|
Mar 19 01:16:31 PM PDT 24 |
Mar 19 01:16:32 PM PDT 24 |
42592467 ps |
| T959 |
/workspace/coverage/default/35.spi_device_tpm_rw.571872169 |
|
|
Mar 19 01:18:23 PM PDT 24 |
Mar 19 01:18:25 PM PDT 24 |
329344685 ps |
| T960 |
/workspace/coverage/default/16.spi_device_flash_and_tpm.2026938694 |
|
|
Mar 19 01:15:49 PM PDT 24 |
Mar 19 01:18:10 PM PDT 24 |
33172161500 ps |
| T961 |
/workspace/coverage/default/9.spi_device_read_buffer_direct.3059197972 |
|
|
Mar 19 01:14:40 PM PDT 24 |
Mar 19 01:14:44 PM PDT 24 |
206825898 ps |
| T962 |
/workspace/coverage/default/13.spi_device_flash_all.300474203 |
|
|
Mar 19 01:15:29 PM PDT 24 |
Mar 19 01:18:15 PM PDT 24 |
36277106197 ps |
| T963 |
/workspace/coverage/default/46.spi_device_upload.785488730 |
|
|
Mar 19 01:19:51 PM PDT 24 |
Mar 19 01:19:57 PM PDT 24 |
406539552 ps |
| T964 |
/workspace/coverage/default/15.spi_device_alert_test.325142787 |
|
|
Mar 19 01:15:53 PM PDT 24 |
Mar 19 01:15:54 PM PDT 24 |
33903179 ps |
| T965 |
/workspace/coverage/default/38.spi_device_alert_test.398813299 |
|
|
Mar 19 01:18:44 PM PDT 24 |
Mar 19 01:18:45 PM PDT 24 |
26339980 ps |
| T966 |
/workspace/coverage/default/25.spi_device_flash_mode.905834525 |
|
|
Mar 19 01:17:02 PM PDT 24 |
Mar 19 01:17:18 PM PDT 24 |
12818399612 ps |
| T967 |
/workspace/coverage/default/43.spi_device_tpm_all.729994433 |
|
|
Mar 19 01:19:09 PM PDT 24 |
Mar 19 01:19:23 PM PDT 24 |
2727174842 ps |
| T968 |
/workspace/coverage/default/29.spi_device_upload.2878819700 |
|
|
Mar 19 01:17:35 PM PDT 24 |
Mar 19 01:17:39 PM PDT 24 |
7019104291 ps |
| T969 |
/workspace/coverage/default/8.spi_device_flash_mode.1846541592 |
|
|
Mar 19 01:14:33 PM PDT 24 |
Mar 19 01:14:52 PM PDT 24 |
13772234923 ps |
| T121 |
/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3971489737 |
|
|
Mar 19 02:54:41 PM PDT 24 |
Mar 19 02:54:43 PM PDT 24 |
213490094 ps |
| T65 |
/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1437215660 |
|
|
Mar 19 02:54:20 PM PDT 24 |
Mar 19 02:54:33 PM PDT 24 |
1450447772 ps |
| T122 |
/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.913925676 |
|
|
Mar 19 02:53:44 PM PDT 24 |
Mar 19 02:53:46 PM PDT 24 |
37138247 ps |
| T970 |
/workspace/coverage/cover_reg_top/12.spi_device_intr_test.1149369537 |
|
|
Mar 19 02:54:13 PM PDT 24 |
Mar 19 02:54:14 PM PDT 24 |
13637619 ps |
| T123 |
/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2323729510 |
|
|
Mar 19 02:54:22 PM PDT 24 |
Mar 19 02:54:26 PM PDT 24 |
1451772636 ps |
| T66 |
/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2014896551 |
|
|
Mar 19 02:54:22 PM PDT 24 |
Mar 19 02:54:26 PM PDT 24 |
275601452 ps |
| T146 |
/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2290489259 |
|
|
Mar 19 02:54:12 PM PDT 24 |
Mar 19 02:54:16 PM PDT 24 |
608756970 ps |
| T971 |
/workspace/coverage/cover_reg_top/45.spi_device_intr_test.1714229224 |
|
|
Mar 19 02:54:22 PM PDT 24 |
Mar 19 02:54:24 PM PDT 24 |
22281818 ps |
| T972 |
/workspace/coverage/cover_reg_top/30.spi_device_intr_test.34126018 |
|
|
Mar 19 02:54:22 PM PDT 24 |
Mar 19 02:54:23 PM PDT 24 |
14230371 ps |
| T973 |
/workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2292041831 |
|
|
Mar 19 02:53:44 PM PDT 24 |
Mar 19 02:53:45 PM PDT 24 |
13400456 ps |
| T974 |
/workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2884573647 |
|
|
Mar 19 02:53:55 PM PDT 24 |
Mar 19 02:53:56 PM PDT 24 |
16279205 ps |
| T975 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1526422894 |
|
|
Mar 19 02:53:43 PM PDT 24 |
Mar 19 02:54:10 PM PDT 24 |
13400694335 ps |
| T124 |
/workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1055940606 |
|
|
Mar 19 02:54:01 PM PDT 24 |
Mar 19 02:54:03 PM PDT 24 |
67958329 ps |
| T976 |
/workspace/coverage/cover_reg_top/39.spi_device_intr_test.2017572157 |
|
|
Mar 19 02:54:26 PM PDT 24 |
Mar 19 02:54:28 PM PDT 24 |
14025053 ps |
| T977 |
/workspace/coverage/cover_reg_top/47.spi_device_intr_test.379962246 |
|
|
Mar 19 02:54:25 PM PDT 24 |
Mar 19 02:54:27 PM PDT 24 |
13382354 ps |
| T125 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1333996337 |
|
|
Mar 19 02:53:43 PM PDT 24 |
Mar 19 02:53:45 PM PDT 24 |
30135345 ps |
| T978 |
/workspace/coverage/cover_reg_top/28.spi_device_intr_test.1766627082 |
|
|
Mar 19 02:54:21 PM PDT 24 |
Mar 19 02:54:23 PM PDT 24 |
14888021 ps |
| T67 |
/workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2660492074 |
|
|
Mar 19 02:53:55 PM PDT 24 |
Mar 19 02:54:09 PM PDT 24 |
754565180 ps |
| T101 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3397579056 |
|
|
Mar 19 02:53:48 PM PDT 24 |
Mar 19 02:53:51 PM PDT 24 |
680128415 ps |
| T979 |
/workspace/coverage/cover_reg_top/23.spi_device_intr_test.1163766121 |
|
|
Mar 19 02:54:19 PM PDT 24 |
Mar 19 02:54:21 PM PDT 24 |
20677199 ps |
| T103 |
/workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2377633812 |
|
|
Mar 19 02:53:40 PM PDT 24 |
Mar 19 02:54:02 PM PDT 24 |
11291148481 ps |
| T147 |
/workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2213106437 |
|
|
Mar 19 02:54:19 PM PDT 24 |
Mar 19 02:54:20 PM PDT 24 |
40283647 ps |
| T980 |
/workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.224020893 |
|
|
Mar 19 02:54:22 PM PDT 24 |
Mar 19 02:54:25 PM PDT 24 |
103439740 ps |
| T90 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2534768941 |
|
|
Mar 19 02:53:41 PM PDT 24 |
Mar 19 02:53:42 PM PDT 24 |
46882592 ps |
| T981 |
/workspace/coverage/cover_reg_top/27.spi_device_intr_test.3666348360 |
|
|
Mar 19 02:54:22 PM PDT 24 |
Mar 19 02:54:24 PM PDT 24 |
39598622 ps |
| T982 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2801889392 |
|
|
Mar 19 02:53:43 PM PDT 24 |
Mar 19 02:54:06 PM PDT 24 |
1453971378 ps |
| T983 |
/workspace/coverage/cover_reg_top/14.spi_device_intr_test.314744288 |
|
|
Mar 19 02:54:13 PM PDT 24 |
Mar 19 02:54:14 PM PDT 24 |
17654520 ps |
| T126 |
/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1602335646 |
|
|
Mar 19 02:54:14 PM PDT 24 |
Mar 19 02:54:16 PM PDT 24 |
110958202 ps |
| T984 |
/workspace/coverage/cover_reg_top/2.spi_device_intr_test.960400750 |
|
|
Mar 19 02:53:48 PM PDT 24 |
Mar 19 02:53:49 PM PDT 24 |
12226367 ps |
| T102 |
/workspace/coverage/cover_reg_top/19.spi_device_tl_errors.929766569 |
|
|
Mar 19 02:54:22 PM PDT 24 |
Mar 19 02:54:25 PM PDT 24 |
29402439 ps |
| T91 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1631729221 |
|
|
Mar 19 02:53:47 PM PDT 24 |
Mar 19 02:53:49 PM PDT 24 |
26159228 ps |
| T985 |
/workspace/coverage/cover_reg_top/36.spi_device_intr_test.1027971344 |
|
|
Mar 19 02:54:21 PM PDT 24 |
Mar 19 02:54:23 PM PDT 24 |
41674828 ps |
| T104 |
/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1234429896 |
|
|
Mar 19 02:54:12 PM PDT 24 |
Mar 19 02:54:15 PM PDT 24 |
656807688 ps |
| T105 |
/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.91041828 |
|
|
Mar 19 02:54:12 PM PDT 24 |
Mar 19 02:54:16 PM PDT 24 |
150145641 ps |
| T106 |
/workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1904998218 |
|
|
Mar 19 02:54:11 PM PDT 24 |
Mar 19 02:54:15 PM PDT 24 |
125562139 ps |
| T120 |
/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.4130097793 |
|
|
Mar 19 02:54:12 PM PDT 24 |
Mar 19 02:54:31 PM PDT 24 |
306001454 ps |
| T112 |
/workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1740963498 |
|
|
Mar 19 02:54:12 PM PDT 24 |
Mar 19 02:54:17 PM PDT 24 |
133272074 ps |
| T127 |
/workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3647721108 |
|
|
Mar 19 02:53:46 PM PDT 24 |
Mar 19 02:53:48 PM PDT 24 |
20123177 ps |
| T986 |
/workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1980161968 |
|
|
Mar 19 02:53:41 PM PDT 24 |
Mar 19 02:53:42 PM PDT 24 |
12899138 ps |
| T128 |
/workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3068581192 |
|
|
Mar 19 02:54:20 PM PDT 24 |
Mar 19 02:54:24 PM PDT 24 |
175332824 ps |
| T987 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3562362251 |
|
|
Mar 19 02:53:40 PM PDT 24 |
Mar 19 02:53:50 PM PDT 24 |
1238048148 ps |
| T119 |
/workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2625503059 |
|
|
Mar 19 02:53:55 PM PDT 24 |
Mar 19 02:54:15 PM PDT 24 |
2140695680 ps |
| T129 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1906099489 |
|
|
Mar 19 02:53:42 PM PDT 24 |
Mar 19 02:53:56 PM PDT 24 |
422788088 ps |
| T988 |
/workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1566646124 |
|
|
Mar 19 02:54:22 PM PDT 24 |
Mar 19 02:54:25 PM PDT 24 |
216189105 ps |
| T989 |
/workspace/coverage/cover_reg_top/25.spi_device_intr_test.2239099970 |
|
|
Mar 19 02:54:23 PM PDT 24 |
Mar 19 02:54:24 PM PDT 24 |
25988156 ps |
| T92 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.193988974 |
|
|
Mar 19 02:53:56 PM PDT 24 |
Mar 19 02:53:58 PM PDT 24 |
220954752 ps |
| T148 |
/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2643465468 |
|
|
Mar 19 02:54:05 PM PDT 24 |
Mar 19 02:54:09 PM PDT 24 |
129072317 ps |
| T247 |
/workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.4186515081 |
|
|
Mar 19 02:53:49 PM PDT 24 |
Mar 19 02:54:09 PM PDT 24 |
1003615232 ps |
| T990 |
/workspace/coverage/cover_reg_top/37.spi_device_intr_test.2264952023 |
|
|
Mar 19 02:54:19 PM PDT 24 |
Mar 19 02:54:21 PM PDT 24 |
32025658 ps |
| T991 |
/workspace/coverage/cover_reg_top/11.spi_device_intr_test.650574408 |
|
|
Mar 19 02:54:08 PM PDT 24 |
Mar 19 02:54:09 PM PDT 24 |
105305376 ps |
| T116 |
/workspace/coverage/cover_reg_top/7.spi_device_tl_errors.476899595 |
|
|
Mar 19 02:54:02 PM PDT 24 |
Mar 19 02:54:04 PM PDT 24 |
23101538 ps |
| T992 |
/workspace/coverage/cover_reg_top/33.spi_device_intr_test.4146051278 |
|
|
Mar 19 02:54:22 PM PDT 24 |
Mar 19 02:54:23 PM PDT 24 |
31366579 ps |
| T993 |
/workspace/coverage/cover_reg_top/0.spi_device_intr_test.1717285334 |
|
|
Mar 19 02:53:42 PM PDT 24 |
Mar 19 02:53:43 PM PDT 24 |
22398073 ps |
| T994 |
/workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1950775766 |
|
|
Mar 19 02:54:12 PM PDT 24 |
Mar 19 02:54:24 PM PDT 24 |
847638587 ps |
| T995 |
/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.69339708 |
|
|
Mar 19 02:54:10 PM PDT 24 |
Mar 19 02:54:12 PM PDT 24 |
25739195 ps |
| T110 |
/workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2701394021 |
|
|
Mar 19 02:53:54 PM PDT 24 |
Mar 19 02:53:58 PM PDT 24 |
1993618083 ps |
| T108 |
/workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2611691432 |
|
|
Mar 19 02:53:42 PM PDT 24 |
Mar 19 02:53:47 PM PDT 24 |
238483945 ps |
| T117 |
/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2113653143 |
|
|
Mar 19 02:54:12 PM PDT 24 |
Mar 19 02:54:14 PM PDT 24 |
258623256 ps |
| T118 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.650517140 |
|
|
Mar 19 02:53:57 PM PDT 24 |
Mar 19 02:53:59 PM PDT 24 |
75216543 ps |
| T996 |
/workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3923142224 |
|
|
Mar 19 02:54:25 PM PDT 24 |
Mar 19 02:54:29 PM PDT 24 |
45684682 ps |
| T149 |
/workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1176532464 |
|
|
Mar 19 02:54:05 PM PDT 24 |
Mar 19 02:54:21 PM PDT 24 |
666801310 ps |
| T997 |
/workspace/coverage/cover_reg_top/8.spi_device_intr_test.313954559 |
|
|
Mar 19 02:54:03 PM PDT 24 |
Mar 19 02:54:04 PM PDT 24 |
15355225 ps |
| T130 |
/workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1188411505 |
|
|
Mar 19 02:53:56 PM PDT 24 |
Mar 19 02:53:59 PM PDT 24 |
96967452 ps |
| T998 |
/workspace/coverage/cover_reg_top/15.spi_device_intr_test.3155732037 |
|
|
Mar 19 02:54:11 PM PDT 24 |
Mar 19 02:54:12 PM PDT 24 |
77151674 ps |
| T109 |
/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3451351486 |
|
|
Mar 19 02:54:02 PM PDT 24 |
Mar 19 02:54:05 PM PDT 24 |
106733937 ps |
| T999 |
/workspace/coverage/cover_reg_top/32.spi_device_intr_test.2743780359 |
|
|
Mar 19 02:54:20 PM PDT 24 |
Mar 19 02:54:22 PM PDT 24 |
51489520 ps |
| T1000 |
/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3919645070 |
|
|
Mar 19 02:54:12 PM PDT 24 |
Mar 19 02:54:14 PM PDT 24 |
81135552 ps |
| T113 |
/workspace/coverage/cover_reg_top/10.spi_device_tl_errors.767401643 |
|
|
Mar 19 02:54:01 PM PDT 24 |
Mar 19 02:54:05 PM PDT 24 |
371203151 ps |
| T1001 |
/workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3723717571 |
|
|
Mar 19 02:53:47 PM PDT 24 |
Mar 19 02:53:48 PM PDT 24 |
13930226 ps |
| T131 |
/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.928261300 |
|
|
Mar 19 02:54:12 PM PDT 24 |
Mar 19 02:54:14 PM PDT 24 |
392564844 ps |
| T1002 |
/workspace/coverage/cover_reg_top/17.spi_device_intr_test.2084741645 |
|
|
Mar 19 02:54:20 PM PDT 24 |
Mar 19 02:54:22 PM PDT 24 |
13522792 ps |
| T1003 |
/workspace/coverage/cover_reg_top/3.spi_device_intr_test.423733912 |
|
|
Mar 19 02:53:46 PM PDT 24 |
Mar 19 02:53:48 PM PDT 24 |
16400387 ps |
| T150 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1001517341 |
|
|
Mar 19 02:53:55 PM PDT 24 |
Mar 19 02:54:00 PM PDT 24 |
160670381 ps |
| T1004 |
/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3236889783 |
|
|
Mar 19 02:54:21 PM PDT 24 |
Mar 19 02:54:25 PM PDT 24 |
271982304 ps |
| T1005 |
/workspace/coverage/cover_reg_top/22.spi_device_intr_test.2691460869 |
|
|
Mar 19 02:54:20 PM PDT 24 |
Mar 19 02:54:21 PM PDT 24 |
28966664 ps |
| T1006 |
/workspace/coverage/cover_reg_top/5.spi_device_intr_test.2850066838 |
|
|
Mar 19 02:53:55 PM PDT 24 |
Mar 19 02:53:55 PM PDT 24 |
20129087 ps |
| T1007 |
/workspace/coverage/cover_reg_top/4.spi_device_intr_test.1556494593 |
|
|
Mar 19 02:53:59 PM PDT 24 |
Mar 19 02:54:00 PM PDT 24 |
11582700 ps |
| T1008 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2709064970 |
|
|
Mar 19 02:53:46 PM PDT 24 |
Mar 19 02:53:48 PM PDT 24 |
56738318 ps |
| T151 |
/workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.4010593209 |
|
|
Mar 19 02:54:10 PM PDT 24 |
Mar 19 02:54:14 PM PDT 24 |
149720031 ps |
| T1009 |
/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1042046056 |
|
|
Mar 19 02:54:12 PM PDT 24 |
Mar 19 02:54:14 PM PDT 24 |
55741984 ps |
| T1010 |
/workspace/coverage/cover_reg_top/48.spi_device_intr_test.4045325608 |
|
|
Mar 19 02:54:26 PM PDT 24 |
Mar 19 02:54:29 PM PDT 24 |
20076637 ps |
| T114 |
/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.4281854328 |
|
|
Mar 19 02:54:22 PM PDT 24 |
Mar 19 02:54:26 PM PDT 24 |
425277846 ps |
| T152 |
/workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3677592374 |
|
|
Mar 19 02:53:40 PM PDT 24 |
Mar 19 02:53:57 PM PDT 24 |
726537730 ps |