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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.95 98.32 94.35 98.61 89.36 97.00 95.84 98.17


Total test records in report: 1092
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T132 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3534057297 Mar 19 02:53:48 PM PDT 24 Mar 19 02:53:50 PM PDT 24 52178488 ps
T1011 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2503777901 Mar 19 02:53:42 PM PDT 24 Mar 19 02:53:44 PM PDT 24 192541541 ps
T153 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3180528110 Mar 19 02:54:21 PM PDT 24 Mar 19 02:54:25 PM PDT 24 243566791 ps
T1012 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2582553629 Mar 19 02:54:27 PM PDT 24 Mar 19 02:54:29 PM PDT 24 29952509 ps
T1013 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.4232585083 Mar 19 02:53:48 PM PDT 24 Mar 19 02:53:51 PM PDT 24 409916950 ps
T248 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3614940432 Mar 19 02:54:16 PM PDT 24 Mar 19 02:54:23 PM PDT 24 109060085 ps
T1014 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1827228126 Mar 19 02:54:03 PM PDT 24 Mar 19 02:54:06 PM PDT 24 99857461 ps
T1015 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2450766275 Mar 19 02:54:02 PM PDT 24 Mar 19 02:54:04 PM PDT 24 69240475 ps
T1016 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2635616558 Mar 19 02:54:05 PM PDT 24 Mar 19 02:54:27 PM PDT 24 1618076008 ps
T249 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1993263503 Mar 19 02:54:11 PM PDT 24 Mar 19 02:54:28 PM PDT 24 282074022 ps
T1017 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.255715108 Mar 19 02:54:20 PM PDT 24 Mar 19 02:54:22 PM PDT 24 107429805 ps
T1018 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2422302891 Mar 19 02:54:26 PM PDT 24 Mar 19 02:54:28 PM PDT 24 14912625 ps
T1019 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1511955625 Mar 19 02:54:22 PM PDT 24 Mar 19 02:54:41 PM PDT 24 6598209802 ps
T1020 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1016836238 Mar 19 02:54:03 PM PDT 24 Mar 19 02:54:06 PM PDT 24 82835039 ps
T115 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.406240144 Mar 19 02:54:13 PM PDT 24 Mar 19 02:54:16 PM PDT 24 76602953 ps
T1021 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.551004691 Mar 19 02:54:21 PM PDT 24 Mar 19 02:54:23 PM PDT 24 42511597 ps
T1022 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.48809232 Mar 19 02:54:03 PM PDT 24 Mar 19 02:54:24 PM PDT 24 901065660 ps
T1023 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.4119216672 Mar 19 02:54:08 PM PDT 24 Mar 19 02:54:13 PM PDT 24 688040511 ps
T1024 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1780662566 Mar 19 02:53:48 PM PDT 24 Mar 19 02:53:50 PM PDT 24 69477014 ps
T133 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3153733520 Mar 19 02:53:48 PM PDT 24 Mar 19 02:54:11 PM PDT 24 1178410792 ps
T245 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2668063314 Mar 19 02:54:23 PM PDT 24 Mar 19 02:54:45 PM PDT 24 1616454142 ps
T1025 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.147617316 Mar 19 02:54:22 PM PDT 24 Mar 19 02:54:27 PM PDT 24 1122714410 ps
T1026 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1874578335 Mar 19 02:54:01 PM PDT 24 Mar 19 02:54:04 PM PDT 24 98202289 ps
T1027 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3919456117 Mar 19 02:54:13 PM PDT 24 Mar 19 02:54:14 PM PDT 24 21088126 ps
T1028 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.816963214 Mar 19 02:54:03 PM PDT 24 Mar 19 02:54:04 PM PDT 24 43030647 ps
T1029 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2937658019 Mar 19 02:54:03 PM PDT 24 Mar 19 02:54:07 PM PDT 24 999344727 ps
T1030 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2847594 Mar 19 02:53:48 PM PDT 24 Mar 19 02:53:49 PM PDT 24 22220836 ps
T1031 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3679791290 Mar 19 02:54:12 PM PDT 24 Mar 19 02:54:13 PM PDT 24 108120057 ps
T1032 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2544954839 Mar 19 02:54:03 PM PDT 24 Mar 19 02:54:04 PM PDT 24 24051698 ps
T1033 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.132832615 Mar 19 02:53:42 PM PDT 24 Mar 19 02:53:45 PM PDT 24 52809094 ps
T1034 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2940531180 Mar 19 02:53:42 PM PDT 24 Mar 19 02:53:43 PM PDT 24 51303929 ps
T134 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.498637972 Mar 19 02:53:40 PM PDT 24 Mar 19 02:53:42 PM PDT 24 71423551 ps
T1035 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.4099825262 Mar 19 02:54:02 PM PDT 24 Mar 19 02:54:04 PM PDT 24 111544023 ps
T1036 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.485929243 Mar 19 02:53:47 PM PDT 24 Mar 19 02:53:52 PM PDT 24 452152767 ps
T1037 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1278529784 Mar 19 02:54:20 PM PDT 24 Mar 19 02:54:23 PM PDT 24 12221195 ps
T1038 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.239702078 Mar 19 02:53:44 PM PDT 24 Mar 19 02:53:46 PM PDT 24 26643516 ps
T1039 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4281840869 Mar 19 02:54:22 PM PDT 24 Mar 19 02:54:24 PM PDT 24 13560089 ps
T1040 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4022938972 Mar 19 02:54:02 PM PDT 24 Mar 19 02:54:05 PM PDT 24 277177251 ps
T1041 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3443454912 Mar 19 02:54:22 PM PDT 24 Mar 19 02:54:24 PM PDT 24 60248607 ps
T1042 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1873370690 Mar 19 02:54:21 PM PDT 24 Mar 19 02:54:24 PM PDT 24 21951224 ps
T1043 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.985019784 Mar 19 02:53:46 PM PDT 24 Mar 19 02:54:12 PM PDT 24 2164047886 ps
T246 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2986631939 Mar 19 02:54:04 PM PDT 24 Mar 19 02:54:11 PM PDT 24 2425821714 ps
T1044 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2365248200 Mar 19 02:54:20 PM PDT 24 Mar 19 02:54:23 PM PDT 24 58802707 ps
T1045 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3147175826 Mar 19 02:53:47 PM PDT 24 Mar 19 02:54:24 PM PDT 24 532389825 ps
T1046 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1639748433 Mar 19 02:54:21 PM PDT 24 Mar 19 02:54:23 PM PDT 24 14824627 ps
T1047 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.815786146 Mar 19 02:54:12 PM PDT 24 Mar 19 02:54:14 PM PDT 24 187928435 ps
T1048 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.618013153 Mar 19 02:54:05 PM PDT 24 Mar 19 02:54:06 PM PDT 24 363841130 ps
T1049 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2812668412 Mar 19 02:54:24 PM PDT 24 Mar 19 02:54:25 PM PDT 24 14413159 ps
T1050 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.961982151 Mar 19 02:53:56 PM PDT 24 Mar 19 02:53:58 PM PDT 24 340856099 ps
T1051 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.222060981 Mar 19 02:53:59 PM PDT 24 Mar 19 02:54:16 PM PDT 24 640104057 ps
T1052 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.508396089 Mar 19 02:54:02 PM PDT 24 Mar 19 02:54:06 PM PDT 24 127747108 ps
T1053 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3890146124 Mar 19 02:54:03 PM PDT 24 Mar 19 02:54:04 PM PDT 24 37604904 ps
T1054 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1876154452 Mar 19 02:54:03 PM PDT 24 Mar 19 02:54:06 PM PDT 24 372325101 ps
T1055 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3461709070 Mar 19 02:53:48 PM PDT 24 Mar 19 02:54:02 PM PDT 24 1645844277 ps
T1056 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1471840201 Mar 19 02:53:57 PM PDT 24 Mar 19 02:54:00 PM PDT 24 173001199 ps
T1057 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2188869571 Mar 19 02:54:25 PM PDT 24 Mar 19 02:54:28 PM PDT 24 40488650 ps
T1058 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2646275831 Mar 19 02:54:13 PM PDT 24 Mar 19 02:54:17 PM PDT 24 128257615 ps
T111 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1021986975 Mar 19 02:54:08 PM PDT 24 Mar 19 02:54:28 PM PDT 24 3177715313 ps
T1059 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2773067013 Mar 19 02:53:55 PM PDT 24 Mar 19 02:53:58 PM PDT 24 126905748 ps
T1060 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.233164272 Mar 19 02:54:02 PM PDT 24 Mar 19 02:54:06 PM PDT 24 318003004 ps
T1061 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2898458994 Mar 19 02:53:41 PM PDT 24 Mar 19 02:53:44 PM PDT 24 816727225 ps
T1062 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2580114664 Mar 19 02:53:43 PM PDT 24 Mar 19 02:53:44 PM PDT 24 12372114 ps
T1063 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.677020045 Mar 19 02:53:54 PM PDT 24 Mar 19 02:54:31 PM PDT 24 1906594077 ps
T1064 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2307427151 Mar 19 02:54:19 PM PDT 24 Mar 19 02:54:21 PM PDT 24 25837347 ps
T1065 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1274961763 Mar 19 02:54:01 PM PDT 24 Mar 19 02:54:05 PM PDT 24 98859677 ps
T1066 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.4135351350 Mar 19 02:53:55 PM PDT 24 Mar 19 02:53:58 PM PDT 24 274772389 ps
T1067 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3130256668 Mar 19 02:54:16 PM PDT 24 Mar 19 02:54:21 PM PDT 24 204604211 ps
T1068 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1602640506 Mar 19 02:54:25 PM PDT 24 Mar 19 02:54:27 PM PDT 24 30421498 ps
T1069 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3370874490 Mar 19 02:53:43 PM PDT 24 Mar 19 02:53:47 PM PDT 24 65408603 ps
T1070 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.734149437 Mar 19 02:53:54 PM PDT 24 Mar 19 02:53:57 PM PDT 24 27606384 ps
T1071 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.582040978 Mar 19 02:53:48 PM PDT 24 Mar 19 02:53:50 PM PDT 24 21463371 ps
T1072 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.311297894 Mar 19 02:54:12 PM PDT 24 Mar 19 02:54:14 PM PDT 24 56807750 ps
T1073 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.4248790311 Mar 19 02:53:48 PM PDT 24 Mar 19 02:53:49 PM PDT 24 18448588 ps
T1074 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1135601479 Mar 19 02:54:27 PM PDT 24 Mar 19 02:54:29 PM PDT 24 14066037 ps
T1075 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.125918200 Mar 19 02:54:00 PM PDT 24 Mar 19 02:54:01 PM PDT 24 12577610 ps
T1076 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2213571858 Mar 19 02:54:23 PM PDT 24 Mar 19 02:54:26 PM PDT 24 202282868 ps
T1077 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3282242766 Mar 19 02:54:14 PM PDT 24 Mar 19 02:54:18 PM PDT 24 543184419 ps
T1078 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1494300016 Mar 19 02:54:21 PM PDT 24 Mar 19 02:54:23 PM PDT 24 32882041 ps
T1079 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2474853498 Mar 19 02:53:55 PM PDT 24 Mar 19 02:53:59 PM PDT 24 489242829 ps
T1080 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.970517610 Mar 19 02:54:18 PM PDT 24 Mar 19 02:54:20 PM PDT 24 36078553 ps
T1081 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1137025912 Mar 19 02:54:02 PM PDT 24 Mar 19 02:54:05 PM PDT 24 138672715 ps
T1082 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2998913611 Mar 19 02:54:05 PM PDT 24 Mar 19 02:54:08 PM PDT 24 234488729 ps
T1083 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1704490451 Mar 19 02:53:55 PM PDT 24 Mar 19 02:53:58 PM PDT 24 55344661 ps
T1084 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.484484666 Mar 19 02:53:53 PM PDT 24 Mar 19 02:53:57 PM PDT 24 238706101 ps
T1085 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.847257094 Mar 19 02:53:48 PM PDT 24 Mar 19 02:53:51 PM PDT 24 179317921 ps
T1086 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1332826081 Mar 19 02:53:48 PM PDT 24 Mar 19 02:53:57 PM PDT 24 627953687 ps
T1087 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.983379795 Mar 19 02:54:20 PM PDT 24 Mar 19 02:54:22 PM PDT 24 34320667 ps
T1088 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1402506881 Mar 19 02:54:21 PM PDT 24 Mar 19 02:54:23 PM PDT 24 56509327 ps
T1089 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1898121553 Mar 19 02:54:01 PM PDT 24 Mar 19 02:54:04 PM PDT 24 54469396 ps
T1090 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2845635045 Mar 19 02:53:56 PM PDT 24 Mar 19 02:54:06 PM PDT 24 297861751 ps
T1091 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2882915804 Mar 19 02:54:12 PM PDT 24 Mar 19 02:54:29 PM PDT 24 705109081 ps
T1092 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1966926887 Mar 19 02:54:08 PM PDT 24 Mar 19 02:54:09 PM PDT 24 47189140 ps

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.492361702
Short name T2
Test name
Test status
Simulation time 159838717505 ps
CPU time 239.61 seconds
Started Mar 19 01:13:29 PM PDT 24
Finished Mar 19 01:17:29 PM PDT 24
Peak memory 255372 kb
Host smart-28a326fe-5be5-4b53-960d-d6ad37dcef7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492361702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
492361702
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.335267069
Short name T31
Test name
Test status
Simulation time 544384970777 ps
CPU time 589.66 seconds
Started Mar 19 01:15:10 PM PDT 24
Finished Mar 19 01:25:00 PM PDT 24
Peak memory 254468 kb
Host smart-0c0cbe4c-1bba-480c-a41a-9325afe215f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335267069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.335267069
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3111180844
Short name T44
Test name
Test status
Simulation time 4888183766 ps
CPU time 76.36 seconds
Started Mar 19 01:17:50 PM PDT 24
Finished Mar 19 01:19:06 PM PDT 24
Peak memory 253552 kb
Host smart-7e1a67cb-201e-48f8-a97f-757b97d6c083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111180844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3111180844
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1234429896
Short name T104
Test name
Test status
Simulation time 656807688 ps
CPU time 2.84 seconds
Started Mar 19 02:54:12 PM PDT 24
Finished Mar 19 02:54:15 PM PDT 24
Peak memory 216184 kb
Host smart-d6ef8d60-7c53-4ee8-b8d5-e55af53e68cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234429896 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1234429896
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.748998652
Short name T70
Test name
Test status
Simulation time 17219007266 ps
CPU time 173.95 seconds
Started Mar 19 01:17:55 PM PDT 24
Finished Mar 19 01:20:49 PM PDT 24
Peak memory 261980 kb
Host smart-0b3d0e1a-7f12-4e35-b8b9-fddcd8c89685
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748998652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stres
s_all.748998652
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1119440384
Short name T23
Test name
Test status
Simulation time 27706816777 ps
CPU time 198.43 seconds
Started Mar 19 01:19:21 PM PDT 24
Finished Mar 19 01:22:40 PM PDT 24
Peak memory 272780 kb
Host smart-015128ec-b114-4768-a7e8-52015af3dc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119440384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1119440384
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2289815243
Short name T15
Test name
Test status
Simulation time 2707229249 ps
CPU time 16.55 seconds
Started Mar 19 01:18:49 PM PDT 24
Finished Mar 19 01:19:05 PM PDT 24
Peak memory 215832 kb
Host smart-ceb73272-22aa-48e6-8c55-4cd7585f20f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289815243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2289815243
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.1875893577
Short name T73
Test name
Test status
Simulation time 82987998 ps
CPU time 0.74 seconds
Started Mar 19 01:14:41 PM PDT 24
Finished Mar 19 01:14:42 PM PDT 24
Peak memory 215760 kb
Host smart-4d32472c-fa2b-4ea6-b589-d38157d7b742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875893577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.1875893577
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1843573045
Short name T45
Test name
Test status
Simulation time 17142271522 ps
CPU time 94.48 seconds
Started Mar 19 01:16:03 PM PDT 24
Finished Mar 19 01:17:37 PM PDT 24
Peak memory 255592 kb
Host smart-b1db93cc-cc9d-421e-a62b-51cd326ef13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843573045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1843573045
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.578447898
Short name T21
Test name
Test status
Simulation time 317913466313 ps
CPU time 574.72 seconds
Started Mar 19 01:17:41 PM PDT 24
Finished Mar 19 01:27:16 PM PDT 24
Peak memory 272956 kb
Host smart-d6a248ad-98fa-4e93-9973-4b261c7fbe5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578447898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.578447898
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.634400691
Short name T64
Test name
Test status
Simulation time 454339548 ps
CPU time 1.21 seconds
Started Mar 19 01:12:51 PM PDT 24
Finished Mar 19 01:12:52 PM PDT 24
Peak memory 234636 kb
Host smart-c6e5531a-0907-4a60-8e1a-bc5ce30e7975
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634400691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.634400691
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2805230540
Short name T32
Test name
Test status
Simulation time 14540836661 ps
CPU time 177.61 seconds
Started Mar 19 01:19:08 PM PDT 24
Finished Mar 19 01:22:05 PM PDT 24
Peak memory 266612 kb
Host smart-0847c1ca-3ad3-4f34-8437-8e2b0e7226dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805230540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2805230540
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1599603531
Short name T36
Test name
Test status
Simulation time 32832586624 ps
CPU time 44.83 seconds
Started Mar 19 01:19:01 PM PDT 24
Finished Mar 19 01:19:46 PM PDT 24
Peak memory 232200 kb
Host smart-6d5d8633-0157-4c20-b088-f8dcd2b8ee95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599603531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1599603531
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1937107473
Short name T46
Test name
Test status
Simulation time 58033980244 ps
CPU time 496.48 seconds
Started Mar 19 01:19:16 PM PDT 24
Finished Mar 19 01:27:33 PM PDT 24
Peak memory 282700 kb
Host smart-004a529d-4db4-4305-8e4a-b431b3cae9ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937107473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1937107473
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2625503059
Short name T119
Test name
Test status
Simulation time 2140695680 ps
CPU time 18.77 seconds
Started Mar 19 02:53:55 PM PDT 24
Finished Mar 19 02:54:15 PM PDT 24
Peak memory 223192 kb
Host smart-4849846a-dd25-4efd-9ad6-315f4acc854d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625503059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2625503059
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2607684871
Short name T186
Test name
Test status
Simulation time 98587166207 ps
CPU time 353.49 seconds
Started Mar 19 01:15:29 PM PDT 24
Finished Mar 19 01:21:22 PM PDT 24
Peak memory 272720 kb
Host smart-ef13aa16-e529-4d64-8461-b6dc435a5ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607684871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2607684871
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1906099489
Short name T129
Test name
Test status
Simulation time 422788088 ps
CPU time 13.66 seconds
Started Mar 19 02:53:42 PM PDT 24
Finished Mar 19 02:53:56 PM PDT 24
Peak memory 215028 kb
Host smart-8cc4d556-4f45-4580-9744-d87c3ba01b93
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906099489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1906099489
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2611691432
Short name T108
Test name
Test status
Simulation time 238483945 ps
CPU time 4.83 seconds
Started Mar 19 02:53:42 PM PDT 24
Finished Mar 19 02:53:47 PM PDT 24
Peak memory 215264 kb
Host smart-ec66b16c-c252-4f35-a946-58b90690a23a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611691432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
611691432
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.246555358
Short name T192
Test name
Test status
Simulation time 15256410851 ps
CPU time 168.39 seconds
Started Mar 19 01:17:58 PM PDT 24
Finished Mar 19 01:20:46 PM PDT 24
Peak memory 266092 kb
Host smart-785554df-d3b7-462e-adad-9a6b71010b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246555358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.246555358
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2473795100
Short name T42
Test name
Test status
Simulation time 7239270622 ps
CPU time 71.29 seconds
Started Mar 19 01:17:24 PM PDT 24
Finished Mar 19 01:18:36 PM PDT 24
Peak memory 248808 kb
Host smart-dfd63d9b-6f07-49e4-9977-aaf37043616e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473795100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2473795100
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3428346940
Short name T20
Test name
Test status
Simulation time 581949292736 ps
CPU time 529.31 seconds
Started Mar 19 01:17:13 PM PDT 24
Finished Mar 19 01:26:02 PM PDT 24
Peak memory 256952 kb
Host smart-a9544823-80e6-40dd-84d3-2e22d8a51edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428346940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3428346940
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.43966224
Short name T16
Test name
Test status
Simulation time 4517267886 ps
CPU time 5.42 seconds
Started Mar 19 01:12:43 PM PDT 24
Finished Mar 19 01:12:49 PM PDT 24
Peak memory 215828 kb
Host smart-d27c26a1-f6f5-4feb-aa5d-9439164bbd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43966224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.43966224
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.492328948
Short name T230
Test name
Test status
Simulation time 8657836961 ps
CPU time 157.01 seconds
Started Mar 19 01:14:04 PM PDT 24
Finished Mar 19 01:16:41 PM PDT 24
Peak memory 281524 kb
Host smart-ff3e51ec-38c3-4059-81b0-93d99d83b811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492328948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
492328948
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.890112334
Short name T28
Test name
Test status
Simulation time 6273083211 ps
CPU time 82.01 seconds
Started Mar 19 01:17:23 PM PDT 24
Finished Mar 19 01:18:46 PM PDT 24
Peak memory 256892 kb
Host smart-92ee3e05-7241-4b73-9cb0-dac91842c877
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890112334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.890112334
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1606522052
Short name T352
Test name
Test status
Simulation time 42302527 ps
CPU time 0.76 seconds
Started Mar 19 01:15:18 PM PDT 24
Finished Mar 19 01:15:19 PM PDT 24
Peak memory 204888 kb
Host smart-33d204f9-b2cc-4034-b8c9-73a483b64ba8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606522052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1606522052
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3367469974
Short name T226
Test name
Test status
Simulation time 113494173743 ps
CPU time 222.77 seconds
Started Mar 19 01:14:56 PM PDT 24
Finished Mar 19 01:18:38 PM PDT 24
Peak memory 264940 kb
Host smart-c216f9c4-ac79-4760-946c-39e01323bca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367469974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3367469974
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2269889722
Short name T138
Test name
Test status
Simulation time 28003199382 ps
CPU time 219.69 seconds
Started Mar 19 01:15:18 PM PDT 24
Finished Mar 19 01:18:58 PM PDT 24
Peak memory 256900 kb
Host smart-69e0eef8-5a78-46f1-9cc4-c1b4276434e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269889722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2269889722
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2974693952
Short name T196
Test name
Test status
Simulation time 453377040397 ps
CPU time 710.71 seconds
Started Mar 19 01:16:05 PM PDT 24
Finished Mar 19 01:27:57 PM PDT 24
Peak memory 266064 kb
Host smart-59964220-2f46-485e-b2ac-0c8eb73783d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974693952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2974693952
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.936188221
Short name T189
Test name
Test status
Simulation time 3408559532 ps
CPU time 8.58 seconds
Started Mar 19 01:17:10 PM PDT 24
Finished Mar 19 01:17:19 PM PDT 24
Peak memory 230536 kb
Host smart-1888b6b8-9ace-4373-891b-7b215abf7b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936188221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.936188221
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3041459258
Short name T139
Test name
Test status
Simulation time 309855816712 ps
CPU time 488.78 seconds
Started Mar 19 01:18:32 PM PDT 24
Finished Mar 19 01:26:41 PM PDT 24
Peak memory 248760 kb
Host smart-d7792841-b1bf-48ab-ba7d-b2da26a79b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041459258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3041459258
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2701394021
Short name T110
Test name
Test status
Simulation time 1993618083 ps
CPU time 3.34 seconds
Started Mar 19 02:53:54 PM PDT 24
Finished Mar 19 02:53:58 PM PDT 24
Peak memory 215272 kb
Host smart-91a24fec-8846-4c6d-87ec-adc40f444820
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701394021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
701394021
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1993263503
Short name T249
Test name
Test status
Simulation time 282074022 ps
CPU time 16.76 seconds
Started Mar 19 02:54:11 PM PDT 24
Finished Mar 19 02:54:28 PM PDT 24
Peak memory 215132 kb
Host smart-e65b81fc-56c8-40cd-a0b3-bfbabe39c4e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993263503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1993263503
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1774089007
Short name T270
Test name
Test status
Simulation time 2213641456 ps
CPU time 16.08 seconds
Started Mar 19 01:17:39 PM PDT 24
Finished Mar 19 01:17:56 PM PDT 24
Peak memory 232300 kb
Host smart-bd0e4721-8094-4f86-85c6-dc28fb9a12e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774089007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1774089007
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1424394573
Short name T180
Test name
Test status
Simulation time 232530259172 ps
CPU time 272.94 seconds
Started Mar 19 01:17:53 PM PDT 24
Finished Mar 19 01:22:26 PM PDT 24
Peak memory 239356 kb
Host smart-c3366ae5-2386-4f67-933c-0176ec58eb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424394573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1424394573
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2736954934
Short name T12
Test name
Test status
Simulation time 3669364790 ps
CPU time 12.32 seconds
Started Mar 19 01:13:53 PM PDT 24
Finished Mar 19 01:14:05 PM PDT 24
Peak memory 233188 kb
Host smart-461beb54-c840-4600-a08f-ecc2d0437e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736954934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2736954934
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3543340703
Short name T96
Test name
Test status
Simulation time 313075725190 ps
CPU time 420.01 seconds
Started Mar 19 01:16:20 PM PDT 24
Finished Mar 19 01:23:21 PM PDT 24
Peak memory 250792 kb
Host smart-54cd3c6d-9226-4acd-9d50-810c8d6cd429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543340703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3543340703
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1021986975
Short name T111
Test name
Test status
Simulation time 3177715313 ps
CPU time 20.16 seconds
Started Mar 19 02:54:08 PM PDT 24
Finished Mar 19 02:54:28 PM PDT 24
Peak memory 215228 kb
Host smart-0c650b98-fc70-4c4a-826a-6570cb4ef556
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021986975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1021986975
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.406240144
Short name T115
Test name
Test status
Simulation time 76602953 ps
CPU time 2.23 seconds
Started Mar 19 02:54:13 PM PDT 24
Finished Mar 19 02:54:16 PM PDT 24
Peak memory 215192 kb
Host smart-d9afcff4-778a-4e66-b88b-b02445e44db5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406240144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.406240144
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1437215660
Short name T65
Test name
Test status
Simulation time 1450447772 ps
CPU time 12.47 seconds
Started Mar 19 02:54:20 PM PDT 24
Finished Mar 19 02:54:33 PM PDT 24
Peak memory 215136 kb
Host smart-381529cc-6b69-4d05-b5d1-1d819d920098
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437215660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1437215660
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.395333487
Short name T657
Test name
Test status
Simulation time 8496222453 ps
CPU time 113.41 seconds
Started Mar 19 01:12:42 PM PDT 24
Finished Mar 19 01:14:36 PM PDT 24
Peak memory 265032 kb
Host smart-6d97cede-3c5f-4344-bdd2-bd21ddcb7450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395333487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.395333487
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2714716441
Short name T236
Test name
Test status
Simulation time 15284181657 ps
CPU time 96.47 seconds
Started Mar 19 01:15:47 PM PDT 24
Finished Mar 19 01:17:24 PM PDT 24
Peak memory 254992 kb
Host smart-db8d42db-b333-463e-a5b2-cf24d50d20d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714716441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2714716441
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.3095027323
Short name T193
Test name
Test status
Simulation time 16006353082 ps
CPU time 87.71 seconds
Started Mar 19 01:14:31 PM PDT 24
Finished Mar 19 01:15:59 PM PDT 24
Peak memory 251856 kb
Host smart-1632c19d-7a1a-48c4-ac28-c982dcac1d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095027323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3095027323
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3499386765
Short name T172
Test name
Test status
Simulation time 117019226 ps
CPU time 2.64 seconds
Started Mar 19 01:13:05 PM PDT 24
Finished Mar 19 01:13:08 PM PDT 24
Peak memory 216892 kb
Host smart-f5fd75f2-7dd4-4325-a09e-1a4583424c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499386765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3499386765
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2534768941
Short name T90
Test name
Test status
Simulation time 46882592 ps
CPU time 0.97 seconds
Started Mar 19 02:53:41 PM PDT 24
Finished Mar 19 02:53:42 PM PDT 24
Peak memory 206532 kb
Host smart-59a424c3-7656-405f-ac86-e80f936ab0e4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534768941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2534768941
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3370874490
Short name T1069
Test name
Test status
Simulation time 65408603 ps
CPU time 3.82 seconds
Started Mar 19 02:53:43 PM PDT 24
Finished Mar 19 02:53:47 PM PDT 24
Peak memory 215328 kb
Host smart-9c96a885-8d2e-450a-b670-2ced45debbf7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370874490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
370874490
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3562362251
Short name T987
Test name
Test status
Simulation time 1238048148 ps
CPU time 8.6 seconds
Started Mar 19 02:53:40 PM PDT 24
Finished Mar 19 02:53:50 PM PDT 24
Peak memory 206820 kb
Host smart-dba61c19-4ea8-43ad-bd02-6cc49b272c06
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562362251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3562362251
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1526422894
Short name T975
Test name
Test status
Simulation time 13400694335 ps
CPU time 26.79 seconds
Started Mar 19 02:53:43 PM PDT 24
Finished Mar 19 02:54:10 PM PDT 24
Peak memory 215148 kb
Host smart-f4733de9-f7a8-461f-8d41-f3a05a6d267f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526422894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1526422894
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2940531180
Short name T1034
Test name
Test status
Simulation time 51303929 ps
CPU time 0.92 seconds
Started Mar 19 02:53:42 PM PDT 24
Finished Mar 19 02:53:43 PM PDT 24
Peak memory 206692 kb
Host smart-a8a8c5ef-2c15-4100-9564-29c5baa49b84
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940531180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2940531180
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.132832615
Short name T1033
Test name
Test status
Simulation time 52809094 ps
CPU time 1.95 seconds
Started Mar 19 02:53:42 PM PDT 24
Finished Mar 19 02:53:45 PM PDT 24
Peak memory 216188 kb
Host smart-b98031fa-21ca-4c67-b70f-5695f695c4ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132832615 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.132832615
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.239702078
Short name T1038
Test name
Test status
Simulation time 26643516 ps
CPU time 1.83 seconds
Started Mar 19 02:53:44 PM PDT 24
Finished Mar 19 02:53:46 PM PDT 24
Peak memory 215020 kb
Host smart-03688d65-9103-4834-9f4c-e49095f1e596
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239702078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.239702078
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1717285334
Short name T993
Test name
Test status
Simulation time 22398073 ps
CPU time 0.71 seconds
Started Mar 19 02:53:42 PM PDT 24
Finished Mar 19 02:53:43 PM PDT 24
Peak memory 203440 kb
Host smart-7bfb7284-9ca9-48e4-9b52-7031602f76df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717285334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
717285334
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.498637972
Short name T134
Test name
Test status
Simulation time 71423551 ps
CPU time 2.21 seconds
Started Mar 19 02:53:40 PM PDT 24
Finished Mar 19 02:53:42 PM PDT 24
Peak memory 215172 kb
Host smart-0eb56171-ccc6-4843-8bd3-a47608df2654
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498637972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.498637972
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2292041831
Short name T973
Test name
Test status
Simulation time 13400456 ps
CPU time 0.66 seconds
Started Mar 19 02:53:44 PM PDT 24
Finished Mar 19 02:53:45 PM PDT 24
Peak memory 203356 kb
Host smart-5a3e1432-be31-4e70-973f-7ac38fabf1c0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292041831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2292041831
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2503777901
Short name T1011
Test name
Test status
Simulation time 192541541 ps
CPU time 1.91 seconds
Started Mar 19 02:53:42 PM PDT 24
Finished Mar 19 02:53:44 PM PDT 24
Peak memory 206888 kb
Host smart-5be09c68-d818-4d10-856b-590ffdd68e08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503777901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2503777901
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3677592374
Short name T152
Test name
Test status
Simulation time 726537730 ps
CPU time 16.67 seconds
Started Mar 19 02:53:40 PM PDT 24
Finished Mar 19 02:53:57 PM PDT 24
Peak memory 215104 kb
Host smart-5953d6bd-0b4b-4242-969c-1ed9273a5f8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677592374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3677592374
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2801889392
Short name T982
Test name
Test status
Simulation time 1453971378 ps
CPU time 23 seconds
Started Mar 19 02:53:43 PM PDT 24
Finished Mar 19 02:54:06 PM PDT 24
Peak memory 206784 kb
Host smart-7e7b0649-9b9b-48e7-9551-a8c7105878a7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801889392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2801889392
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.847257094
Short name T1085
Test name
Test status
Simulation time 179317921 ps
CPU time 1.7 seconds
Started Mar 19 02:53:48 PM PDT 24
Finished Mar 19 02:53:51 PM PDT 24
Peak memory 216220 kb
Host smart-f0dd8b9f-f489-453a-8942-e08d8f64e59c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847257094 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.847257094
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1333996337
Short name T125
Test name
Test status
Simulation time 30135345 ps
CPU time 1.74 seconds
Started Mar 19 02:53:43 PM PDT 24
Finished Mar 19 02:53:45 PM PDT 24
Peak memory 215008 kb
Host smart-85253761-92e9-4cb7-a1c7-488bbcc591ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333996337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
333996337
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2580114664
Short name T1062
Test name
Test status
Simulation time 12372114 ps
CPU time 0.7 seconds
Started Mar 19 02:53:43 PM PDT 24
Finished Mar 19 02:53:44 PM PDT 24
Peak memory 203516 kb
Host smart-1dff41d5-5efd-4844-9404-f26462719e47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580114664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
580114664
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.913925676
Short name T122
Test name
Test status
Simulation time 37138247 ps
CPU time 1.34 seconds
Started Mar 19 02:53:44 PM PDT 24
Finished Mar 19 02:53:46 PM PDT 24
Peak memory 215028 kb
Host smart-e76a4307-63f2-4704-9f68-369fc6998de1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913925676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.913925676
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1980161968
Short name T986
Test name
Test status
Simulation time 12899138 ps
CPU time 0.71 seconds
Started Mar 19 02:53:41 PM PDT 24
Finished Mar 19 02:53:42 PM PDT 24
Peak memory 203336 kb
Host smart-9241b5f0-c220-498a-8f15-99f1bc657b5b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980161968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.1980161968
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2898458994
Short name T1061
Test name
Test status
Simulation time 816727225 ps
CPU time 2.8 seconds
Started Mar 19 02:53:41 PM PDT 24
Finished Mar 19 02:53:44 PM PDT 24
Peak memory 215084 kb
Host smart-5e0ebe59-ef56-4090-a56f-1afd29ebcc98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898458994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2898458994
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2377633812
Short name T103
Test name
Test status
Simulation time 11291148481 ps
CPU time 22.2 seconds
Started Mar 19 02:53:40 PM PDT 24
Finished Mar 19 02:54:02 PM PDT 24
Peak memory 215480 kb
Host smart-2af542eb-138c-46a0-95d1-79a8aa110a44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377633812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2377633812
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.4099825262
Short name T1035
Test name
Test status
Simulation time 111544023 ps
CPU time 1.9 seconds
Started Mar 19 02:54:02 PM PDT 24
Finished Mar 19 02:54:04 PM PDT 24
Peak memory 215152 kb
Host smart-c4101cf9-34cf-4a63-bb94-5e109a27cb77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099825262 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.4099825262
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1876154452
Short name T1054
Test name
Test status
Simulation time 372325101 ps
CPU time 2.68 seconds
Started Mar 19 02:54:03 PM PDT 24
Finished Mar 19 02:54:06 PM PDT 24
Peak memory 206840 kb
Host smart-d564c20f-d64f-4128-bc54-582cd667fe49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876154452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1876154452
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.125918200
Short name T1075
Test name
Test status
Simulation time 12577610 ps
CPU time 0.78 seconds
Started Mar 19 02:54:00 PM PDT 24
Finished Mar 19 02:54:01 PM PDT 24
Peak memory 203472 kb
Host smart-41453b4b-665b-4c5f-a802-4d09043d9c11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125918200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.125918200
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1898121553
Short name T1089
Test name
Test status
Simulation time 54469396 ps
CPU time 2.72 seconds
Started Mar 19 02:54:01 PM PDT 24
Finished Mar 19 02:54:04 PM PDT 24
Peak memory 215068 kb
Host smart-89070852-4fe5-4378-87f0-72469efe0095
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898121553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1898121553
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.767401643
Short name T113
Test name
Test status
Simulation time 371203151 ps
CPU time 3.6 seconds
Started Mar 19 02:54:01 PM PDT 24
Finished Mar 19 02:54:05 PM PDT 24
Peak memory 215328 kb
Host smart-7bda5e33-a2fb-46d8-8c1b-b7b0718853b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767401643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.767401643
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.48809232
Short name T1022
Test name
Test status
Simulation time 901065660 ps
CPU time 20.43 seconds
Started Mar 19 02:54:03 PM PDT 24
Finished Mar 19 02:54:24 PM PDT 24
Peak memory 215148 kb
Host smart-03766f03-538e-49d3-a922-9aca12863903
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48809232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_
tl_intg_err.48809232
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1274961763
Short name T1065
Test name
Test status
Simulation time 98859677 ps
CPU time 3.73 seconds
Started Mar 19 02:54:01 PM PDT 24
Finished Mar 19 02:54:05 PM PDT 24
Peak memory 216924 kb
Host smart-5b8503ca-c952-49bb-b97d-3fb2f4764e37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274961763 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1274961763
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.618013153
Short name T1048
Test name
Test status
Simulation time 363841130 ps
CPU time 1.29 seconds
Started Mar 19 02:54:05 PM PDT 24
Finished Mar 19 02:54:06 PM PDT 24
Peak memory 215076 kb
Host smart-3c4d1c91-9e33-4560-9f8f-fa5dd38feebc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618013153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.618013153
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.650574408
Short name T991
Test name
Test status
Simulation time 105305376 ps
CPU time 0.75 seconds
Started Mar 19 02:54:08 PM PDT 24
Finished Mar 19 02:54:09 PM PDT 24
Peak memory 203512 kb
Host smart-15bf5133-4f97-43dc-b7e7-b5ab897de589
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650574408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.650574408
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2643465468
Short name T148
Test name
Test status
Simulation time 129072317 ps
CPU time 3.18 seconds
Started Mar 19 02:54:05 PM PDT 24
Finished Mar 19 02:54:09 PM PDT 24
Peak memory 215128 kb
Host smart-13ac83ef-5b0d-46e4-8651-f586e007a09f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643465468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2643465468
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3451351486
Short name T109
Test name
Test status
Simulation time 106733937 ps
CPU time 2.86 seconds
Started Mar 19 02:54:02 PM PDT 24
Finished Mar 19 02:54:05 PM PDT 24
Peak memory 215236 kb
Host smart-e06c69b2-65d1-421a-b226-29300c161858
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451351486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3451351486
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3919645070
Short name T1000
Test name
Test status
Simulation time 81135552 ps
CPU time 1.63 seconds
Started Mar 19 02:54:12 PM PDT 24
Finished Mar 19 02:54:14 PM PDT 24
Peak memory 215192 kb
Host smart-0cbab5f6-4d6c-4664-99d0-0c5a344d4e51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919645070 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3919645070
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.928261300
Short name T131
Test name
Test status
Simulation time 392564844 ps
CPU time 2.07 seconds
Started Mar 19 02:54:12 PM PDT 24
Finished Mar 19 02:54:14 PM PDT 24
Peak memory 215132 kb
Host smart-359edbd4-f3be-46f2-b5c2-f575be777b3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928261300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.928261300
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1149369537
Short name T970
Test name
Test status
Simulation time 13637619 ps
CPU time 0.74 seconds
Started Mar 19 02:54:13 PM PDT 24
Finished Mar 19 02:54:14 PM PDT 24
Peak memory 203444 kb
Host smart-9db365a5-97d0-4645-a561-5838205b4f70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149369537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1149369537
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.69339708
Short name T995
Test name
Test status
Simulation time 25739195 ps
CPU time 1.76 seconds
Started Mar 19 02:54:10 PM PDT 24
Finished Mar 19 02:54:12 PM PDT 24
Peak memory 206900 kb
Host smart-79c1b9a8-6e0b-4fa4-9495-8ab30158fd7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69339708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sp
i_device_same_csr_outstanding.69339708
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2882915804
Short name T1091
Test name
Test status
Simulation time 705109081 ps
CPU time 16.29 seconds
Started Mar 19 02:54:12 PM PDT 24
Finished Mar 19 02:54:29 PM PDT 24
Peak memory 215152 kb
Host smart-a2da74c7-0b65-46a8-9389-e713cb351c4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882915804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2882915804
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3971489737
Short name T121
Test name
Test status
Simulation time 213490094 ps
CPU time 1.88 seconds
Started Mar 19 02:54:41 PM PDT 24
Finished Mar 19 02:54:43 PM PDT 24
Peak memory 206856 kb
Host smart-45730f17-2059-4fb4-a143-f2aaea69232c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971489737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3971489737
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3919456117
Short name T1027
Test name
Test status
Simulation time 21088126 ps
CPU time 0.74 seconds
Started Mar 19 02:54:13 PM PDT 24
Finished Mar 19 02:54:14 PM PDT 24
Peak memory 203472 kb
Host smart-be253eeb-72cd-4ff4-be16-6a45e5502b08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919456117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3919456117
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2290489259
Short name T146
Test name
Test status
Simulation time 608756970 ps
CPU time 4.35 seconds
Started Mar 19 02:54:12 PM PDT 24
Finished Mar 19 02:54:16 PM PDT 24
Peak memory 215032 kb
Host smart-6e9f2146-c295-4722-9231-e53d3cf208fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290489259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2290489259
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3282242766
Short name T1077
Test name
Test status
Simulation time 543184419 ps
CPU time 3.58 seconds
Started Mar 19 02:54:14 PM PDT 24
Finished Mar 19 02:54:18 PM PDT 24
Peak memory 215336 kb
Host smart-39f5ec8e-26f2-46d9-8105-5d9657f98430
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282242766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3282242766
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.4130097793
Short name T120
Test name
Test status
Simulation time 306001454 ps
CPU time 18.05 seconds
Started Mar 19 02:54:12 PM PDT 24
Finished Mar 19 02:54:31 PM PDT 24
Peak memory 215220 kb
Host smart-a91dd563-6351-449d-bc98-232a6f0015ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130097793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.4130097793
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1740963498
Short name T112
Test name
Test status
Simulation time 133272074 ps
CPU time 3.9 seconds
Started Mar 19 02:54:12 PM PDT 24
Finished Mar 19 02:54:17 PM PDT 24
Peak memory 217004 kb
Host smart-e8776b69-f419-4fec-b4c7-3ced76dfa0ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740963498 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1740963498
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1042046056
Short name T1009
Test name
Test status
Simulation time 55741984 ps
CPU time 1.94 seconds
Started Mar 19 02:54:12 PM PDT 24
Finished Mar 19 02:54:14 PM PDT 24
Peak memory 215048 kb
Host smart-af73d46f-1c30-4b88-be53-d78f9fbcacdd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042046056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1042046056
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.314744288
Short name T983
Test name
Test status
Simulation time 17654520 ps
CPU time 0.69 seconds
Started Mar 19 02:54:13 PM PDT 24
Finished Mar 19 02:54:14 PM PDT 24
Peak memory 203456 kb
Host smart-fdfe12df-c0d5-4156-9156-eee382c24918
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314744288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.314744288
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3130256668
Short name T1067
Test name
Test status
Simulation time 204604211 ps
CPU time 4.28 seconds
Started Mar 19 02:54:16 PM PDT 24
Finished Mar 19 02:54:21 PM PDT 24
Peak memory 215084 kb
Host smart-c4a54fbb-7fed-41dd-89b5-4ed286767457
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130256668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3130256668
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2113653143
Short name T117
Test name
Test status
Simulation time 258623256 ps
CPU time 2.08 seconds
Started Mar 19 02:54:12 PM PDT 24
Finished Mar 19 02:54:14 PM PDT 24
Peak memory 215224 kb
Host smart-144d3623-496a-4119-b4dd-4f3bfbab13cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113653143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2113653143
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1950775766
Short name T994
Test name
Test status
Simulation time 847638587 ps
CPU time 12 seconds
Started Mar 19 02:54:12 PM PDT 24
Finished Mar 19 02:54:24 PM PDT 24
Peak memory 215052 kb
Host smart-7eb34814-3c3c-4acc-b11f-091b07e780b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950775766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1950775766
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2646275831
Short name T1058
Test name
Test status
Simulation time 128257615 ps
CPU time 3.88 seconds
Started Mar 19 02:54:13 PM PDT 24
Finished Mar 19 02:54:17 PM PDT 24
Peak memory 217044 kb
Host smart-070674e1-28f0-4dc9-ac2a-7d89ae3dee16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646275831 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2646275831
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1602335646
Short name T126
Test name
Test status
Simulation time 110958202 ps
CPU time 1.76 seconds
Started Mar 19 02:54:14 PM PDT 24
Finished Mar 19 02:54:16 PM PDT 24
Peak memory 215040 kb
Host smart-04cedb77-59c1-43d2-9277-35de3c71529e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602335646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1602335646
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3155732037
Short name T998
Test name
Test status
Simulation time 77151674 ps
CPU time 0.67 seconds
Started Mar 19 02:54:11 PM PDT 24
Finished Mar 19 02:54:12 PM PDT 24
Peak memory 203504 kb
Host smart-f2f5f503-3cce-42b6-be82-99412c438e40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155732037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3155732037
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.311297894
Short name T1072
Test name
Test status
Simulation time 56807750 ps
CPU time 1.83 seconds
Started Mar 19 02:54:12 PM PDT 24
Finished Mar 19 02:54:14 PM PDT 24
Peak memory 206944 kb
Host smart-14bc35cf-c2cf-4f24-af7d-2001b7e0023a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311297894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.311297894
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.91041828
Short name T105
Test name
Test status
Simulation time 150145641 ps
CPU time 3.66 seconds
Started Mar 19 02:54:12 PM PDT 24
Finished Mar 19 02:54:16 PM PDT 24
Peak memory 215352 kb
Host smart-708c55c9-79d1-4bee-8260-e7c318df85e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91041828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.91041828
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3236889783
Short name T1004
Test name
Test status
Simulation time 271982304 ps
CPU time 2.5 seconds
Started Mar 19 02:54:21 PM PDT 24
Finished Mar 19 02:54:25 PM PDT 24
Peak memory 216312 kb
Host smart-ab334168-acf9-40dd-a9ea-47455adc7fab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236889783 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3236889783
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.815786146
Short name T1047
Test name
Test status
Simulation time 187928435 ps
CPU time 1.52 seconds
Started Mar 19 02:54:12 PM PDT 24
Finished Mar 19 02:54:14 PM PDT 24
Peak memory 206916 kb
Host smart-ad3a77cc-525c-40f9-9fdc-8c3db070e801
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815786146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.815786146
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3679791290
Short name T1031
Test name
Test status
Simulation time 108120057 ps
CPU time 0.72 seconds
Started Mar 19 02:54:12 PM PDT 24
Finished Mar 19 02:54:13 PM PDT 24
Peak memory 203560 kb
Host smart-144133e0-84be-4376-ae29-5c379ddf7637
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679791290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3679791290
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.147617316
Short name T1025
Test name
Test status
Simulation time 1122714410 ps
CPU time 4.31 seconds
Started Mar 19 02:54:22 PM PDT 24
Finished Mar 19 02:54:27 PM PDT 24
Peak memory 215096 kb
Host smart-6fabcb37-035e-4c7c-9147-e84520db6eed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147617316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.147617316
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1904998218
Short name T106
Test name
Test status
Simulation time 125562139 ps
CPU time 4.02 seconds
Started Mar 19 02:54:11 PM PDT 24
Finished Mar 19 02:54:15 PM PDT 24
Peak memory 215272 kb
Host smart-85e6110e-4cd2-44ea-9a95-cb98345f453a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904998218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1904998218
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3614940432
Short name T248
Test name
Test status
Simulation time 109060085 ps
CPU time 6.89 seconds
Started Mar 19 02:54:16 PM PDT 24
Finished Mar 19 02:54:23 PM PDT 24
Peak memory 215140 kb
Host smart-ed823590-6297-4499-bd72-1ae938072910
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614940432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3614940432
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2365248200
Short name T1044
Test name
Test status
Simulation time 58802707 ps
CPU time 2.04 seconds
Started Mar 19 02:54:20 PM PDT 24
Finished Mar 19 02:54:23 PM PDT 24
Peak memory 216140 kb
Host smart-badc5a11-26c4-4e3b-ae8b-9e9e434f1502
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365248200 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2365248200
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2323729510
Short name T123
Test name
Test status
Simulation time 1451772636 ps
CPU time 2.88 seconds
Started Mar 19 02:54:22 PM PDT 24
Finished Mar 19 02:54:26 PM PDT 24
Peak memory 215024 kb
Host smart-801cb917-c60b-4ec3-bece-b79838e17d56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323729510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2323729510
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2084741645
Short name T1002
Test name
Test status
Simulation time 13522792 ps
CPU time 0.74 seconds
Started Mar 19 02:54:20 PM PDT 24
Finished Mar 19 02:54:22 PM PDT 24
Peak memory 203340 kb
Host smart-70aafe74-c9dd-476a-99f9-ad2bacb38917
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084741645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2084741645
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.224020893
Short name T980
Test name
Test status
Simulation time 103439740 ps
CPU time 1.91 seconds
Started Mar 19 02:54:22 PM PDT 24
Finished Mar 19 02:54:25 PM PDT 24
Peak memory 215068 kb
Host smart-198372b9-fb4e-4186-8be9-655a4db955de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224020893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.224020893
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.4281854328
Short name T114
Test name
Test status
Simulation time 425277846 ps
CPU time 2.91 seconds
Started Mar 19 02:54:22 PM PDT 24
Finished Mar 19 02:54:26 PM PDT 24
Peak memory 215296 kb
Host smart-4b0eafbf-9ae8-41ec-be69-0cdcec783677
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281854328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
4281854328
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2668063314
Short name T245
Test name
Test status
Simulation time 1616454142 ps
CPU time 20.44 seconds
Started Mar 19 02:54:23 PM PDT 24
Finished Mar 19 02:54:45 PM PDT 24
Peak memory 215080 kb
Host smart-a501c969-449f-4e68-a7d6-69e6831b3ee8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668063314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2668063314
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2014896551
Short name T66
Test name
Test status
Simulation time 275601452 ps
CPU time 3.57 seconds
Started Mar 19 02:54:22 PM PDT 24
Finished Mar 19 02:54:26 PM PDT 24
Peak memory 217260 kb
Host smart-ffed7709-86b2-438a-8558-50d7adaa3eb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014896551 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2014896551
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2213106437
Short name T147
Test name
Test status
Simulation time 40283647 ps
CPU time 1.3 seconds
Started Mar 19 02:54:19 PM PDT 24
Finished Mar 19 02:54:20 PM PDT 24
Peak memory 215024 kb
Host smart-a028429c-048c-4e26-8b98-3d699cb587e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213106437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2213106437
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.551004691
Short name T1021
Test name
Test status
Simulation time 42511597 ps
CPU time 0.72 seconds
Started Mar 19 02:54:21 PM PDT 24
Finished Mar 19 02:54:23 PM PDT 24
Peak memory 203544 kb
Host smart-ce89f561-3ab8-4b8d-af61-5410e2d4fd6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551004691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.551004691
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1566646124
Short name T988
Test name
Test status
Simulation time 216189105 ps
CPU time 2.13 seconds
Started Mar 19 02:54:22 PM PDT 24
Finished Mar 19 02:54:25 PM PDT 24
Peak memory 215088 kb
Host smart-2162dfd9-5bc7-48f2-8401-aaeb3ba3581c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566646124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1566646124
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2213571858
Short name T1076
Test name
Test status
Simulation time 202282868 ps
CPU time 1.62 seconds
Started Mar 19 02:54:23 PM PDT 24
Finished Mar 19 02:54:26 PM PDT 24
Peak memory 215196 kb
Host smart-2bd21737-1125-414b-a672-efa452dfbe07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213571858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2213571858
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3923142224
Short name T996
Test name
Test status
Simulation time 45684682 ps
CPU time 3.13 seconds
Started Mar 19 02:54:25 PM PDT 24
Finished Mar 19 02:54:29 PM PDT 24
Peak memory 217596 kb
Host smart-3e475858-5c91-4586-8ef8-0058daa1c090
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923142224 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3923142224
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3068581192
Short name T128
Test name
Test status
Simulation time 175332824 ps
CPU time 2.61 seconds
Started Mar 19 02:54:20 PM PDT 24
Finished Mar 19 02:54:24 PM PDT 24
Peak memory 215084 kb
Host smart-6fe7db0e-089e-4974-8459-78a7c05c903f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068581192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3068581192
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1873370690
Short name T1042
Test name
Test status
Simulation time 21951224 ps
CPU time 0.76 seconds
Started Mar 19 02:54:21 PM PDT 24
Finished Mar 19 02:54:24 PM PDT 24
Peak memory 203460 kb
Host smart-0d379089-f5fb-4af0-96c9-11c24f995144
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873370690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1873370690
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3180528110
Short name T153
Test name
Test status
Simulation time 243566791 ps
CPU time 2.92 seconds
Started Mar 19 02:54:21 PM PDT 24
Finished Mar 19 02:54:25 PM PDT 24
Peak memory 214980 kb
Host smart-65737da1-122d-4150-b7ef-f699dfa8c655
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180528110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3180528110
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.929766569
Short name T102
Test name
Test status
Simulation time 29402439 ps
CPU time 2.16 seconds
Started Mar 19 02:54:22 PM PDT 24
Finished Mar 19 02:54:25 PM PDT 24
Peak memory 215216 kb
Host smart-bd48c19e-8387-4a90-a239-1b26fc50f838
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929766569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.929766569
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1511955625
Short name T1019
Test name
Test status
Simulation time 6598209802 ps
CPU time 17.94 seconds
Started Mar 19 02:54:22 PM PDT 24
Finished Mar 19 02:54:41 PM PDT 24
Peak memory 215264 kb
Host smart-a7a4d4cb-1053-404d-9b40-28d38cc4c709
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511955625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1511955625
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.985019784
Short name T1043
Test name
Test status
Simulation time 2164047886 ps
CPU time 24.88 seconds
Started Mar 19 02:53:46 PM PDT 24
Finished Mar 19 02:54:12 PM PDT 24
Peak memory 215144 kb
Host smart-c1ce28c4-3651-4c58-91ec-c25574c81a43
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985019784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.985019784
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3147175826
Short name T1045
Test name
Test status
Simulation time 532389825 ps
CPU time 36.75 seconds
Started Mar 19 02:53:47 PM PDT 24
Finished Mar 19 02:54:24 PM PDT 24
Peak memory 206904 kb
Host smart-7231e93c-52f9-4e61-b206-2598451bcee6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147175826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3147175826
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1631729221
Short name T91
Test name
Test status
Simulation time 26159228 ps
CPU time 1.42 seconds
Started Mar 19 02:53:47 PM PDT 24
Finished Mar 19 02:53:49 PM PDT 24
Peak memory 206888 kb
Host smart-b295643b-60b9-4ba2-b8bb-6d0db68a531a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631729221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1631729221
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3397579056
Short name T101
Test name
Test status
Simulation time 680128415 ps
CPU time 3.21 seconds
Started Mar 19 02:53:48 PM PDT 24
Finished Mar 19 02:53:51 PM PDT 24
Peak memory 216244 kb
Host smart-de7fea2a-1d83-445b-8c24-a5436131be9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397579056 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3397579056
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.582040978
Short name T1071
Test name
Test status
Simulation time 21463371 ps
CPU time 1.27 seconds
Started Mar 19 02:53:48 PM PDT 24
Finished Mar 19 02:53:50 PM PDT 24
Peak memory 206860 kb
Host smart-65338425-89cd-468e-b19e-21fe59ccb5d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582040978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.582040978
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.960400750
Short name T984
Test name
Test status
Simulation time 12226367 ps
CPU time 0.73 seconds
Started Mar 19 02:53:48 PM PDT 24
Finished Mar 19 02:53:49 PM PDT 24
Peak memory 203432 kb
Host smart-e52fae0a-232c-4c45-bf98-9dfed5545085
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960400750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.960400750
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3534057297
Short name T132
Test name
Test status
Simulation time 52178488 ps
CPU time 1.73 seconds
Started Mar 19 02:53:48 PM PDT 24
Finished Mar 19 02:53:50 PM PDT 24
Peak memory 215124 kb
Host smart-1c4b0cf4-8ff5-4f51-a841-617007251d78
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534057297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3534057297
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3723717571
Short name T1001
Test name
Test status
Simulation time 13930226 ps
CPU time 0.68 seconds
Started Mar 19 02:53:47 PM PDT 24
Finished Mar 19 02:53:48 PM PDT 24
Peak memory 203344 kb
Host smart-3760d1af-ba56-475f-9c38-3f1c08d80627
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723717571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3723717571
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.4232585083
Short name T1013
Test name
Test status
Simulation time 409916950 ps
CPU time 2.84 seconds
Started Mar 19 02:53:48 PM PDT 24
Finished Mar 19 02:53:51 PM PDT 24
Peak memory 215112 kb
Host smart-db954a40-1c18-4b28-8405-114b4a87eef2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232585083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.4232585083
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1780662566
Short name T1024
Test name
Test status
Simulation time 69477014 ps
CPU time 1.83 seconds
Started Mar 19 02:53:48 PM PDT 24
Finished Mar 19 02:53:50 PM PDT 24
Peak memory 215196 kb
Host smart-86e5394c-7723-461d-8df2-dab1ec07bcb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780662566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
780662566
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1332826081
Short name T1086
Test name
Test status
Simulation time 627953687 ps
CPU time 8.43 seconds
Started Mar 19 02:53:48 PM PDT 24
Finished Mar 19 02:53:57 PM PDT 24
Peak memory 215584 kb
Host smart-4d3fb439-516a-4bbd-960f-f8b3389b7757
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332826081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1332826081
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.970517610
Short name T1080
Test name
Test status
Simulation time 36078553 ps
CPU time 0.73 seconds
Started Mar 19 02:54:18 PM PDT 24
Finished Mar 19 02:54:20 PM PDT 24
Peak memory 203584 kb
Host smart-addb0571-cbb9-4ceb-9f82-311761b2d517
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970517610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.970517610
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.983379795
Short name T1087
Test name
Test status
Simulation time 34320667 ps
CPU time 0.77 seconds
Started Mar 19 02:54:20 PM PDT 24
Finished Mar 19 02:54:22 PM PDT 24
Peak memory 203468 kb
Host smart-083b331d-eab6-49f5-966f-24078582cdb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983379795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.983379795
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2691460869
Short name T1005
Test name
Test status
Simulation time 28966664 ps
CPU time 0.68 seconds
Started Mar 19 02:54:20 PM PDT 24
Finished Mar 19 02:54:21 PM PDT 24
Peak memory 203480 kb
Host smart-a7e68ee6-be0d-4d1c-86fc-2e1defe3f96e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691460869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2691460869
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1163766121
Short name T979
Test name
Test status
Simulation time 20677199 ps
CPU time 0.69 seconds
Started Mar 19 02:54:19 PM PDT 24
Finished Mar 19 02:54:21 PM PDT 24
Peak memory 203508 kb
Host smart-3be64f48-804e-4011-8df7-74c81fbca3e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163766121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1163766121
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2812668412
Short name T1049
Test name
Test status
Simulation time 14413159 ps
CPU time 0.72 seconds
Started Mar 19 02:54:24 PM PDT 24
Finished Mar 19 02:54:25 PM PDT 24
Peak memory 203512 kb
Host smart-666502d8-18b9-44d0-a5ca-fca3e1c7fe68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812668412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2812668412
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2239099970
Short name T989
Test name
Test status
Simulation time 25988156 ps
CPU time 0.73 seconds
Started Mar 19 02:54:23 PM PDT 24
Finished Mar 19 02:54:24 PM PDT 24
Peak memory 203520 kb
Host smart-03581944-c880-43e7-89bd-13193b0fc097
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239099970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2239099970
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2307427151
Short name T1064
Test name
Test status
Simulation time 25837347 ps
CPU time 0.69 seconds
Started Mar 19 02:54:19 PM PDT 24
Finished Mar 19 02:54:21 PM PDT 24
Peak memory 203468 kb
Host smart-877f3c1e-053b-4f95-b7c1-9f5673357a37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307427151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2307427151
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3666348360
Short name T981
Test name
Test status
Simulation time 39598622 ps
CPU time 0.75 seconds
Started Mar 19 02:54:22 PM PDT 24
Finished Mar 19 02:54:24 PM PDT 24
Peak memory 203568 kb
Host smart-58807c02-973b-498d-af65-391e01103536
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666348360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3666348360
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1766627082
Short name T978
Test name
Test status
Simulation time 14888021 ps
CPU time 0.88 seconds
Started Mar 19 02:54:21 PM PDT 24
Finished Mar 19 02:54:23 PM PDT 24
Peak memory 203476 kb
Host smart-00b774fc-b575-410c-bd81-715f74d7a7f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766627082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1766627082
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1402506881
Short name T1088
Test name
Test status
Simulation time 56509327 ps
CPU time 0.81 seconds
Started Mar 19 02:54:21 PM PDT 24
Finished Mar 19 02:54:23 PM PDT 24
Peak memory 203520 kb
Host smart-8790eec0-821a-4dc7-b5b2-3c085497cd6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402506881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1402506881
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3153733520
Short name T133
Test name
Test status
Simulation time 1178410792 ps
CPU time 23.33 seconds
Started Mar 19 02:53:48 PM PDT 24
Finished Mar 19 02:54:11 PM PDT 24
Peak memory 214928 kb
Host smart-dfb59465-6ae4-41b0-a822-167e8047dbd3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153733520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3153733520
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3461709070
Short name T1055
Test name
Test status
Simulation time 1645844277 ps
CPU time 12.66 seconds
Started Mar 19 02:53:48 PM PDT 24
Finished Mar 19 02:54:02 PM PDT 24
Peak memory 206984 kb
Host smart-cf723189-961a-44d7-8191-71b9c236ea9b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461709070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3461709070
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2847594
Short name T1030
Test name
Test status
Simulation time 22220836 ps
CPU time 1 seconds
Started Mar 19 02:53:48 PM PDT 24
Finished Mar 19 02:53:49 PM PDT 24
Peak memory 206696 kb
Host smart-1649a460-b1bd-4907-902d-81426f3a05f0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_h
w_reset.2847594
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1001517341
Short name T150
Test name
Test status
Simulation time 160670381 ps
CPU time 3.94 seconds
Started Mar 19 02:53:55 PM PDT 24
Finished Mar 19 02:54:00 PM PDT 24
Peak memory 217416 kb
Host smart-64871540-7651-4ed9-8eb9-ad8fe4267f0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001517341 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1001517341
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2709064970
Short name T1008
Test name
Test status
Simulation time 56738318 ps
CPU time 1.52 seconds
Started Mar 19 02:53:46 PM PDT 24
Finished Mar 19 02:53:48 PM PDT 24
Peak memory 206812 kb
Host smart-98e32dd2-7316-4e2a-b989-ed15f1a6cb11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709064970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
709064970
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.423733912
Short name T1003
Test name
Test status
Simulation time 16400387 ps
CPU time 0.77 seconds
Started Mar 19 02:53:46 PM PDT 24
Finished Mar 19 02:53:48 PM PDT 24
Peak memory 203472 kb
Host smart-2f4632ef-734d-4e07-9ca5-3139ee72e284
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423733912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.423733912
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3647721108
Short name T127
Test name
Test status
Simulation time 20123177 ps
CPU time 1.28 seconds
Started Mar 19 02:53:46 PM PDT 24
Finished Mar 19 02:53:48 PM PDT 24
Peak memory 215096 kb
Host smart-713905c8-037e-457c-b0f4-1e2499904dd8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647721108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3647721108
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.4248790311
Short name T1073
Test name
Test status
Simulation time 18448588 ps
CPU time 0.67 seconds
Started Mar 19 02:53:48 PM PDT 24
Finished Mar 19 02:53:49 PM PDT 24
Peak memory 203376 kb
Host smart-8fc841f1-aac6-4f25-a838-00c010917540
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248790311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.4248790311
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.4135351350
Short name T1066
Test name
Test status
Simulation time 274772389 ps
CPU time 1.91 seconds
Started Mar 19 02:53:55 PM PDT 24
Finished Mar 19 02:53:58 PM PDT 24
Peak memory 215080 kb
Host smart-9e53d5ee-fdc9-4dd5-a49f-d9bca24c2ac0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135351350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.4135351350
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.485929243
Short name T1036
Test name
Test status
Simulation time 452152767 ps
CPU time 4.4 seconds
Started Mar 19 02:53:47 PM PDT 24
Finished Mar 19 02:53:52 PM PDT 24
Peak memory 215284 kb
Host smart-63e21d6a-d595-4df6-adff-6dd7a7510933
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485929243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.485929243
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.4186515081
Short name T247
Test name
Test status
Simulation time 1003615232 ps
CPU time 19.75 seconds
Started Mar 19 02:53:49 PM PDT 24
Finished Mar 19 02:54:09 PM PDT 24
Peak memory 215512 kb
Host smart-d6c3c52f-3360-4a3f-8d19-275c0e51f98b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186515081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.4186515081
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.34126018
Short name T972
Test name
Test status
Simulation time 14230371 ps
CPU time 0.8 seconds
Started Mar 19 02:54:22 PM PDT 24
Finished Mar 19 02:54:23 PM PDT 24
Peak memory 203540 kb
Host smart-b83fa8bc-33db-4e2f-9ffd-a0f8c040b184
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34126018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.34126018
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4281840869
Short name T1039
Test name
Test status
Simulation time 13560089 ps
CPU time 0.79 seconds
Started Mar 19 02:54:22 PM PDT 24
Finished Mar 19 02:54:24 PM PDT 24
Peak memory 203520 kb
Host smart-e3e08c16-9d2e-4d68-b995-5a3c130e8154
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281840869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
4281840869
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2743780359
Short name T999
Test name
Test status
Simulation time 51489520 ps
CPU time 0.77 seconds
Started Mar 19 02:54:20 PM PDT 24
Finished Mar 19 02:54:22 PM PDT 24
Peak memory 203472 kb
Host smart-fc204b52-a134-4536-aa41-586269580b86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743780359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2743780359
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.4146051278
Short name T992
Test name
Test status
Simulation time 31366579 ps
CPU time 0.73 seconds
Started Mar 19 02:54:22 PM PDT 24
Finished Mar 19 02:54:23 PM PDT 24
Peak memory 203460 kb
Host smart-266ea671-ae2f-43c1-b10e-1a7c8de89300
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146051278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
4146051278
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1639748433
Short name T1046
Test name
Test status
Simulation time 14824627 ps
CPU time 0.78 seconds
Started Mar 19 02:54:21 PM PDT 24
Finished Mar 19 02:54:23 PM PDT 24
Peak memory 203548 kb
Host smart-17c87285-36e5-49c8-b84f-8d7a079565fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639748433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1639748433
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1278529784
Short name T1037
Test name
Test status
Simulation time 12221195 ps
CPU time 0.75 seconds
Started Mar 19 02:54:20 PM PDT 24
Finished Mar 19 02:54:23 PM PDT 24
Peak memory 203492 kb
Host smart-1391cc8a-58ae-421c-aa51-69cecd4956bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278529784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1278529784
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1027971344
Short name T985
Test name
Test status
Simulation time 41674828 ps
CPU time 0.79 seconds
Started Mar 19 02:54:21 PM PDT 24
Finished Mar 19 02:54:23 PM PDT 24
Peak memory 203468 kb
Host smart-1b237773-293c-4bcb-8cc2-7dd1a233c8e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027971344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1027971344
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2264952023
Short name T990
Test name
Test status
Simulation time 32025658 ps
CPU time 0.71 seconds
Started Mar 19 02:54:19 PM PDT 24
Finished Mar 19 02:54:21 PM PDT 24
Peak memory 203464 kb
Host smart-a2cc4800-3126-4d75-ae29-f6226e6c0f53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264952023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2264952023
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3443454912
Short name T1041
Test name
Test status
Simulation time 60248607 ps
CPU time 0.81 seconds
Started Mar 19 02:54:22 PM PDT 24
Finished Mar 19 02:54:24 PM PDT 24
Peak memory 203456 kb
Host smart-71e5162b-ac7d-4d26-8820-68a5ebece581
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443454912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3443454912
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2017572157
Short name T976
Test name
Test status
Simulation time 14025053 ps
CPU time 0.74 seconds
Started Mar 19 02:54:26 PM PDT 24
Finished Mar 19 02:54:28 PM PDT 24
Peak memory 203516 kb
Host smart-b8f7647b-88dd-430d-a72e-1dffcb091af0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017572157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2017572157
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.222060981
Short name T1051
Test name
Test status
Simulation time 640104057 ps
CPU time 17.03 seconds
Started Mar 19 02:53:59 PM PDT 24
Finished Mar 19 02:54:16 PM PDT 24
Peak memory 215076 kb
Host smart-05921d5b-69a2-427f-b8b8-3357a319a014
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222060981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.222060981
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.677020045
Short name T1063
Test name
Test status
Simulation time 1906594077 ps
CPU time 36.77 seconds
Started Mar 19 02:53:54 PM PDT 24
Finished Mar 19 02:54:31 PM PDT 24
Peak memory 206836 kb
Host smart-bd630fd6-f8cf-4243-8ab5-fc44bff0686a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677020045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.677020045
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.193988974
Short name T92
Test name
Test status
Simulation time 220954752 ps
CPU time 1.56 seconds
Started Mar 19 02:53:56 PM PDT 24
Finished Mar 19 02:53:58 PM PDT 24
Peak memory 206788 kb
Host smart-128635de-a8a6-43a4-94ae-69296d673b83
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193988974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.193988974
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.650517140
Short name T118
Test name
Test status
Simulation time 75216543 ps
CPU time 1.78 seconds
Started Mar 19 02:53:57 PM PDT 24
Finished Mar 19 02:53:59 PM PDT 24
Peak memory 216212 kb
Host smart-8d26ae82-0c05-42b4-b56c-adc96c959bb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650517140 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.650517140
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.734149437
Short name T1070
Test name
Test status
Simulation time 27606384 ps
CPU time 2.07 seconds
Started Mar 19 02:53:54 PM PDT 24
Finished Mar 19 02:53:57 PM PDT 24
Peak memory 215020 kb
Host smart-8ff24e4e-8acf-45bd-ada6-f377b1b6707d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734149437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.734149437
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1556494593
Short name T1007
Test name
Test status
Simulation time 11582700 ps
CPU time 0.75 seconds
Started Mar 19 02:53:59 PM PDT 24
Finished Mar 19 02:54:00 PM PDT 24
Peak memory 203464 kb
Host smart-2b506d63-50bd-44ea-8a51-a58f5bbd1cae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556494593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
556494593
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.961982151
Short name T1050
Test name
Test status
Simulation time 340856099 ps
CPU time 1.39 seconds
Started Mar 19 02:53:56 PM PDT 24
Finished Mar 19 02:53:58 PM PDT 24
Peak memory 215112 kb
Host smart-ee6ff645-0442-4866-a731-a8159ae2d4ec
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961982151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.961982151
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2884573647
Short name T974
Test name
Test status
Simulation time 16279205 ps
CPU time 0.64 seconds
Started Mar 19 02:53:55 PM PDT 24
Finished Mar 19 02:53:56 PM PDT 24
Peak memory 203344 kb
Host smart-667a5143-0b73-41c0-950b-93e9203c8bad
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884573647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2884573647
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2474853498
Short name T1079
Test name
Test status
Simulation time 489242829 ps
CPU time 3.07 seconds
Started Mar 19 02:53:55 PM PDT 24
Finished Mar 19 02:53:59 PM PDT 24
Peak memory 215512 kb
Host smart-758a3d9c-bbb5-4c9b-b2da-bbdb41a19749
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474853498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2474853498
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2773067013
Short name T1059
Test name
Test status
Simulation time 126905748 ps
CPU time 2.34 seconds
Started Mar 19 02:53:55 PM PDT 24
Finished Mar 19 02:53:58 PM PDT 24
Peak memory 215216 kb
Host smart-bbfbe6a6-aa2f-422c-9e0e-df2c71e3777e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773067013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
773067013
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2660492074
Short name T67
Test name
Test status
Simulation time 754565180 ps
CPU time 13.27 seconds
Started Mar 19 02:53:55 PM PDT 24
Finished Mar 19 02:54:09 PM PDT 24
Peak memory 215660 kb
Host smart-f1372477-78c9-4914-a523-a2f751a09f9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660492074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2660492074
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1494300016
Short name T1078
Test name
Test status
Simulation time 32882041 ps
CPU time 0.73 seconds
Started Mar 19 02:54:21 PM PDT 24
Finished Mar 19 02:54:23 PM PDT 24
Peak memory 203560 kb
Host smart-cdcff3f1-aea1-4aa5-8ed2-a85222672106
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494300016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1494300016
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1135601479
Short name T1074
Test name
Test status
Simulation time 14066037 ps
CPU time 0.71 seconds
Started Mar 19 02:54:27 PM PDT 24
Finished Mar 19 02:54:29 PM PDT 24
Peak memory 203488 kb
Host smart-7c4cff75-ed61-4fef-9e60-ce1b8ecf4f72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135601479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1135601479
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2422302891
Short name T1018
Test name
Test status
Simulation time 14912625 ps
CPU time 0.77 seconds
Started Mar 19 02:54:26 PM PDT 24
Finished Mar 19 02:54:28 PM PDT 24
Peak memory 203464 kb
Host smart-a9b849db-3272-485f-b183-32134d88a067
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422302891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2422302891
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.255715108
Short name T1017
Test name
Test status
Simulation time 107429805 ps
CPU time 0.7 seconds
Started Mar 19 02:54:20 PM PDT 24
Finished Mar 19 02:54:22 PM PDT 24
Peak memory 203404 kb
Host smart-ada82171-4b67-4edc-8442-a8c54ea892b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255715108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.255715108
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2188869571
Short name T1057
Test name
Test status
Simulation time 40488650 ps
CPU time 0.72 seconds
Started Mar 19 02:54:25 PM PDT 24
Finished Mar 19 02:54:28 PM PDT 24
Peak memory 203448 kb
Host smart-96532383-321b-4f77-b915-a0f6205a165d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188869571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2188869571
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1714229224
Short name T971
Test name
Test status
Simulation time 22281818 ps
CPU time 0.75 seconds
Started Mar 19 02:54:22 PM PDT 24
Finished Mar 19 02:54:24 PM PDT 24
Peak memory 203476 kb
Host smart-39594ee6-22e5-4fb7-a965-0bb8f3a83c3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714229224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1714229224
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1602640506
Short name T1068
Test name
Test status
Simulation time 30421498 ps
CPU time 0.79 seconds
Started Mar 19 02:54:25 PM PDT 24
Finished Mar 19 02:54:27 PM PDT 24
Peak memory 203464 kb
Host smart-1bae0df7-9ba6-4271-b3b7-b01d29383023
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602640506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1602640506
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.379962246
Short name T977
Test name
Test status
Simulation time 13382354 ps
CPU time 0.75 seconds
Started Mar 19 02:54:25 PM PDT 24
Finished Mar 19 02:54:27 PM PDT 24
Peak memory 203484 kb
Host smart-a4fc1314-ca76-4350-9381-521eaaaa8f5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379962246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.379962246
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.4045325608
Short name T1010
Test name
Test status
Simulation time 20076637 ps
CPU time 0.7 seconds
Started Mar 19 02:54:26 PM PDT 24
Finished Mar 19 02:54:29 PM PDT 24
Peak memory 203448 kb
Host smart-4c3a37f9-43dc-4d10-96ee-24753b5331c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045325608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
4045325608
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2582553629
Short name T1012
Test name
Test status
Simulation time 29952509 ps
CPU time 0.79 seconds
Started Mar 19 02:54:27 PM PDT 24
Finished Mar 19 02:54:29 PM PDT 24
Peak memory 203484 kb
Host smart-3763be59-6e7b-4f3a-aa72-489780ba32f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582553629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2582553629
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.484484666
Short name T1084
Test name
Test status
Simulation time 238706101 ps
CPU time 3.87 seconds
Started Mar 19 02:53:53 PM PDT 24
Finished Mar 19 02:53:57 PM PDT 24
Peak memory 217788 kb
Host smart-cc0cc30f-5be2-4ab5-98fa-4888cf97901c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484484666 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.484484666
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1188411505
Short name T130
Test name
Test status
Simulation time 96967452 ps
CPU time 2.78 seconds
Started Mar 19 02:53:56 PM PDT 24
Finished Mar 19 02:53:59 PM PDT 24
Peak memory 215108 kb
Host smart-efaedb77-b9f9-4ef4-a30a-118d48909051
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188411505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
188411505
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2850066838
Short name T1006
Test name
Test status
Simulation time 20129087 ps
CPU time 0.75 seconds
Started Mar 19 02:53:55 PM PDT 24
Finished Mar 19 02:53:55 PM PDT 24
Peak memory 203468 kb
Host smart-eb643a5d-3f11-4f2b-81da-1987e73b9978
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850066838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
850066838
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1704490451
Short name T1083
Test name
Test status
Simulation time 55344661 ps
CPU time 1.75 seconds
Started Mar 19 02:53:55 PM PDT 24
Finished Mar 19 02:53:58 PM PDT 24
Peak memory 206904 kb
Host smart-69b67073-149c-4135-9890-4630017f0420
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704490451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1704490451
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1471840201
Short name T1056
Test name
Test status
Simulation time 173001199 ps
CPU time 3.08 seconds
Started Mar 19 02:53:57 PM PDT 24
Finished Mar 19 02:54:00 PM PDT 24
Peak memory 215416 kb
Host smart-e93af5b7-3411-438c-806d-cedf4cc1b0ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471840201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
471840201
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2845635045
Short name T1090
Test name
Test status
Simulation time 297861751 ps
CPU time 8.9 seconds
Started Mar 19 02:53:56 PM PDT 24
Finished Mar 19 02:54:06 PM PDT 24
Peak memory 215096 kb
Host smart-3458bee2-44aa-4dc1-95c0-02f23e7d9fe4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845635045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2845635045
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.233164272
Short name T1060
Test name
Test status
Simulation time 318003004 ps
CPU time 3.65 seconds
Started Mar 19 02:54:02 PM PDT 24
Finished Mar 19 02:54:06 PM PDT 24
Peak memory 216804 kb
Host smart-87fd5875-d495-4947-81cd-5bcded685af5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233164272 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.233164272
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1016836238
Short name T1020
Test name
Test status
Simulation time 82835039 ps
CPU time 2.16 seconds
Started Mar 19 02:54:03 PM PDT 24
Finished Mar 19 02:54:06 PM PDT 24
Peak memory 206880 kb
Host smart-30d599a9-2a2c-4e4d-816e-0d72088da555
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016836238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
016836238
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.816963214
Short name T1028
Test name
Test status
Simulation time 43030647 ps
CPU time 0.79 seconds
Started Mar 19 02:54:03 PM PDT 24
Finished Mar 19 02:54:04 PM PDT 24
Peak memory 203528 kb
Host smart-9a1f1bd2-ff8c-443b-b091-23033aa58a83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816963214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.816963214
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1966926887
Short name T1092
Test name
Test status
Simulation time 47189140 ps
CPU time 1.66 seconds
Started Mar 19 02:54:08 PM PDT 24
Finished Mar 19 02:54:09 PM PDT 24
Peak memory 215136 kb
Host smart-17b71e8f-3c24-4986-af23-e5b14126803a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966926887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1966926887
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.508396089
Short name T1052
Test name
Test status
Simulation time 127747108 ps
CPU time 3.91 seconds
Started Mar 19 02:54:02 PM PDT 24
Finished Mar 19 02:54:06 PM PDT 24
Peak memory 216704 kb
Host smart-983099e1-1fb8-49f0-b75c-37d1bfede883
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508396089 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.508396089
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2450766275
Short name T1015
Test name
Test status
Simulation time 69240475 ps
CPU time 1.34 seconds
Started Mar 19 02:54:02 PM PDT 24
Finished Mar 19 02:54:04 PM PDT 24
Peak memory 214976 kb
Host smart-d6eeb5c7-1f35-43c1-a828-cf926203a9fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450766275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
450766275
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2544954839
Short name T1032
Test name
Test status
Simulation time 24051698 ps
CPU time 0.73 seconds
Started Mar 19 02:54:03 PM PDT 24
Finished Mar 19 02:54:04 PM PDT 24
Peak memory 203456 kb
Host smart-cace7c0c-3bac-49e9-b5bb-09854870e166
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544954839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
544954839
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.4119216672
Short name T1023
Test name
Test status
Simulation time 688040511 ps
CPU time 5.02 seconds
Started Mar 19 02:54:08 PM PDT 24
Finished Mar 19 02:54:13 PM PDT 24
Peak memory 215108 kb
Host smart-d168243b-bf81-4fe2-80be-78975507a44a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119216672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.4119216672
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.476899595
Short name T116
Test name
Test status
Simulation time 23101538 ps
CPU time 1.78 seconds
Started Mar 19 02:54:02 PM PDT 24
Finished Mar 19 02:54:04 PM PDT 24
Peak memory 215392 kb
Host smart-e50be13c-0e74-4b49-9dd8-eb461d885c1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476899595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.476899595
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1176532464
Short name T149
Test name
Test status
Simulation time 666801310 ps
CPU time 16.09 seconds
Started Mar 19 02:54:05 PM PDT 24
Finished Mar 19 02:54:21 PM PDT 24
Peak memory 215120 kb
Host smart-7dc0646f-1880-4562-854d-68035b2e9bed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176532464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1176532464
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.4010593209
Short name T151
Test name
Test status
Simulation time 149720031 ps
CPU time 3.78 seconds
Started Mar 19 02:54:10 PM PDT 24
Finished Mar 19 02:54:14 PM PDT 24
Peak memory 216832 kb
Host smart-18ad40e7-4606-474f-a76e-e6aee2f88b3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010593209 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.4010593209
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1055940606
Short name T124
Test name
Test status
Simulation time 67958329 ps
CPU time 1.36 seconds
Started Mar 19 02:54:01 PM PDT 24
Finished Mar 19 02:54:03 PM PDT 24
Peak memory 206804 kb
Host smart-208521fa-45ab-49ee-8c87-949d778da080
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055940606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
055940606
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.313954559
Short name T997
Test name
Test status
Simulation time 15355225 ps
CPU time 0.76 seconds
Started Mar 19 02:54:03 PM PDT 24
Finished Mar 19 02:54:04 PM PDT 24
Peak memory 203540 kb
Host smart-ab485e28-7285-4d0b-8c65-ef029412a6d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313954559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.313954559
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2998913611
Short name T1082
Test name
Test status
Simulation time 234488729 ps
CPU time 1.99 seconds
Started Mar 19 02:54:05 PM PDT 24
Finished Mar 19 02:54:08 PM PDT 24
Peak memory 206856 kb
Host smart-223508d7-12aa-41fb-b2df-5b31643b6bff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998913611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2998913611
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1874578335
Short name T1026
Test name
Test status
Simulation time 98202289 ps
CPU time 3.07 seconds
Started Mar 19 02:54:01 PM PDT 24
Finished Mar 19 02:54:04 PM PDT 24
Peak memory 215260 kb
Host smart-162ceada-9d2e-4c37-b6f9-8542286db8c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874578335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
874578335
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2986631939
Short name T246
Test name
Test status
Simulation time 2425821714 ps
CPU time 7.37 seconds
Started Mar 19 02:54:04 PM PDT 24
Finished Mar 19 02:54:11 PM PDT 24
Peak memory 215184 kb
Host smart-1adca149-b809-4042-b7cf-b9e9ea7058e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986631939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2986631939
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1827228126
Short name T1014
Test name
Test status
Simulation time 99857461 ps
CPU time 2.6 seconds
Started Mar 19 02:54:03 PM PDT 24
Finished Mar 19 02:54:06 PM PDT 24
Peak memory 216164 kb
Host smart-dd2e6163-c3ef-4d27-83c3-d8bec618b6df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827228126 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1827228126
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1137025912
Short name T1081
Test name
Test status
Simulation time 138672715 ps
CPU time 2.64 seconds
Started Mar 19 02:54:02 PM PDT 24
Finished Mar 19 02:54:05 PM PDT 24
Peak memory 206820 kb
Host smart-50ceae04-39f5-445a-b8ed-a2e4347f9c3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137025912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
137025912
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3890146124
Short name T1053
Test name
Test status
Simulation time 37604904 ps
CPU time 0.76 seconds
Started Mar 19 02:54:03 PM PDT 24
Finished Mar 19 02:54:04 PM PDT 24
Peak memory 203332 kb
Host smart-66667f64-51d7-4d8b-a36d-63821c51c02a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890146124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
890146124
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4022938972
Short name T1040
Test name
Test status
Simulation time 277177251 ps
CPU time 2.03 seconds
Started Mar 19 02:54:02 PM PDT 24
Finished Mar 19 02:54:05 PM PDT 24
Peak memory 215116 kb
Host smart-be2dc66c-1024-49bc-8ea1-3bcaa8afc379
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022938972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.4022938972
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2937658019
Short name T1029
Test name
Test status
Simulation time 999344727 ps
CPU time 3.15 seconds
Started Mar 19 02:54:03 PM PDT 24
Finished Mar 19 02:54:07 PM PDT 24
Peak memory 215248 kb
Host smart-8f73d0e5-1927-41fa-94a9-2c598f7ad9a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937658019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
937658019
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2635616558
Short name T1016
Test name
Test status
Simulation time 1618076008 ps
CPU time 21.66 seconds
Started Mar 19 02:54:05 PM PDT 24
Finished Mar 19 02:54:27 PM PDT 24
Peak memory 215132 kb
Host smart-3c477828-dc2a-431c-af70-3217bfa3c198
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635616558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2635616558
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3032739207
Short name T779
Test name
Test status
Simulation time 83800726 ps
CPU time 0.74 seconds
Started Mar 19 01:12:41 PM PDT 24
Finished Mar 19 01:12:42 PM PDT 24
Peak memory 204324 kb
Host smart-1c1ce709-8699-48ad-b589-4edaecd717ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032739207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
032739207
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.495066462
Short name T210
Test name
Test status
Simulation time 1463607611 ps
CPU time 6.43 seconds
Started Mar 19 01:12:34 PM PDT 24
Finished Mar 19 01:12:41 PM PDT 24
Peak memory 237420 kb
Host smart-8493d932-4f74-4c56-8ef1-aa4148d1e6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495066462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.495066462
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.162706578
Short name T445
Test name
Test status
Simulation time 39709187 ps
CPU time 0.77 seconds
Started Mar 19 01:12:24 PM PDT 24
Finished Mar 19 01:12:25 PM PDT 24
Peak memory 206048 kb
Host smart-496d0b08-1173-4810-8fb5-89557fbd20bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162706578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.162706578
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1729296708
Short name T534
Test name
Test status
Simulation time 118132657546 ps
CPU time 162 seconds
Started Mar 19 01:12:42 PM PDT 24
Finished Mar 19 01:15:24 PM PDT 24
Peak memory 238896 kb
Host smart-4b125ae5-b2f6-457f-a79f-7b4b328c15ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729296708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1729296708
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2459430076
Short name T241
Test name
Test status
Simulation time 5005947803 ps
CPU time 41.82 seconds
Started Mar 19 01:12:43 PM PDT 24
Finished Mar 19 01:13:25 PM PDT 24
Peak memory 269704 kb
Host smart-52ab1fa8-e0d3-4fc2-a98f-87a5a0d36bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459430076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2459430076
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.331117304
Short name T449
Test name
Test status
Simulation time 36464339376 ps
CPU time 17.97 seconds
Started Mar 19 01:12:32 PM PDT 24
Finished Mar 19 01:12:50 PM PDT 24
Peak memory 232256 kb
Host smart-6fbf4aa8-47a0-4c31-8a5a-94dc3c20503c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331117304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.331117304
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1412017122
Short name T520
Test name
Test status
Simulation time 1176298100 ps
CPU time 5.8 seconds
Started Mar 19 01:12:33 PM PDT 24
Finished Mar 19 01:12:39 PM PDT 24
Peak memory 237644 kb
Host smart-a3e9c776-8bc6-403a-aa54-1571b40dba51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412017122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1412017122
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.484995190
Short name T145
Test name
Test status
Simulation time 11581272631 ps
CPU time 27.05 seconds
Started Mar 19 01:12:32 PM PDT 24
Finished Mar 19 01:12:59 PM PDT 24
Peak memory 217304 kb
Host smart-ed8d5b91-82d0-4647-8680-f934bc8fb2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484995190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.484995190
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1331470713
Short name T615
Test name
Test status
Simulation time 6919403326 ps
CPU time 5.46 seconds
Started Mar 19 01:12:37 PM PDT 24
Finished Mar 19 01:12:42 PM PDT 24
Peak memory 218432 kb
Host smart-4959b06f-8300-47d6-8a1a-847f491e7199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331470713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1331470713
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3225893029
Short name T935
Test name
Test status
Simulation time 14205078194 ps
CPU time 8.82 seconds
Started Mar 19 01:12:24 PM PDT 24
Finished Mar 19 01:12:33 PM PDT 24
Peak memory 218096 kb
Host smart-6417b127-6769-492d-8d55-dddab4fb748c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225893029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3225893029
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.751143125
Short name T902
Test name
Test status
Simulation time 33884719 ps
CPU time 0.74 seconds
Started Mar 19 01:12:23 PM PDT 24
Finished Mar 19 01:12:24 PM PDT 24
Peak memory 215792 kb
Host smart-21e225f5-b31e-4c23-aed4-e539e2e948ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751143125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.751143125
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2754676617
Short name T135
Test name
Test status
Simulation time 7123361455 ps
CPU time 5.47 seconds
Started Mar 19 01:12:41 PM PDT 24
Finished Mar 19 01:12:47 PM PDT 24
Peak memory 218756 kb
Host smart-430d09d8-a4db-4769-967d-b7a736da0923
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2754676617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2754676617
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3066209246
Short name T74
Test name
Test status
Simulation time 677322145 ps
CPU time 1.28 seconds
Started Mar 19 01:12:42 PM PDT 24
Finished Mar 19 01:12:44 PM PDT 24
Peak memory 234784 kb
Host smart-4c950854-a627-482b-8c6a-1560e3f436d6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066209246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3066209246
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3744804571
Short name T159
Test name
Test status
Simulation time 142014500245 ps
CPU time 231.79 seconds
Started Mar 19 01:12:47 PM PDT 24
Finished Mar 19 01:16:39 PM PDT 24
Peak memory 266232 kb
Host smart-8dac5c55-faa2-445b-b62b-ba6d30f51618
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744804571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3744804571
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2896432494
Short name T380
Test name
Test status
Simulation time 6856307476 ps
CPU time 44.41 seconds
Started Mar 19 01:12:24 PM PDT 24
Finished Mar 19 01:13:08 PM PDT 24
Peak memory 215796 kb
Host smart-1b35ac7e-33f1-478b-ad3d-7bd664f77e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896432494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2896432494
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3609877702
Short name T743
Test name
Test status
Simulation time 8466354642 ps
CPU time 24.25 seconds
Started Mar 19 01:12:23 PM PDT 24
Finished Mar 19 01:12:47 PM PDT 24
Peak memory 215656 kb
Host smart-9df59770-efaa-4931-ac0c-757cc552d69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609877702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3609877702
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.196481539
Short name T690
Test name
Test status
Simulation time 180391163 ps
CPU time 1.59 seconds
Started Mar 19 01:12:25 PM PDT 24
Finished Mar 19 01:12:27 PM PDT 24
Peak memory 215796 kb
Host smart-94ad374e-5630-46b0-ae75-388cefbcf1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196481539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.196481539
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.781396216
Short name T429
Test name
Test status
Simulation time 145347474 ps
CPU time 1.02 seconds
Started Mar 19 01:12:25 PM PDT 24
Finished Mar 19 01:12:26 PM PDT 24
Peak memory 206244 kb
Host smart-6a70fbf1-e677-41d3-9f0c-00b89e8e3e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781396216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.781396216
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1743485897
Short name T458
Test name
Test status
Simulation time 15822698449 ps
CPU time 10.64 seconds
Started Mar 19 01:12:37 PM PDT 24
Finished Mar 19 01:12:48 PM PDT 24
Peak memory 240508 kb
Host smart-8afacdba-bf4a-4951-9eda-bcad2427edb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743485897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1743485897
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.960309358
Short name T953
Test name
Test status
Simulation time 21060072 ps
CPU time 0.67 seconds
Started Mar 19 01:12:53 PM PDT 24
Finished Mar 19 01:12:53 PM PDT 24
Peak memory 204296 kb
Host smart-ba74b20e-d1d5-44f2-ad32-39ab4fbf21ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960309358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.960309358
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1887622664
Short name T946
Test name
Test status
Simulation time 136153808 ps
CPU time 2.61 seconds
Started Mar 19 01:12:52 PM PDT 24
Finished Mar 19 01:12:55 PM PDT 24
Peak memory 233096 kb
Host smart-268f8476-e391-490d-aaa6-22cce9008d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887622664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1887622664
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3607998345
Short name T584
Test name
Test status
Simulation time 13631253 ps
CPU time 0.77 seconds
Started Mar 19 01:12:42 PM PDT 24
Finished Mar 19 01:12:44 PM PDT 24
Peak memory 204960 kb
Host smart-a7f8946d-a7e0-4929-b770-a34a2a66a3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607998345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3607998345
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1534568760
Short name T548
Test name
Test status
Simulation time 3262970190 ps
CPU time 34.76 seconds
Started Mar 19 01:12:50 PM PDT 24
Finished Mar 19 01:13:25 PM PDT 24
Peak memory 248732 kb
Host smart-771f2914-8f48-454f-a57d-c893fe4b91ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534568760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1534568760
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.308689067
Short name T47
Test name
Test status
Simulation time 5488694913 ps
CPU time 65.03 seconds
Started Mar 19 01:12:53 PM PDT 24
Finished Mar 19 01:13:58 PM PDT 24
Peak memory 254208 kb
Host smart-d660384d-312a-4ee1-89cc-7f6c3c3574b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308689067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.308689067
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1803312987
Short name T868
Test name
Test status
Simulation time 1400683936 ps
CPU time 21.43 seconds
Started Mar 19 01:12:50 PM PDT 24
Finished Mar 19 01:13:12 PM PDT 24
Peak memory 220836 kb
Host smart-eeef6624-34da-49d1-bcd4-3daca5b840d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803312987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1803312987
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1087187513
Short name T682
Test name
Test status
Simulation time 1493131607 ps
CPU time 12.44 seconds
Started Mar 19 01:12:53 PM PDT 24
Finished Mar 19 01:13:06 PM PDT 24
Peak memory 232252 kb
Host smart-db46a5d2-144f-4bed-baa3-1aba51ea41fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087187513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1087187513
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1973427456
Short name T771
Test name
Test status
Simulation time 331080276 ps
CPU time 3.19 seconds
Started Mar 19 01:12:50 PM PDT 24
Finished Mar 19 01:12:54 PM PDT 24
Peak memory 224008 kb
Host smart-1a4d91a4-1c22-47a6-9d84-c1c4fae0cfde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973427456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1973427456
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.2625333110
Short name T639
Test name
Test status
Simulation time 31354595226 ps
CPU time 27.99 seconds
Started Mar 19 01:12:52 PM PDT 24
Finished Mar 19 01:13:20 PM PDT 24
Peak memory 236696 kb
Host smart-84db2059-dd6b-4b78-9ac2-3f1dd32e540d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625333110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2625333110
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2809454764
Short name T394
Test name
Test status
Simulation time 1158912924 ps
CPU time 8.62 seconds
Started Mar 19 01:12:51 PM PDT 24
Finished Mar 19 01:13:01 PM PDT 24
Peak memory 217944 kb
Host smart-19707847-6abc-4eb8-903e-164816582665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809454764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2809454764
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.4022139753
Short name T551
Test name
Test status
Simulation time 2305422314 ps
CPU time 16.06 seconds
Started Mar 19 01:12:44 PM PDT 24
Finished Mar 19 01:13:00 PM PDT 24
Peak memory 234332 kb
Host smart-b9993253-6506-42be-92ae-11ebe53e11d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022139753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.4022139753
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.186414963
Short name T918
Test name
Test status
Simulation time 17962194 ps
CPU time 0.81 seconds
Started Mar 19 01:12:42 PM PDT 24
Finished Mar 19 01:12:44 PM PDT 24
Peak memory 215720 kb
Host smart-d7e5a108-22f6-46f5-ae88-0ec1bb6f8468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186414963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.186414963
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1671924849
Short name T607
Test name
Test status
Simulation time 625773285 ps
CPU time 4.71 seconds
Started Mar 19 01:12:51 PM PDT 24
Finished Mar 19 01:12:57 PM PDT 24
Peak memory 219408 kb
Host smart-75f444ab-e72d-48ea-9869-d865bf9228e7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1671924849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1671924849
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1995480254
Short name T446
Test name
Test status
Simulation time 47738808708 ps
CPU time 319.17 seconds
Started Mar 19 01:12:51 PM PDT 24
Finished Mar 19 01:18:11 PM PDT 24
Peak memory 248996 kb
Host smart-49886bdd-cc94-4f51-b43c-20bdd2d7ead6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995480254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1995480254
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2600607295
Short name T500
Test name
Test status
Simulation time 745647841 ps
CPU time 3.87 seconds
Started Mar 19 01:12:42 PM PDT 24
Finished Mar 19 01:12:47 PM PDT 24
Peak memory 215768 kb
Host smart-ca8e98bc-7e22-4a4f-bee0-3d32ebce3add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600607295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2600607295
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3588414253
Short name T335
Test name
Test status
Simulation time 1218119353 ps
CPU time 4.12 seconds
Started Mar 19 01:12:44 PM PDT 24
Finished Mar 19 01:12:50 PM PDT 24
Peak memory 215852 kb
Host smart-3a376129-1847-485a-9cb8-0f57df6e4d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588414253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3588414253
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2068820316
Short name T285
Test name
Test status
Simulation time 12089240 ps
CPU time 0.71 seconds
Started Mar 19 01:12:43 PM PDT 24
Finished Mar 19 01:12:45 PM PDT 24
Peak memory 205268 kb
Host smart-c877bdcf-ac32-4f4a-a986-018058d21721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068820316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2068820316
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.3212566067
Short name T835
Test name
Test status
Simulation time 433578516 ps
CPU time 3.29 seconds
Started Mar 19 01:12:51 PM PDT 24
Finished Mar 19 01:12:54 PM PDT 24
Peak memory 235224 kb
Host smart-9d07300c-a6fb-4664-8966-f09e3a26f3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212566067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3212566067
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1433573491
Short name T401
Test name
Test status
Simulation time 48487856 ps
CPU time 0.72 seconds
Started Mar 19 01:14:59 PM PDT 24
Finished Mar 19 01:15:00 PM PDT 24
Peak memory 204896 kb
Host smart-9068c3ca-ddb4-4f83-9004-379d8400a527
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433573491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1433573491
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.86349194
Short name T367
Test name
Test status
Simulation time 477367744 ps
CPU time 2.51 seconds
Started Mar 19 01:14:48 PM PDT 24
Finished Mar 19 01:14:51 PM PDT 24
Peak memory 217272 kb
Host smart-4a2e0998-80da-4848-ba8e-72e7a3a4487f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86349194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.86349194
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2031622102
Short name T787
Test name
Test status
Simulation time 43739709 ps
CPU time 0.74 seconds
Started Mar 19 01:14:41 PM PDT 24
Finished Mar 19 01:14:42 PM PDT 24
Peak memory 206032 kb
Host smart-8eb174d9-d455-4490-86c0-cd66603461f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031622102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2031622102
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2077089475
Short name T530
Test name
Test status
Simulation time 16988969413 ps
CPU time 59.34 seconds
Started Mar 19 01:14:56 PM PDT 24
Finished Mar 19 01:15:56 PM PDT 24
Peak memory 248704 kb
Host smart-dc4287a1-1b18-475c-a0c2-0b7619659d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077089475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2077089475
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.266429325
Short name T864
Test name
Test status
Simulation time 72469583838 ps
CPU time 501.26 seconds
Started Mar 19 01:14:59 PM PDT 24
Finished Mar 19 01:23:21 PM PDT 24
Peak memory 256928 kb
Host smart-e7254efc-67ea-479d-92d2-e15fb2e191e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266429325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.266429325
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.231300540
Short name T398
Test name
Test status
Simulation time 47582328047 ps
CPU time 188.38 seconds
Started Mar 19 01:14:58 PM PDT 24
Finished Mar 19 01:18:06 PM PDT 24
Peak memory 255140 kb
Host smart-aa670ef5-1a50-4c4c-bb52-9a7642d01267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231300540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.231300540
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2133769563
Short name T320
Test name
Test status
Simulation time 1323498505 ps
CPU time 13.88 seconds
Started Mar 19 01:14:48 PM PDT 24
Finished Mar 19 01:15:02 PM PDT 24
Peak memory 222892 kb
Host smart-b6e657dc-8ce0-4ca1-a8ce-6a68f57f6553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133769563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2133769563
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3141014129
Short name T169
Test name
Test status
Simulation time 9191948116 ps
CPU time 3.73 seconds
Started Mar 19 01:14:47 PM PDT 24
Finished Mar 19 01:14:51 PM PDT 24
Peak memory 224036 kb
Host smart-cff3040b-707e-4935-8c15-7234155c7266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141014129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3141014129
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.326484497
Short name T213
Test name
Test status
Simulation time 6825982091 ps
CPU time 8.08 seconds
Started Mar 19 01:14:48 PM PDT 24
Finished Mar 19 01:14:56 PM PDT 24
Peak memory 237084 kb
Host smart-db42698a-fed8-4a67-aae7-e3aa37e06d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326484497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.326484497
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.380964660
Short name T231
Test name
Test status
Simulation time 2355057969 ps
CPU time 9.38 seconds
Started Mar 19 01:14:57 PM PDT 24
Finished Mar 19 01:15:06 PM PDT 24
Peak memory 236252 kb
Host smart-8173ff2d-ecaf-4119-9dd0-566123b0efad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380964660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.380964660
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3651350553
Short name T638
Test name
Test status
Simulation time 10901743203 ps
CPU time 9.91 seconds
Started Mar 19 01:14:57 PM PDT 24
Finished Mar 19 01:15:07 PM PDT 24
Peak memory 233204 kb
Host smart-1fe524dc-d10e-4ae6-a94f-73e16526441e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651350553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3651350553
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.883841705
Short name T381
Test name
Test status
Simulation time 899598454 ps
CPU time 5.08 seconds
Started Mar 19 01:14:56 PM PDT 24
Finished Mar 19 01:15:02 PM PDT 24
Peak memory 219736 kb
Host smart-167c2834-a7f7-48bb-8da6-46dc36abcee6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=883841705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.883841705
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.976091047
Short name T925
Test name
Test status
Simulation time 49343653002 ps
CPU time 115.32 seconds
Started Mar 19 01:14:58 PM PDT 24
Finished Mar 19 01:16:53 PM PDT 24
Peak memory 256940 kb
Host smart-546c7bd7-e354-4bae-96a4-79d20f957eff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976091047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.976091047
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.718856456
Short name T95
Test name
Test status
Simulation time 16329293907 ps
CPU time 34.43 seconds
Started Mar 19 01:14:57 PM PDT 24
Finished Mar 19 01:15:31 PM PDT 24
Peak memory 215848 kb
Host smart-d1e27693-a5d0-4dd5-9c8e-32937cf2e6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718856456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.718856456
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1011888040
Short name T287
Test name
Test status
Simulation time 7994688619 ps
CPU time 6.86 seconds
Started Mar 19 01:14:49 PM PDT 24
Finished Mar 19 01:14:55 PM PDT 24
Peak memory 215816 kb
Host smart-b4ffa9b8-dc90-4e56-93bd-b305603f827a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011888040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1011888040
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.125546678
Short name T244
Test name
Test status
Simulation time 61565386 ps
CPU time 1.64 seconds
Started Mar 19 01:14:48 PM PDT 24
Finished Mar 19 01:14:50 PM PDT 24
Peak memory 215756 kb
Host smart-b52911a5-0f4e-450b-b252-a5ebecf9b551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125546678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.125546678
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1157383188
Short name T40
Test name
Test status
Simulation time 103565932 ps
CPU time 1.04 seconds
Started Mar 19 01:14:47 PM PDT 24
Finished Mar 19 01:14:48 PM PDT 24
Peak memory 206216 kb
Host smart-ee48020b-9108-42c0-90da-77e84c197967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157383188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1157383188
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3608494712
Short name T544
Test name
Test status
Simulation time 931422640 ps
CPU time 6.08 seconds
Started Mar 19 01:14:47 PM PDT 24
Finished Mar 19 01:14:54 PM PDT 24
Peak memory 229332 kb
Host smart-7031008f-0d1d-4369-8586-382c88723dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608494712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3608494712
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.744733193
Short name T564
Test name
Test status
Simulation time 13825039 ps
CPU time 0.72 seconds
Started Mar 19 01:15:11 PM PDT 24
Finished Mar 19 01:15:13 PM PDT 24
Peak memory 204916 kb
Host smart-6d650db8-7b4a-42ec-ae07-835930fea132
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744733193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.744733193
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3644685151
Short name T788
Test name
Test status
Simulation time 1663638635 ps
CPU time 3.88 seconds
Started Mar 19 01:14:56 PM PDT 24
Finished Mar 19 01:15:00 PM PDT 24
Peak memory 233236 kb
Host smart-61676c9f-8484-44b8-9f29-ab2e8054c1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644685151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3644685151
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2007532413
Short name T282
Test name
Test status
Simulation time 14721259 ps
CPU time 0.77 seconds
Started Mar 19 01:14:55 PM PDT 24
Finished Mar 19 01:14:56 PM PDT 24
Peak memory 205984 kb
Host smart-e9803f24-c10b-4623-a4b8-3efe38401a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007532413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2007532413
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.587823843
Short name T185
Test name
Test status
Simulation time 6111841952 ps
CPU time 82.45 seconds
Started Mar 19 01:14:58 PM PDT 24
Finished Mar 19 01:16:21 PM PDT 24
Peak memory 255912 kb
Host smart-fbb8aff8-3132-4b09-a35d-f7c0df392b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587823843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.587823843
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2544054408
Short name T227
Test name
Test status
Simulation time 10645564438 ps
CPU time 103.17 seconds
Started Mar 19 01:14:56 PM PDT 24
Finished Mar 19 01:16:39 PM PDT 24
Peak memory 248820 kb
Host smart-044960c5-7254-4090-8fa3-bb90fbee7d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544054408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2544054408
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2309376232
Short name T738
Test name
Test status
Simulation time 12887377712 ps
CPU time 65.49 seconds
Started Mar 19 01:14:57 PM PDT 24
Finished Mar 19 01:16:03 PM PDT 24
Peak memory 248636 kb
Host smart-500eb5ec-9297-48c7-bd8e-d538afb53b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309376232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2309376232
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3184022365
Short name T348
Test name
Test status
Simulation time 87677895 ps
CPU time 3.07 seconds
Started Mar 19 01:14:59 PM PDT 24
Finished Mar 19 01:15:03 PM PDT 24
Peak memory 232192 kb
Host smart-980fec81-9478-4ce6-9cd4-4bcab7560ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184022365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3184022365
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.274083980
Short name T250
Test name
Test status
Simulation time 2441720990 ps
CPU time 11.88 seconds
Started Mar 19 01:14:56 PM PDT 24
Finished Mar 19 01:15:08 PM PDT 24
Peak memory 224096 kb
Host smart-b252c3c0-c4f4-4c9e-808f-b566d108d1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274083980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.274083980
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2758883573
Short name T171
Test name
Test status
Simulation time 449298395 ps
CPU time 3.77 seconds
Started Mar 19 01:14:57 PM PDT 24
Finished Mar 19 01:15:00 PM PDT 24
Peak memory 233312 kb
Host smart-6379f888-a184-4ca8-a892-7585d31836f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758883573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2758883573
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1719789875
Short name T699
Test name
Test status
Simulation time 2965686821 ps
CPU time 5.99 seconds
Started Mar 19 01:14:56 PM PDT 24
Finished Mar 19 01:15:02 PM PDT 24
Peak memory 224088 kb
Host smart-73b9920c-f252-4af8-9b69-97dc590f1de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719789875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1719789875
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.3563604381
Short name T314
Test name
Test status
Simulation time 16345587 ps
CPU time 0.75 seconds
Started Mar 19 01:14:59 PM PDT 24
Finished Mar 19 01:15:00 PM PDT 24
Peak memory 215724 kb
Host smart-67a7d0f5-4b4a-467e-a2a3-b86a118aeed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563604381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.3563604381
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1007384761
Short name T533
Test name
Test status
Simulation time 5581928983 ps
CPU time 6.47 seconds
Started Mar 19 01:14:57 PM PDT 24
Finished Mar 19 01:15:04 PM PDT 24
Peak memory 219824 kb
Host smart-77df817b-e083-4b49-a0a0-e0085523cd75
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1007384761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1007384761
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.214713920
Short name T271
Test name
Test status
Simulation time 67335902977 ps
CPU time 44.82 seconds
Started Mar 19 01:14:56 PM PDT 24
Finished Mar 19 01:15:40 PM PDT 24
Peak memory 215860 kb
Host smart-31f4f266-c905-4217-9c84-40d3ef9717fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214713920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.214713920
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3624814432
Short name T929
Test name
Test status
Simulation time 32406324700 ps
CPU time 21.01 seconds
Started Mar 19 01:14:57 PM PDT 24
Finished Mar 19 01:15:19 PM PDT 24
Peak memory 215800 kb
Host smart-45925d7e-772c-4caf-873b-8aa04334eb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624814432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3624814432
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.4235681054
Short name T759
Test name
Test status
Simulation time 41254893 ps
CPU time 1.02 seconds
Started Mar 19 01:14:58 PM PDT 24
Finished Mar 19 01:14:59 PM PDT 24
Peak memory 206772 kb
Host smart-601845cb-1e57-46d5-957e-8a59b049efab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235681054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.4235681054
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3639189516
Short name T927
Test name
Test status
Simulation time 46419060 ps
CPU time 0.74 seconds
Started Mar 19 01:14:57 PM PDT 24
Finished Mar 19 01:14:57 PM PDT 24
Peak memory 205252 kb
Host smart-250f3481-5738-4988-8259-a3ace011a489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639189516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3639189516
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2003009675
Short name T807
Test name
Test status
Simulation time 2547018933 ps
CPU time 9.81 seconds
Started Mar 19 01:14:59 PM PDT 24
Finished Mar 19 01:15:09 PM PDT 24
Peak memory 221012 kb
Host smart-a3b35936-bfe2-4d21-9fb2-c38deadeb695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003009675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2003009675
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3082955440
Short name T262
Test name
Test status
Simulation time 87947956 ps
CPU time 2.86 seconds
Started Mar 19 01:15:11 PM PDT 24
Finished Mar 19 01:15:15 PM PDT 24
Peak memory 234712 kb
Host smart-d6045543-224f-4e27-81d7-00e75583ff41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082955440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3082955440
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3510804819
Short name T376
Test name
Test status
Simulation time 23647132 ps
CPU time 0.78 seconds
Started Mar 19 01:15:09 PM PDT 24
Finished Mar 19 01:15:11 PM PDT 24
Peak memory 206356 kb
Host smart-7cfedac1-6336-4451-9156-0dd50ef2c1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510804819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3510804819
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2241480243
Short name T570
Test name
Test status
Simulation time 17271243580 ps
CPU time 50.8 seconds
Started Mar 19 01:15:18 PM PDT 24
Finished Mar 19 01:16:09 PM PDT 24
Peak memory 249644 kb
Host smart-d14f04d5-042e-4c46-b0fa-6b24558defdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241480243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2241480243
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1889147737
Short name T254
Test name
Test status
Simulation time 20471290520 ps
CPU time 140.09 seconds
Started Mar 19 01:15:17 PM PDT 24
Finished Mar 19 01:17:38 PM PDT 24
Peak memory 250456 kb
Host smart-f4c572ed-afa6-455b-a151-087d8de67a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889147737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1889147737
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2012026111
Short name T311
Test name
Test status
Simulation time 3888537474 ps
CPU time 25.15 seconds
Started Mar 19 01:15:12 PM PDT 24
Finished Mar 19 01:15:37 PM PDT 24
Peak memory 237168 kb
Host smart-b4cefa39-3fc4-4ba9-8ba5-983648eca3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012026111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2012026111
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1513764905
Short name T910
Test name
Test status
Simulation time 35193662804 ps
CPU time 15.52 seconds
Started Mar 19 01:15:12 PM PDT 24
Finished Mar 19 01:15:27 PM PDT 24
Peak memory 233260 kb
Host smart-4b3a0e1b-2834-4b44-9b47-89d96321a946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513764905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1513764905
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1214743062
Short name T338
Test name
Test status
Simulation time 294885311 ps
CPU time 5.63 seconds
Started Mar 19 01:15:08 PM PDT 24
Finished Mar 19 01:15:15 PM PDT 24
Peak memory 237668 kb
Host smart-3e1c4fb7-7d2c-433e-b67e-5d777cc83933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214743062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1214743062
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.262075212
Short name T243
Test name
Test status
Simulation time 46947298828 ps
CPU time 28.56 seconds
Started Mar 19 01:15:10 PM PDT 24
Finished Mar 19 01:15:39 PM PDT 24
Peak memory 228700 kb
Host smart-2a505e12-b09d-426c-a30d-ed18af094e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262075212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.262075212
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3393766628
Short name T507
Test name
Test status
Simulation time 24721861883 ps
CPU time 24.34 seconds
Started Mar 19 01:15:15 PM PDT 24
Finished Mar 19 01:15:39 PM PDT 24
Peak memory 237436 kb
Host smart-c218167c-d7ad-417e-b071-991aba2036f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393766628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3393766628
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_ram_cfg.902650180
Short name T440
Test name
Test status
Simulation time 16026640 ps
CPU time 0.75 seconds
Started Mar 19 01:15:10 PM PDT 24
Finished Mar 19 01:15:11 PM PDT 24
Peak memory 215816 kb
Host smart-41adb7d3-d486-45f4-8876-d7f91dc3c65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902650180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.902650180
Directory /workspace/12.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.56322626
Short name T595
Test name
Test status
Simulation time 372971083 ps
CPU time 3.53 seconds
Started Mar 19 01:15:09 PM PDT 24
Finished Mar 19 01:15:13 PM PDT 24
Peak memory 221152 kb
Host smart-384ce9c6-0081-4e3a-9360-c84730ba5f64
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=56322626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_direc
t.56322626
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.2910541933
Short name T830
Test name
Test status
Simulation time 20045858240 ps
CPU time 129.84 seconds
Started Mar 19 01:15:19 PM PDT 24
Finished Mar 19 01:17:29 PM PDT 24
Peak memory 270776 kb
Host smart-74cad76e-2011-4071-9002-3a006fa71417
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910541933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.2910541933
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.4103503305
Short name T275
Test name
Test status
Simulation time 9800405540 ps
CPU time 38.39 seconds
Started Mar 19 01:15:10 PM PDT 24
Finished Mar 19 01:15:49 PM PDT 24
Peak memory 215880 kb
Host smart-3c4ffc52-4a39-4d6c-abea-e60789553467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103503305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.4103503305
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2647380372
Short name T39
Test name
Test status
Simulation time 901293550 ps
CPU time 5.85 seconds
Started Mar 19 01:15:12 PM PDT 24
Finished Mar 19 01:15:18 PM PDT 24
Peak memory 215752 kb
Host smart-b4991d0e-a0d6-48a5-a9b5-8e9feacdfde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647380372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2647380372
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3004990380
Short name T424
Test name
Test status
Simulation time 98198593 ps
CPU time 1.39 seconds
Started Mar 19 01:15:11 PM PDT 24
Finished Mar 19 01:15:13 PM PDT 24
Peak memory 215768 kb
Host smart-939481b4-6251-4d3b-bb97-fcc98edca028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004990380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3004990380
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.665224480
Short name T451
Test name
Test status
Simulation time 52045856 ps
CPU time 0.87 seconds
Started Mar 19 01:15:09 PM PDT 24
Finished Mar 19 01:15:11 PM PDT 24
Peak memory 205300 kb
Host smart-e3b10a32-15d5-40b8-b7a2-f557b9ed0f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665224480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.665224480
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.3416371629
Short name T555
Test name
Test status
Simulation time 6889831747 ps
CPU time 22.66 seconds
Started Mar 19 01:15:09 PM PDT 24
Finished Mar 19 01:15:32 PM PDT 24
Peak memory 232496 kb
Host smart-15355939-7d58-431f-9d84-e753789a4317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416371629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3416371629
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3261273445
Short name T62
Test name
Test status
Simulation time 25424280 ps
CPU time 0.71 seconds
Started Mar 19 01:15:21 PM PDT 24
Finished Mar 19 01:15:23 PM PDT 24
Peak memory 204212 kb
Host smart-45607952-344d-4969-831c-ecfc3eeddaa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261273445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3261273445
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1887652757
Short name T297
Test name
Test status
Simulation time 457915466 ps
CPU time 2.53 seconds
Started Mar 19 01:15:21 PM PDT 24
Finished Mar 19 01:15:23 PM PDT 24
Peak memory 216832 kb
Host smart-7a307bd0-33d5-427c-ad27-ca8411198659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887652757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1887652757
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.794732252
Short name T599
Test name
Test status
Simulation time 164345037 ps
CPU time 0.74 seconds
Started Mar 19 01:15:18 PM PDT 24
Finished Mar 19 01:15:19 PM PDT 24
Peak memory 206040 kb
Host smart-a965f018-6717-40ca-bc1a-d520924b47da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794732252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.794732252
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.300474203
Short name T962
Test name
Test status
Simulation time 36277106197 ps
CPU time 165.74 seconds
Started Mar 19 01:15:29 PM PDT 24
Finished Mar 19 01:18:15 PM PDT 24
Peak memory 248652 kb
Host smart-216d02ee-7d39-4a94-ad7a-3b2f6483458d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300474203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.300474203
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3337559533
Short name T55
Test name
Test status
Simulation time 20464521182 ps
CPU time 132.76 seconds
Started Mar 19 01:15:17 PM PDT 24
Finished Mar 19 01:17:30 PM PDT 24
Peak memory 255780 kb
Host smart-7cfdb876-1b5f-4c7f-9c72-54eefafec693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337559533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3337559533
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3662044096
Short name T696
Test name
Test status
Simulation time 1363289561 ps
CPU time 11.84 seconds
Started Mar 19 01:15:29 PM PDT 24
Finished Mar 19 01:15:42 PM PDT 24
Peak memory 239912 kb
Host smart-45222c71-1e87-4acb-99b1-2289d084a367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662044096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3662044096
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1566786147
Short name T589
Test name
Test status
Simulation time 23388116076 ps
CPU time 13.5 seconds
Started Mar 19 01:15:20 PM PDT 24
Finished Mar 19 01:15:34 PM PDT 24
Peak memory 223908 kb
Host smart-2fbb43d1-e279-4390-a87f-00132bb06e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566786147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1566786147
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1067977109
Short name T184
Test name
Test status
Simulation time 17152563106 ps
CPU time 43.52 seconds
Started Mar 19 01:15:18 PM PDT 24
Finished Mar 19 01:16:01 PM PDT 24
Peak memory 233100 kb
Host smart-229c00f4-aa31-45f0-9d66-44b8eb78bb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067977109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1067977109
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1568055797
Short name T404
Test name
Test status
Simulation time 18990813353 ps
CPU time 34.95 seconds
Started Mar 19 01:15:18 PM PDT 24
Finished Mar 19 01:15:53 PM PDT 24
Peak memory 229228 kb
Host smart-9852dccf-94d0-4e39-b115-8ce898ec48b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568055797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1568055797
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.105417969
Short name T894
Test name
Test status
Simulation time 19107593708 ps
CPU time 25.08 seconds
Started Mar 19 01:15:29 PM PDT 24
Finished Mar 19 01:15:55 PM PDT 24
Peak memory 234684 kb
Host smart-d41b50aa-8d75-46e1-9bcb-31f1654f4545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105417969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.105417969
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.695388871
Short name T288
Test name
Test status
Simulation time 31272206 ps
CPU time 0.73 seconds
Started Mar 19 01:15:18 PM PDT 24
Finished Mar 19 01:15:19 PM PDT 24
Peak memory 215736 kb
Host smart-f3ecd623-ccc2-41b1-a363-d8418733147d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695388871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.695388871
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1434658851
Short name T707
Test name
Test status
Simulation time 452858666 ps
CPU time 3.3 seconds
Started Mar 19 01:15:18 PM PDT 24
Finished Mar 19 01:15:22 PM PDT 24
Peak memory 219812 kb
Host smart-b96c7964-1030-4d58-992e-8000c599d071
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1434658851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1434658851
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.720786296
Short name T940
Test name
Test status
Simulation time 49889201316 ps
CPU time 335.4 seconds
Started Mar 19 01:15:29 PM PDT 24
Finished Mar 19 01:21:04 PM PDT 24
Peak memory 256136 kb
Host smart-bbdb97a1-786f-4922-b0b7-4af190c4a040
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720786296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.720786296
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1565308895
Short name T896
Test name
Test status
Simulation time 188976567 ps
CPU time 2.6 seconds
Started Mar 19 01:15:20 PM PDT 24
Finished Mar 19 01:15:23 PM PDT 24
Peak memory 215804 kb
Host smart-c28fca68-d74c-4b29-a27c-c6ea57357058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565308895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1565308895
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3861930919
Short name T645
Test name
Test status
Simulation time 1043068251 ps
CPU time 2.61 seconds
Started Mar 19 01:15:21 PM PDT 24
Finished Mar 19 01:15:25 PM PDT 24
Peak memory 215660 kb
Host smart-7040c3e7-3203-4daa-9453-10cb04444941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861930919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3861930919
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3679230018
Short name T402
Test name
Test status
Simulation time 1345454468 ps
CPU time 5.5 seconds
Started Mar 19 01:15:20 PM PDT 24
Finished Mar 19 01:15:26 PM PDT 24
Peak memory 215636 kb
Host smart-efbed2ad-c560-4581-9aa2-5d3a0d8eeba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679230018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3679230018
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2284590768
Short name T945
Test name
Test status
Simulation time 115281747 ps
CPU time 0.76 seconds
Started Mar 19 01:15:19 PM PDT 24
Finished Mar 19 01:15:20 PM PDT 24
Peak memory 205248 kb
Host smart-56ccc77e-e437-43ac-9304-526b884cf985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284590768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2284590768
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2042615495
Short name T664
Test name
Test status
Simulation time 5052068939 ps
CPU time 6.41 seconds
Started Mar 19 01:15:30 PM PDT 24
Finished Mar 19 01:15:37 PM PDT 24
Peak memory 234412 kb
Host smart-1d5d05b3-d303-4f73-8e9e-16b1642e3f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042615495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2042615495
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3837814788
Short name T368
Test name
Test status
Simulation time 12866825 ps
CPU time 0.7 seconds
Started Mar 19 01:15:33 PM PDT 24
Finished Mar 19 01:15:34 PM PDT 24
Peak memory 204884 kb
Host smart-690f72b5-a010-44a0-b949-f9234f40ffd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837814788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3837814788
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1768739769
Short name T188
Test name
Test status
Simulation time 715855280 ps
CPU time 4.6 seconds
Started Mar 19 01:15:25 PM PDT 24
Finished Mar 19 01:15:30 PM PDT 24
Peak memory 233744 kb
Host smart-0b813a95-9f9b-48e3-9c72-10bb2a24b942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768739769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1768739769
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.4077540727
Short name T923
Test name
Test status
Simulation time 15418515 ps
CPU time 0.87 seconds
Started Mar 19 01:15:29 PM PDT 24
Finished Mar 19 01:15:30 PM PDT 24
Peak memory 204984 kb
Host smart-36b24b91-40ea-429c-95d9-518fd8040f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077540727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.4077540727
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.2079763781
Short name T499
Test name
Test status
Simulation time 16477309962 ps
CPU time 91.06 seconds
Started Mar 19 01:15:36 PM PDT 24
Finished Mar 19 01:17:07 PM PDT 24
Peak memory 240576 kb
Host smart-8d6a4b40-9543-4fa6-afbb-f513623e0180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079763781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2079763781
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1493483441
Short name T535
Test name
Test status
Simulation time 1726859036 ps
CPU time 16.74 seconds
Started Mar 19 01:15:38 PM PDT 24
Finished Mar 19 01:15:54 PM PDT 24
Peak memory 220264 kb
Host smart-0358feea-48a1-4a75-a4a0-f0c134c93e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493483441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1493483441
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2276283779
Short name T237
Test name
Test status
Simulation time 99024987490 ps
CPU time 211.49 seconds
Started Mar 19 01:15:35 PM PDT 24
Finished Mar 19 01:19:06 PM PDT 24
Peak memory 265096 kb
Host smart-c5ebaee2-481e-4b12-9d49-a4ad86c55e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276283779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2276283779
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.663976200
Short name T785
Test name
Test status
Simulation time 1334846908 ps
CPU time 14.76 seconds
Started Mar 19 01:15:26 PM PDT 24
Finished Mar 19 01:15:41 PM PDT 24
Peak memory 232304 kb
Host smart-04d7c583-b85d-4e50-b88b-92ae988951a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663976200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.663976200
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3908294640
Short name T860
Test name
Test status
Simulation time 393270359 ps
CPU time 4.38 seconds
Started Mar 19 01:15:27 PM PDT 24
Finished Mar 19 01:15:32 PM PDT 24
Peak memory 224052 kb
Host smart-709d9b57-42ed-4bf9-b6be-623b8f2fd3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908294640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3908294640
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1106027559
Short name T568
Test name
Test status
Simulation time 398150066 ps
CPU time 4.29 seconds
Started Mar 19 01:15:28 PM PDT 24
Finished Mar 19 01:15:33 PM PDT 24
Peak memory 240384 kb
Host smart-8b5c8149-a9c7-4edb-bbe7-e7a23b955f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106027559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1106027559
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.942260768
Short name T850
Test name
Test status
Simulation time 5904979278 ps
CPU time 17.34 seconds
Started Mar 19 01:15:26 PM PDT 24
Finished Mar 19 01:15:43 PM PDT 24
Peak memory 220748 kb
Host smart-3ba64a39-5a14-402d-84f7-6cad3f73819b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942260768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.942260768
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.132554557
Short name T512
Test name
Test status
Simulation time 3430723498 ps
CPU time 10.48 seconds
Started Mar 19 01:15:31 PM PDT 24
Finished Mar 19 01:15:42 PM PDT 24
Peak memory 217548 kb
Host smart-9f7773e1-bff7-4a4f-94b9-de2979fb4ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132554557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.132554557
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.1374419346
Short name T811
Test name
Test status
Simulation time 16465991 ps
CPU time 0.75 seconds
Started Mar 19 01:15:27 PM PDT 24
Finished Mar 19 01:15:27 PM PDT 24
Peak memory 215788 kb
Host smart-cfdde99b-e48d-4ff6-a3b2-f811b40916db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374419346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.1374419346
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3394235044
Short name T412
Test name
Test status
Simulation time 321843423 ps
CPU time 3.16 seconds
Started Mar 19 01:15:35 PM PDT 24
Finished Mar 19 01:15:38 PM PDT 24
Peak memory 218500 kb
Host smart-b28a0250-4547-427c-b06c-45d04aa02197
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3394235044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3394235044
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2759347330
Short name T273
Test name
Test status
Simulation time 2044957678 ps
CPU time 30.44 seconds
Started Mar 19 01:15:29 PM PDT 24
Finished Mar 19 01:16:00 PM PDT 24
Peak memory 217444 kb
Host smart-cc84514b-96df-4235-af66-5ebd2ceb63b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759347330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2759347330
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2398723055
Short name T774
Test name
Test status
Simulation time 1277082674 ps
CPU time 3.5 seconds
Started Mar 19 01:15:30 PM PDT 24
Finished Mar 19 01:15:34 PM PDT 24
Peak memory 215752 kb
Host smart-667f492e-f8e0-46d6-ba33-c3f3916a43a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398723055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2398723055
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1303993251
Short name T790
Test name
Test status
Simulation time 233706079 ps
CPU time 1.63 seconds
Started Mar 19 01:15:27 PM PDT 24
Finished Mar 19 01:15:29 PM PDT 24
Peak memory 215820 kb
Host smart-4857bad5-5357-4b09-af1d-be5c12c2699b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303993251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1303993251
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1587988667
Short name T552
Test name
Test status
Simulation time 41548817 ps
CPU time 0.81 seconds
Started Mar 19 01:15:26 PM PDT 24
Finished Mar 19 01:15:27 PM PDT 24
Peak memory 205260 kb
Host smart-0ba5174a-64e1-4e83-8f6d-dea6b4aca049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587988667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1587988667
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1685503237
Short name T892
Test name
Test status
Simulation time 3582097276 ps
CPU time 3.04 seconds
Started Mar 19 01:15:25 PM PDT 24
Finished Mar 19 01:15:28 PM PDT 24
Peak memory 218084 kb
Host smart-91b9cb2e-3a43-4663-8228-8b7194643fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685503237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1685503237
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.325142787
Short name T964
Test name
Test status
Simulation time 33903179 ps
CPU time 0.75 seconds
Started Mar 19 01:15:53 PM PDT 24
Finished Mar 19 01:15:54 PM PDT 24
Peak memory 204976 kb
Host smart-64a547de-3aa6-4bee-86ce-fda2c54ddcd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325142787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.325142787
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.10074671
Short name T204
Test name
Test status
Simulation time 13194371631 ps
CPU time 7.37 seconds
Started Mar 19 01:15:46 PM PDT 24
Finished Mar 19 01:15:53 PM PDT 24
Peak memory 219460 kb
Host smart-e0298302-01e1-4ab1-a7ea-6cbeca45c731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10074671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.10074671
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3002778824
Short name T556
Test name
Test status
Simulation time 26357678 ps
CPU time 0.76 seconds
Started Mar 19 01:15:37 PM PDT 24
Finished Mar 19 01:15:38 PM PDT 24
Peak memory 206368 kb
Host smart-d066cc01-7f3e-4dd8-bfe7-d658f356b3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002778824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3002778824
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1963372189
Short name T223
Test name
Test status
Simulation time 9473592543 ps
CPU time 157.87 seconds
Started Mar 19 01:15:48 PM PDT 24
Finished Mar 19 01:18:26 PM PDT 24
Peak memory 271848 kb
Host smart-ed2fb3a6-a62e-4bfd-81d4-8eeec671b5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963372189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1963372189
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3622116027
Short name T355
Test name
Test status
Simulation time 763753258 ps
CPU time 12.48 seconds
Started Mar 19 01:15:46 PM PDT 24
Finished Mar 19 01:16:00 PM PDT 24
Peak memory 233280 kb
Host smart-fcfff169-18a2-4b67-8971-e821746524e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622116027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3622116027
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3530515655
Short name T823
Test name
Test status
Simulation time 900345494 ps
CPU time 5.13 seconds
Started Mar 19 01:15:34 PM PDT 24
Finished Mar 19 01:15:40 PM PDT 24
Peak memory 234068 kb
Host smart-472f8046-a3ab-421b-b69c-0cca2d1810a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530515655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3530515655
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.4275013286
Short name T930
Test name
Test status
Simulation time 112042644381 ps
CPU time 41.19 seconds
Started Mar 19 01:15:49 PM PDT 24
Finished Mar 19 01:16:31 PM PDT 24
Peak memory 239860 kb
Host smart-35d3aa9f-eeb0-4f9d-8bae-bc7370ea3395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275013286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.4275013286
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.4110562836
Short name T916
Test name
Test status
Simulation time 667790148 ps
CPU time 3.55 seconds
Started Mar 19 01:15:34 PM PDT 24
Finished Mar 19 01:15:38 PM PDT 24
Peak memory 233176 kb
Host smart-86264334-96dc-4c02-92ad-083563e1db2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110562836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.4110562836
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2289529836
Short name T181
Test name
Test status
Simulation time 4859908263 ps
CPU time 13.42 seconds
Started Mar 19 01:15:37 PM PDT 24
Finished Mar 19 01:15:50 PM PDT 24
Peak memory 233276 kb
Host smart-f4ab1b94-ed28-4795-9178-b17a10872e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289529836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2289529836
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.950717429
Short name T951
Test name
Test status
Simulation time 16282342 ps
CPU time 0.78 seconds
Started Mar 19 01:15:35 PM PDT 24
Finished Mar 19 01:15:36 PM PDT 24
Peak memory 215744 kb
Host smart-6ff54176-a6e4-4117-a919-3a11af2ba091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950717429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.950717429
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3797664069
Short name T652
Test name
Test status
Simulation time 8643465772 ps
CPU time 7.22 seconds
Started Mar 19 01:15:48 PM PDT 24
Finished Mar 19 01:15:56 PM PDT 24
Peak memory 222388 kb
Host smart-92d5a3d4-df32-49f8-919c-98d604600926
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3797664069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3797664069
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.4174546191
Short name T485
Test name
Test status
Simulation time 159657589 ps
CPU time 1.01 seconds
Started Mar 19 01:15:48 PM PDT 24
Finished Mar 19 01:15:49 PM PDT 24
Peak memory 206512 kb
Host smart-457e24a7-5c44-40b9-8c8d-e86f9e38db68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174546191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.4174546191
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1119261552
Short name T495
Test name
Test status
Simulation time 23561177983 ps
CPU time 77.4 seconds
Started Mar 19 01:15:36 PM PDT 24
Finished Mar 19 01:16:54 PM PDT 24
Peak memory 215860 kb
Host smart-659801aa-9e84-4d7b-a28e-181bc9165e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119261552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1119261552
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.965817750
Short name T606
Test name
Test status
Simulation time 1561651206 ps
CPU time 6.8 seconds
Started Mar 19 01:15:34 PM PDT 24
Finished Mar 19 01:15:41 PM PDT 24
Peak memory 215712 kb
Host smart-517be09c-4126-4f3e-b926-e415438bae34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965817750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.965817750
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1558437029
Short name T490
Test name
Test status
Simulation time 122052611 ps
CPU time 0.99 seconds
Started Mar 19 01:15:34 PM PDT 24
Finished Mar 19 01:15:35 PM PDT 24
Peak memory 206544 kb
Host smart-759aaa52-523b-4412-a59c-af5dd92994f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558437029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1558437029
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.430256573
Short name T290
Test name
Test status
Simulation time 67487015 ps
CPU time 0.78 seconds
Started Mar 19 01:15:38 PM PDT 24
Finished Mar 19 01:15:39 PM PDT 24
Peak memory 205216 kb
Host smart-c4fccc60-6acf-460f-80c9-4a224043b13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430256573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.430256573
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.907802478
Short name T258
Test name
Test status
Simulation time 22600900339 ps
CPU time 39.3 seconds
Started Mar 19 01:15:52 PM PDT 24
Finished Mar 19 01:16:32 PM PDT 24
Peak memory 245980 kb
Host smart-6653ef5d-bcde-43d6-85bb-58a637bb667a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907802478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.907802478
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.885764991
Short name T371
Test name
Test status
Simulation time 18435664 ps
CPU time 0.72 seconds
Started Mar 19 01:15:57 PM PDT 24
Finished Mar 19 01:15:58 PM PDT 24
Peak memory 204308 kb
Host smart-f44224a7-dba2-458b-808c-7f401e4532ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885764991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.885764991
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3502066347
Short name T11
Test name
Test status
Simulation time 2163410554 ps
CPU time 4.17 seconds
Started Mar 19 01:15:51 PM PDT 24
Finished Mar 19 01:15:55 PM PDT 24
Peak memory 233972 kb
Host smart-88ad1d72-db2c-46e2-9423-a387c25a8223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502066347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3502066347
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1633086553
Short name T814
Test name
Test status
Simulation time 37306160 ps
CPU time 0.83 seconds
Started Mar 19 01:15:55 PM PDT 24
Finished Mar 19 01:15:57 PM PDT 24
Peak memory 206084 kb
Host smart-fe2d5cb9-b1bc-45e9-ba14-7e3e6af2b29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633086553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1633086553
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1855970764
Short name T220
Test name
Test status
Simulation time 356166851229 ps
CPU time 422.75 seconds
Started Mar 19 01:15:51 PM PDT 24
Finished Mar 19 01:22:54 PM PDT 24
Peak memory 265064 kb
Host smart-40514697-681c-4693-9457-5a7b24445184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855970764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1855970764
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2026938694
Short name T960
Test name
Test status
Simulation time 33172161500 ps
CPU time 140.92 seconds
Started Mar 19 01:15:49 PM PDT 24
Finished Mar 19 01:18:10 PM PDT 24
Peak memory 248764 kb
Host smart-61950d64-0a95-4853-b52c-e9814ccf8f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026938694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2026938694
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.4290463243
Short name T176
Test name
Test status
Simulation time 47465111322 ps
CPU time 383.68 seconds
Started Mar 19 01:15:59 PM PDT 24
Finished Mar 19 01:22:22 PM PDT 24
Peak memory 256872 kb
Host smart-365e581b-d166-4363-82b2-10d99327f1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290463243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.4290463243
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1779891105
Short name T405
Test name
Test status
Simulation time 30656004497 ps
CPU time 37.9 seconds
Started Mar 19 01:15:49 PM PDT 24
Finished Mar 19 01:16:27 PM PDT 24
Peak memory 248640 kb
Host smart-687c9cc7-c34a-4803-b591-2c5008b42b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779891105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1779891105
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.3093232216
Short name T461
Test name
Test status
Simulation time 14954167430 ps
CPU time 13.13 seconds
Started Mar 19 01:15:50 PM PDT 24
Finished Mar 19 01:16:03 PM PDT 24
Peak memory 233432 kb
Host smart-a39d37a3-eac8-4dd2-a836-30f0c4d8f39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093232216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3093232216
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1412140406
Short name T821
Test name
Test status
Simulation time 232408530 ps
CPU time 2.45 seconds
Started Mar 19 01:15:52 PM PDT 24
Finished Mar 19 01:15:55 PM PDT 24
Peak memory 232204 kb
Host smart-e90ee419-7a4d-47d0-b3c4-a027739dafdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412140406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1412140406
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.556785369
Short name T506
Test name
Test status
Simulation time 8843407871 ps
CPU time 19.57 seconds
Started Mar 19 01:15:52 PM PDT 24
Finished Mar 19 01:16:12 PM PDT 24
Peak memory 218436 kb
Host smart-3c04f718-03d3-46a5-aeaa-aa769407745d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556785369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap
.556785369
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3785430439
Short name T162
Test name
Test status
Simulation time 15415133955 ps
CPU time 20.33 seconds
Started Mar 19 01:15:52 PM PDT 24
Finished Mar 19 01:16:13 PM PDT 24
Peak memory 234172 kb
Host smart-1e6e9a36-92af-45b1-9a14-6fb88db6c75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785430439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3785430439
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.2895035673
Short name T293
Test name
Test status
Simulation time 97985147 ps
CPU time 0.72 seconds
Started Mar 19 01:15:47 PM PDT 24
Finished Mar 19 01:15:48 PM PDT 24
Peak memory 215808 kb
Host smart-4406f439-bd39-446a-abae-d72293f877cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895035673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.2895035673
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1795532012
Short name T143
Test name
Test status
Simulation time 298320188 ps
CPU time 3.31 seconds
Started Mar 19 01:15:49 PM PDT 24
Finished Mar 19 01:15:53 PM PDT 24
Peak memory 222044 kb
Host smart-be13928b-bf36-4f91-95ca-5e94e0d2b2d4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1795532012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1795532012
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3597552594
Short name T452
Test name
Test status
Simulation time 17030752905 ps
CPU time 109.24 seconds
Started Mar 19 01:15:57 PM PDT 24
Finished Mar 19 01:17:47 PM PDT 24
Peak memory 237436 kb
Host smart-ef8cd36c-8282-4935-8e3c-e13ab98e0c4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597552594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3597552594
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2752808595
Short name T330
Test name
Test status
Simulation time 2656398798 ps
CPU time 25.95 seconds
Started Mar 19 01:15:48 PM PDT 24
Finished Mar 19 01:16:14 PM PDT 24
Peak memory 215892 kb
Host smart-77f2db77-b491-462e-a62a-e6f4dcdd3ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752808595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2752808595
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2554544833
Short name T299
Test name
Test status
Simulation time 2879868374 ps
CPU time 15.66 seconds
Started Mar 19 01:15:53 PM PDT 24
Finished Mar 19 01:16:09 PM PDT 24
Peak memory 215916 kb
Host smart-0062f819-ca55-410b-9b55-2ae0968fcdc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554544833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2554544833
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2436111692
Short name T781
Test name
Test status
Simulation time 778532615 ps
CPU time 12.69 seconds
Started Mar 19 01:15:48 PM PDT 24
Finished Mar 19 01:16:01 PM PDT 24
Peak memory 215856 kb
Host smart-2e5b5003-ecb1-4121-9d06-8fee043396fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436111692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2436111692
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2234969897
Short name T291
Test name
Test status
Simulation time 35753038 ps
CPU time 0.86 seconds
Started Mar 19 01:15:52 PM PDT 24
Finished Mar 19 01:15:53 PM PDT 24
Peak memory 205220 kb
Host smart-934735f4-63ef-418d-acd0-891cf799948a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234969897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2234969897
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3476003908
Short name T567
Test name
Test status
Simulation time 3560527569 ps
CPU time 19.37 seconds
Started Mar 19 01:15:53 PM PDT 24
Finished Mar 19 01:16:13 PM PDT 24
Peak memory 223980 kb
Host smart-ac2beda5-d079-48ae-b437-608264225e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476003908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3476003908
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.620040221
Short name T727
Test name
Test status
Simulation time 56808184 ps
CPU time 0.72 seconds
Started Mar 19 01:16:04 PM PDT 24
Finished Mar 19 01:16:05 PM PDT 24
Peak memory 204836 kb
Host smart-0fd70cc8-ee3a-45af-96ec-4f787f56d57a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620040221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.620040221
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.447544945
Short name T561
Test name
Test status
Simulation time 696066296 ps
CPU time 3.3 seconds
Started Mar 19 01:15:56 PM PDT 24
Finished Mar 19 01:16:00 PM PDT 24
Peak memory 236084 kb
Host smart-90c8746a-9f76-4a5c-b2b4-ac68b95604ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447544945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.447544945
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1589596005
Short name T433
Test name
Test status
Simulation time 61911788 ps
CPU time 0.76 seconds
Started Mar 19 01:15:58 PM PDT 24
Finished Mar 19 01:15:59 PM PDT 24
Peak memory 205372 kb
Host smart-6cc907a7-df41-46c9-9a9f-6e564bab9d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589596005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1589596005
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.3817913692
Short name T1
Test name
Test status
Simulation time 35340698096 ps
CPU time 84.65 seconds
Started Mar 19 01:16:03 PM PDT 24
Finished Mar 19 01:17:28 PM PDT 24
Peak memory 248664 kb
Host smart-576b56b2-5487-49e6-a24a-a7f366d7c84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817913692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3817913692
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3438781940
Short name T839
Test name
Test status
Simulation time 2635469662 ps
CPU time 15.9 seconds
Started Mar 19 01:16:01 PM PDT 24
Finished Mar 19 01:16:17 PM PDT 24
Peak memory 233336 kb
Host smart-6c94c234-1b7f-4057-9355-50dccffac1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438781940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3438781940
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.140229430
Short name T851
Test name
Test status
Simulation time 2333999599 ps
CPU time 9.16 seconds
Started Mar 19 01:15:55 PM PDT 24
Finished Mar 19 01:16:05 PM PDT 24
Peak memory 219420 kb
Host smart-07a97e2d-2a30-4c26-ab37-a5db42130884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140229430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.140229430
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1006895553
Short name T463
Test name
Test status
Simulation time 202851398 ps
CPU time 2.2 seconds
Started Mar 19 01:16:01 PM PDT 24
Finished Mar 19 01:16:03 PM PDT 24
Peak memory 217940 kb
Host smart-70eed4d9-325b-438d-83e8-fbc252b56aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006895553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1006895553
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.499357050
Short name T914
Test name
Test status
Simulation time 19804876393 ps
CPU time 29.9 seconds
Started Mar 19 01:15:58 PM PDT 24
Finished Mar 19 01:16:28 PM PDT 24
Peak memory 236516 kb
Host smart-27cdae8c-4416-48b1-9637-abaf5c27167f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499357050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.499357050
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1760075798
Short name T620
Test name
Test status
Simulation time 9519669376 ps
CPU time 15.13 seconds
Started Mar 19 01:15:59 PM PDT 24
Finished Mar 19 01:16:14 PM PDT 24
Peak memory 230176 kb
Host smart-92ecc1e4-6608-4bf7-ad3e-f2459d505b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760075798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1760075798
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.73331379
Short name T72
Test name
Test status
Simulation time 43148448 ps
CPU time 0.76 seconds
Started Mar 19 01:15:57 PM PDT 24
Finished Mar 19 01:15:58 PM PDT 24
Peak memory 215716 kb
Host smart-b8750b30-aac8-4bc8-959e-55706270ef2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73331379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.73331379
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3030649110
Short name T662
Test name
Test status
Simulation time 1099897638 ps
CPU time 4.53 seconds
Started Mar 19 01:16:03 PM PDT 24
Finished Mar 19 01:16:07 PM PDT 24
Peak memory 219272 kb
Host smart-cc6e4ad5-18fb-45d9-abb4-0b64edeeed32
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3030649110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3030649110
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3733430525
Short name T928
Test name
Test status
Simulation time 221964363 ps
CPU time 1.11 seconds
Started Mar 19 01:16:03 PM PDT 24
Finished Mar 19 01:16:05 PM PDT 24
Peak memory 206572 kb
Host smart-5870e2c5-fc29-4821-8ec7-1c298502500d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733430525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3733430525
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.577155725
Short name T272
Test name
Test status
Simulation time 5210532175 ps
CPU time 10.63 seconds
Started Mar 19 01:15:58 PM PDT 24
Finished Mar 19 01:16:09 PM PDT 24
Peak memory 215964 kb
Host smart-2caa6f9c-244b-4efb-b29a-a4ede9368481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577155725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.577155725
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2130462277
Short name T605
Test name
Test status
Simulation time 9426490297 ps
CPU time 4.9 seconds
Started Mar 19 01:15:59 PM PDT 24
Finished Mar 19 01:16:05 PM PDT 24
Peak memory 215796 kb
Host smart-132a3cbb-bf5c-46da-9b13-74ef7b32d398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130462277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2130462277
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.518532943
Short name T312
Test name
Test status
Simulation time 178949279 ps
CPU time 1.76 seconds
Started Mar 19 01:15:59 PM PDT 24
Finished Mar 19 01:16:01 PM PDT 24
Peak memory 215824 kb
Host smart-d22204ef-7cea-4d85-b4f6-202267639f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518532943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.518532943
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2673482042
Short name T812
Test name
Test status
Simulation time 115789659 ps
CPU time 0.83 seconds
Started Mar 19 01:15:59 PM PDT 24
Finished Mar 19 01:16:00 PM PDT 24
Peak memory 205264 kb
Host smart-209da1eb-d015-4c12-99fb-8fc7075d5de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673482042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2673482042
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2663143666
Short name T826
Test name
Test status
Simulation time 1459452378 ps
CPU time 6.5 seconds
Started Mar 19 01:15:59 PM PDT 24
Finished Mar 19 01:16:05 PM PDT 24
Peak memory 216924 kb
Host smart-cd612840-f7c1-4ed4-8a3b-68b7f2714e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663143666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2663143666
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1162456735
Short name T61
Test name
Test status
Simulation time 12348665 ps
CPU time 0.72 seconds
Started Mar 19 01:16:13 PM PDT 24
Finished Mar 19 01:16:14 PM PDT 24
Peak memory 204924 kb
Host smart-63355dfd-1f43-4926-af51-6a4dafb4c0a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162456735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1162456735
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2528400926
Short name T85
Test name
Test status
Simulation time 303930582 ps
CPU time 2.63 seconds
Started Mar 19 01:16:10 PM PDT 24
Finished Mar 19 01:16:12 PM PDT 24
Peak memory 218292 kb
Host smart-a416972e-ac23-4773-8ddd-70481ca4f8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528400926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2528400926
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3260390046
Short name T347
Test name
Test status
Simulation time 115595700 ps
CPU time 0.79 seconds
Started Mar 19 01:16:05 PM PDT 24
Finished Mar 19 01:16:07 PM PDT 24
Peak memory 206380 kb
Host smart-3196982f-0f24-4c3a-978c-dbf6a3b1d90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260390046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3260390046
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3929240682
Short name T93
Test name
Test status
Simulation time 4675727644 ps
CPU time 18.14 seconds
Started Mar 19 01:16:09 PM PDT 24
Finished Mar 19 01:16:28 PM PDT 24
Peak memory 238868 kb
Host smart-d4df790c-bafa-4775-b0c1-e7b5383b16d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929240682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3929240682
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3370651281
Short name T593
Test name
Test status
Simulation time 345324857393 ps
CPU time 330.61 seconds
Started Mar 19 01:16:10 PM PDT 24
Finished Mar 19 01:21:41 PM PDT 24
Peak memory 256996 kb
Host smart-e1885d68-8d17-4716-8638-8e5639402997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370651281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3370651281
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1173220557
Short name T267
Test name
Test status
Simulation time 2985234466 ps
CPU time 13.72 seconds
Started Mar 19 01:16:11 PM PDT 24
Finished Mar 19 01:16:25 PM PDT 24
Peak memory 247840 kb
Host smart-b2bd7926-292b-42bf-af24-6411f2a0ee4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173220557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1173220557
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1419350998
Short name T198
Test name
Test status
Simulation time 1713269558 ps
CPU time 3.34 seconds
Started Mar 19 01:16:05 PM PDT 24
Finished Mar 19 01:16:09 PM PDT 24
Peak memory 223924 kb
Host smart-3231326f-7e36-4728-982a-f83796b3d596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419350998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1419350998
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.981477663
Short name T202
Test name
Test status
Simulation time 883404538 ps
CPU time 5.22 seconds
Started Mar 19 01:16:04 PM PDT 24
Finished Mar 19 01:16:10 PM PDT 24
Peak memory 233044 kb
Host smart-7f6ff371-73ef-4bd3-8204-1e854b4a15a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981477663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.981477663
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3885983123
Short name T764
Test name
Test status
Simulation time 307685926 ps
CPU time 2.34 seconds
Started Mar 19 01:16:02 PM PDT 24
Finished Mar 19 01:16:04 PM PDT 24
Peak memory 218168 kb
Host smart-cae16902-17b3-496b-ad56-6eeb120934bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885983123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3885983123
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.3426299705
Short name T519
Test name
Test status
Simulation time 1092987619 ps
CPU time 5.09 seconds
Started Mar 19 01:16:06 PM PDT 24
Finished Mar 19 01:16:12 PM PDT 24
Peak memory 232816 kb
Host smart-d5a4943c-ec52-44ef-9dbe-b3122df14c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426299705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3426299705
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.1168307848
Short name T482
Test name
Test status
Simulation time 31485428 ps
CPU time 0.76 seconds
Started Mar 19 01:16:05 PM PDT 24
Finished Mar 19 01:16:06 PM PDT 24
Peak memory 215800 kb
Host smart-270763d1-7305-4a16-8c9c-11461b810b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168307848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.1168307848
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2353903714
Short name T9
Test name
Test status
Simulation time 350908568 ps
CPU time 4.32 seconds
Started Mar 19 01:16:13 PM PDT 24
Finished Mar 19 01:16:18 PM PDT 24
Peak memory 221600 kb
Host smart-e96effa6-01fb-4d92-aee0-27764b5b1204
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2353903714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2353903714
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1225871367
Short name T240
Test name
Test status
Simulation time 67956762401 ps
CPU time 142.82 seconds
Started Mar 19 01:16:12 PM PDT 24
Finished Mar 19 01:18:35 PM PDT 24
Peak memory 273248 kb
Host smart-2214d833-fced-47c8-ac2d-8037f60b2bbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225871367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1225871367
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3675695284
Short name T364
Test name
Test status
Simulation time 286607974 ps
CPU time 5.99 seconds
Started Mar 19 01:16:05 PM PDT 24
Finished Mar 19 01:16:11 PM PDT 24
Peak memory 215752 kb
Host smart-38a2d234-b0e6-45af-9954-fbef107168ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675695284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3675695284
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1115834761
Short name T52
Test name
Test status
Simulation time 13599160483 ps
CPU time 19.34 seconds
Started Mar 19 01:16:05 PM PDT 24
Finished Mar 19 01:16:25 PM PDT 24
Peak memory 215856 kb
Host smart-9b044fef-b12e-4d6e-a479-b01edf62c84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115834761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1115834761
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1252661823
Short name T843
Test name
Test status
Simulation time 116356284 ps
CPU time 2.09 seconds
Started Mar 19 01:16:05 PM PDT 24
Finished Mar 19 01:16:07 PM PDT 24
Peak memory 215708 kb
Host smart-35d7dd10-0de5-4c5c-985c-0d3e1e66f6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252661823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1252661823
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2900836685
Short name T723
Test name
Test status
Simulation time 234321186 ps
CPU time 1.1 seconds
Started Mar 19 01:16:03 PM PDT 24
Finished Mar 19 01:16:05 PM PDT 24
Peak memory 206328 kb
Host smart-767b2493-76f7-41c1-a7b9-8105a40e8df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900836685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2900836685
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2181792920
Short name T832
Test name
Test status
Simulation time 8728908046 ps
CPU time 25.63 seconds
Started Mar 19 01:16:15 PM PDT 24
Finished Mar 19 01:16:40 PM PDT 24
Peak memory 230796 kb
Host smart-5e182f1c-21da-4023-9a95-26715818596f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181792920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2181792920
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1386684712
Short name T631
Test name
Test status
Simulation time 22084231 ps
CPU time 0.73 seconds
Started Mar 19 01:16:28 PM PDT 24
Finished Mar 19 01:16:29 PM PDT 24
Peak memory 204288 kb
Host smart-46d4efd3-6de0-4d96-a0cd-948d987e4544
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386684712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1386684712
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2080048827
Short name T423
Test name
Test status
Simulation time 736737411 ps
CPU time 3.16 seconds
Started Mar 19 01:16:19 PM PDT 24
Finished Mar 19 01:16:22 PM PDT 24
Peak memory 233324 kb
Host smart-3f5d7d9f-8cf5-4647-b628-6a9c26ff0976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080048827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2080048827
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.492912997
Short name T575
Test name
Test status
Simulation time 56662916 ps
CPU time 0.79 seconds
Started Mar 19 01:16:11 PM PDT 24
Finished Mar 19 01:16:12 PM PDT 24
Peak memory 206048 kb
Host smart-deaa53c4-5f83-4dc1-a392-00e16338807a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492912997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.492912997
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.3303833729
Short name T805
Test name
Test status
Simulation time 10124079864 ps
CPU time 51 seconds
Started Mar 19 01:16:22 PM PDT 24
Finished Mar 19 01:17:13 PM PDT 24
Peak memory 233332 kb
Host smart-7332e140-847e-4849-89cd-a369ebbe3180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303833729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3303833729
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.802517173
Short name T747
Test name
Test status
Simulation time 5877477870 ps
CPU time 47.38 seconds
Started Mar 19 01:16:20 PM PDT 24
Finished Mar 19 01:17:07 PM PDT 24
Peak memory 255600 kb
Host smart-b70186d7-da80-4295-acf6-ed6a3a66ad1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802517173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.802517173
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2324422906
Short name T529
Test name
Test status
Simulation time 13402439590 ps
CPU time 14.37 seconds
Started Mar 19 01:16:20 PM PDT 24
Finished Mar 19 01:16:34 PM PDT 24
Peak memory 247848 kb
Host smart-d12c1b38-1541-409e-b7f0-8fb6d7e0feef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324422906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2324422906
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1226182934
Short name T954
Test name
Test status
Simulation time 849241182 ps
CPU time 3.53 seconds
Started Mar 19 01:16:20 PM PDT 24
Finished Mar 19 01:16:24 PM PDT 24
Peak memory 224016 kb
Host smart-19b686d3-ecfc-4e23-9a55-b0d08f62db19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226182934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1226182934
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.4033011259
Short name T259
Test name
Test status
Simulation time 22890164224 ps
CPU time 35.97 seconds
Started Mar 19 01:16:21 PM PDT 24
Finished Mar 19 01:16:57 PM PDT 24
Peak memory 219444 kb
Host smart-4001c9e0-aefe-47d0-9048-edb2c2437a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033011259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.4033011259
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.174546361
Short name T582
Test name
Test status
Simulation time 227374235 ps
CPU time 2.72 seconds
Started Mar 19 01:16:23 PM PDT 24
Finished Mar 19 01:16:26 PM PDT 24
Peak memory 223980 kb
Host smart-20caecaf-b00a-402f-805c-1291e50242b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174546361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.174546361
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.37150629
Short name T509
Test name
Test status
Simulation time 1612989845 ps
CPU time 7.17 seconds
Started Mar 19 01:16:19 PM PDT 24
Finished Mar 19 01:16:27 PM PDT 24
Peak memory 218208 kb
Host smart-457cd9db-e24b-4301-808a-1a7e2103e83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37150629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.37150629
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.2043418707
Short name T71
Test name
Test status
Simulation time 24292988 ps
CPU time 0.74 seconds
Started Mar 19 01:16:13 PM PDT 24
Finished Mar 19 01:16:13 PM PDT 24
Peak memory 215784 kb
Host smart-0712ae74-5d49-4366-bd64-bf1f33fb8c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043418707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.2043418707
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2941600539
Short name T388
Test name
Test status
Simulation time 1064719257 ps
CPU time 4.47 seconds
Started Mar 19 01:16:20 PM PDT 24
Finished Mar 19 01:16:25 PM PDT 24
Peak memory 222056 kb
Host smart-938d10fe-4fb5-4c07-a121-f30d5748efa2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2941600539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2941600539
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2371308516
Short name T460
Test name
Test status
Simulation time 54782224442 ps
CPU time 69.7 seconds
Started Mar 19 01:16:27 PM PDT 24
Finished Mar 19 01:17:37 PM PDT 24
Peak memory 259092 kb
Host smart-78cb5bf2-4882-44ff-b997-1288c2d56b79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371308516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2371308516
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1767065914
Short name T408
Test name
Test status
Simulation time 1808512405 ps
CPU time 6.64 seconds
Started Mar 19 01:16:27 PM PDT 24
Finished Mar 19 01:16:34 PM PDT 24
Peak memory 215792 kb
Host smart-de0105df-e6af-4f56-95bc-7a817ff6ecfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767065914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1767065914
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2324309336
Short name T878
Test name
Test status
Simulation time 996590838 ps
CPU time 7.66 seconds
Started Mar 19 01:16:17 PM PDT 24
Finished Mar 19 01:16:24 PM PDT 24
Peak memory 215732 kb
Host smart-c0d0d135-8b2a-4f82-b794-290def9cbf91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324309336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2324309336
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3271572512
Short name T819
Test name
Test status
Simulation time 13283898 ps
CPU time 0.73 seconds
Started Mar 19 01:16:27 PM PDT 24
Finished Mar 19 01:16:27 PM PDT 24
Peak memory 205272 kb
Host smart-3f2685a7-a7e9-43b5-bd4d-0c88f5a1fd7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271572512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3271572512
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1042466496
Short name T540
Test name
Test status
Simulation time 106018114 ps
CPU time 0.96 seconds
Started Mar 19 01:16:27 PM PDT 24
Finished Mar 19 01:16:28 PM PDT 24
Peak memory 206296 kb
Host smart-f7aef3ec-879e-4794-bc65-a339f63cdd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042466496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1042466496
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2203737668
Short name T766
Test name
Test status
Simulation time 1104157742 ps
CPU time 6.97 seconds
Started Mar 19 01:16:22 PM PDT 24
Finished Mar 19 01:16:29 PM PDT 24
Peak memory 219404 kb
Host smart-a11fb22a-02ea-479e-bb7d-71a8fd9113b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203737668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2203737668
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3739384128
Short name T840
Test name
Test status
Simulation time 30654020 ps
CPU time 0.68 seconds
Started Mar 19 01:13:18 PM PDT 24
Finished Mar 19 01:13:19 PM PDT 24
Peak memory 204788 kb
Host smart-135d5d51-d4b9-4802-972a-0db0dde0a9e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739384128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
739384128
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1501244031
Short name T187
Test name
Test status
Simulation time 1652818453 ps
CPU time 7.11 seconds
Started Mar 19 01:13:04 PM PDT 24
Finished Mar 19 01:13:11 PM PDT 24
Peak memory 220492 kb
Host smart-b32c3288-3d9c-4b27-8c67-20f1a1958031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501244031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1501244031
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1318182323
Short name T688
Test name
Test status
Simulation time 61084255 ps
CPU time 0.77 seconds
Started Mar 19 01:13:04 PM PDT 24
Finished Mar 19 01:13:05 PM PDT 24
Peak memory 206352 kb
Host smart-480d65df-b4a0-4c65-b954-441dfde12910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318182323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1318182323
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1686009848
Short name T167
Test name
Test status
Simulation time 9177442815 ps
CPU time 85.35 seconds
Started Mar 19 01:13:17 PM PDT 24
Finished Mar 19 01:14:43 PM PDT 24
Peak memory 256736 kb
Host smart-2f93e5d7-2a90-46f3-a2e9-b61ae1150605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686009848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1686009848
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.4017486951
Short name T137
Test name
Test status
Simulation time 3020688450 ps
CPU time 66.86 seconds
Started Mar 19 01:13:16 PM PDT 24
Finished Mar 19 01:14:23 PM PDT 24
Peak memory 248760 kb
Host smart-170bddcb-4ad2-4fba-9c99-99f7cf10d1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017486951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.4017486951
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.830601908
Short name T792
Test name
Test status
Simulation time 63450336065 ps
CPU time 88.8 seconds
Started Mar 19 01:13:16 PM PDT 24
Finished Mar 19 01:14:45 PM PDT 24
Peak memory 251384 kb
Host smart-487643e7-1beb-4516-a68c-ff4e7edd0fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830601908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
830601908
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2870660033
Short name T801
Test name
Test status
Simulation time 401774942 ps
CPU time 7.47 seconds
Started Mar 19 01:13:18 PM PDT 24
Finished Mar 19 01:13:25 PM PDT 24
Peak memory 231500 kb
Host smart-c33bd959-ade8-412a-b62f-6c85c4b69ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870660033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2870660033
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2623040624
Short name T802
Test name
Test status
Simulation time 5105273165 ps
CPU time 14.25 seconds
Started Mar 19 01:13:05 PM PDT 24
Finished Mar 19 01:13:19 PM PDT 24
Peak memory 219100 kb
Host smart-13972a50-81ea-4226-9729-fe6ae7373d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623040624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2623040624
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3602431558
Short name T735
Test name
Test status
Simulation time 6433721986 ps
CPU time 6.74 seconds
Started Mar 19 01:13:07 PM PDT 24
Finished Mar 19 01:13:14 PM PDT 24
Peak memory 222572 kb
Host smart-14dadd0b-15ae-4d75-9d21-047fefccff3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602431558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3602431558
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1533835906
Short name T782
Test name
Test status
Simulation time 59943126247 ps
CPU time 35.57 seconds
Started Mar 19 01:13:06 PM PDT 24
Finished Mar 19 01:13:41 PM PDT 24
Peak memory 232200 kb
Host smart-e5a65d5b-bd21-4837-ab18-ca067833ca6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533835906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1533835906
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.4087383979
Short name T315
Test name
Test status
Simulation time 46142864 ps
CPU time 0.74 seconds
Started Mar 19 01:13:06 PM PDT 24
Finished Mar 19 01:13:07 PM PDT 24
Peak memory 215792 kb
Host smart-49dbf129-7070-44a9-b5c0-89b0d473e083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087383979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.4087383979
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.247506273
Short name T391
Test name
Test status
Simulation time 3387100599 ps
CPU time 7.79 seconds
Started Mar 19 01:13:17 PM PDT 24
Finished Mar 19 01:13:24 PM PDT 24
Peak memory 222796 kb
Host smart-5004df00-0c6e-41b9-9d54-3519c6715215
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=247506273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.247506273
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2067404740
Short name T75
Test name
Test status
Simulation time 91667341 ps
CPU time 1.2 seconds
Started Mar 19 01:13:15 PM PDT 24
Finished Mar 19 01:13:16 PM PDT 24
Peak memory 234732 kb
Host smart-3a79115e-f2a5-4c35-8806-ad840741e1df
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067404740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2067404740
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3103663505
Short name T877
Test name
Test status
Simulation time 73671213190 ps
CPU time 527.75 seconds
Started Mar 19 01:13:16 PM PDT 24
Finished Mar 19 01:22:04 PM PDT 24
Peak memory 248792 kb
Host smart-1b68c63a-b2d9-45cb-a896-cd3dbc5cfca2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103663505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3103663505
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2166388707
Short name T824
Test name
Test status
Simulation time 7720033960 ps
CPU time 32.03 seconds
Started Mar 19 01:13:07 PM PDT 24
Finished Mar 19 01:13:39 PM PDT 24
Peak memory 215808 kb
Host smart-b502f87b-4f11-4224-8ca4-aad6c4882091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166388707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2166388707
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.65193984
Short name T919
Test name
Test status
Simulation time 504862436 ps
CPU time 1.74 seconds
Started Mar 19 01:13:05 PM PDT 24
Finished Mar 19 01:13:07 PM PDT 24
Peak memory 207456 kb
Host smart-fc3e1488-f1ce-4323-a209-ac1abd04d9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65193984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.65193984
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.4061380559
Short name T827
Test name
Test status
Simulation time 441000145 ps
CPU time 1.79 seconds
Started Mar 19 01:13:07 PM PDT 24
Finished Mar 19 01:13:09 PM PDT 24
Peak memory 215736 kb
Host smart-8761e2c1-4e60-496d-819b-54c5861f8a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061380559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.4061380559
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2159217586
Short name T871
Test name
Test status
Simulation time 307129279 ps
CPU time 0.87 seconds
Started Mar 19 01:13:05 PM PDT 24
Finished Mar 19 01:13:06 PM PDT 24
Peak memory 205296 kb
Host smart-da64f949-0d35-4531-b5f4-e4ef14047d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159217586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2159217586
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1946379203
Short name T527
Test name
Test status
Simulation time 1869928859 ps
CPU time 7.57 seconds
Started Mar 19 01:13:05 PM PDT 24
Finished Mar 19 01:13:13 PM PDT 24
Peak memory 219272 kb
Host smart-1e6eb5ba-db38-4e18-a012-1e0a795a8ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946379203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1946379203
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.926446713
Short name T958
Test name
Test status
Simulation time 42592467 ps
CPU time 0.69 seconds
Started Mar 19 01:16:31 PM PDT 24
Finished Mar 19 01:16:32 PM PDT 24
Peak memory 204900 kb
Host smart-e7aadcca-c6e5-4294-b275-2cb8de39c21a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926446713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.926446713
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.881626299
Short name T796
Test name
Test status
Simulation time 260180603 ps
CPU time 2.45 seconds
Started Mar 19 01:16:28 PM PDT 24
Finished Mar 19 01:16:31 PM PDT 24
Peak memory 218376 kb
Host smart-a938962a-4838-4a34-a4da-314bd862cd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881626299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.881626299
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1891582685
Short name T4
Test name
Test status
Simulation time 25825186 ps
CPU time 0.77 seconds
Started Mar 19 01:16:19 PM PDT 24
Finished Mar 19 01:16:20 PM PDT 24
Peak memory 206036 kb
Host smart-85da6d6f-19b3-4bbf-8631-ff6e6fe6fc93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891582685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1891582685
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3957710885
Short name T164
Test name
Test status
Simulation time 39627089950 ps
CPU time 57.44 seconds
Started Mar 19 01:16:26 PM PDT 24
Finished Mar 19 01:17:24 PM PDT 24
Peak memory 232312 kb
Host smart-929ea817-43f5-4905-bd6b-40ca3d196f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957710885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3957710885
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2056334516
Short name T720
Test name
Test status
Simulation time 44929870731 ps
CPU time 204.03 seconds
Started Mar 19 01:16:27 PM PDT 24
Finished Mar 19 01:19:52 PM PDT 24
Peak memory 248792 kb
Host smart-cfd25b0c-d76f-45bd-9654-887b037dc4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056334516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2056334516
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3888114842
Short name T197
Test name
Test status
Simulation time 129598006370 ps
CPU time 182.89 seconds
Started Mar 19 01:16:34 PM PDT 24
Finished Mar 19 01:19:37 PM PDT 24
Peak memory 265172 kb
Host smart-ad86d3ac-befa-46f0-842c-82c1a8624716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888114842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3888114842
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2967965877
Short name T415
Test name
Test status
Simulation time 53168742844 ps
CPU time 42.52 seconds
Started Mar 19 01:16:26 PM PDT 24
Finished Mar 19 01:17:09 PM PDT 24
Peak memory 240332 kb
Host smart-21089fcd-7200-447a-9953-55aab26f2ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967965877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2967965877
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2086516425
Short name T354
Test name
Test status
Simulation time 911893584 ps
CPU time 5.14 seconds
Started Mar 19 01:16:19 PM PDT 24
Finished Mar 19 01:16:24 PM PDT 24
Peak memory 233420 kb
Host smart-0bdc5849-f316-483b-a71f-01b04dae0663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086516425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2086516425
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.694208441
Short name T800
Test name
Test status
Simulation time 623637267 ps
CPU time 9.39 seconds
Started Mar 19 01:16:23 PM PDT 24
Finished Mar 19 01:16:32 PM PDT 24
Peak memory 233012 kb
Host smart-036b2127-9742-4899-b502-85732c2e181c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694208441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.694208441
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1479244267
Short name T455
Test name
Test status
Simulation time 7206247092 ps
CPU time 8.12 seconds
Started Mar 19 01:16:19 PM PDT 24
Finished Mar 19 01:16:28 PM PDT 24
Peak memory 233744 kb
Host smart-00753617-3333-4c0d-bdec-9ac8b9f6fd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479244267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1479244267
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.4037121322
Short name T760
Test name
Test status
Simulation time 1744058351 ps
CPU time 5.95 seconds
Started Mar 19 01:16:21 PM PDT 24
Finished Mar 19 01:16:27 PM PDT 24
Peak memory 232668 kb
Host smart-998d8d9a-2006-4a1e-a867-e7e8e1ae14bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037121322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.4037121322
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.4019361696
Short name T905
Test name
Test status
Simulation time 6404456153 ps
CPU time 6.96 seconds
Started Mar 19 01:16:27 PM PDT 24
Finished Mar 19 01:16:34 PM PDT 24
Peak memory 222096 kb
Host smart-889c9e7b-732a-4528-a5be-d542dc498698
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4019361696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.4019361696
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3504903368
Short name T799
Test name
Test status
Simulation time 56048717 ps
CPU time 1.12 seconds
Started Mar 19 01:16:32 PM PDT 24
Finished Mar 19 01:16:34 PM PDT 24
Peak memory 206296 kb
Host smart-13ebeaac-7e45-4d22-b79a-50405a22bfe2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504903368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3504903368
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3608774882
Short name T439
Test name
Test status
Simulation time 33609426448 ps
CPU time 53.84 seconds
Started Mar 19 01:16:26 PM PDT 24
Finished Mar 19 01:17:20 PM PDT 24
Peak memory 215856 kb
Host smart-685c6856-3c3a-48f0-886d-b06b77c3e363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608774882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3608774882
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1074238827
Short name T794
Test name
Test status
Simulation time 9459021869 ps
CPU time 29.21 seconds
Started Mar 19 01:16:21 PM PDT 24
Finished Mar 19 01:16:50 PM PDT 24
Peak memory 215792 kb
Host smart-64ae8e3a-878c-4b5e-932e-16fd52f6d812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074238827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1074238827
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.3084896874
Short name T54
Test name
Test status
Simulation time 260892238 ps
CPU time 1.84 seconds
Started Mar 19 01:16:18 PM PDT 24
Finished Mar 19 01:16:20 PM PDT 24
Peak memory 215768 kb
Host smart-f57d7159-b596-4a88-9448-85716bf52964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084896874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3084896874
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.868261689
Short name T78
Test name
Test status
Simulation time 129182272 ps
CPU time 0.77 seconds
Started Mar 19 01:16:23 PM PDT 24
Finished Mar 19 01:16:23 PM PDT 24
Peak memory 205276 kb
Host smart-191a04f5-1fac-42cf-b0e5-05e0ea96d0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868261689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.868261689
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3856158605
Short name T29
Test name
Test status
Simulation time 962628198 ps
CPU time 7.8 seconds
Started Mar 19 01:16:27 PM PDT 24
Finished Mar 19 01:16:35 PM PDT 24
Peak memory 227752 kb
Host smart-06761833-38bb-4c83-b307-3d09b40ea0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856158605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3856158605
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.759121503
Short name T837
Test name
Test status
Simulation time 13199650 ps
CPU time 0.76 seconds
Started Mar 19 01:16:43 PM PDT 24
Finished Mar 19 01:16:44 PM PDT 24
Peak memory 204832 kb
Host smart-bf663252-0a6b-41e9-96a0-cda94d8eb98e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759121503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.759121503
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1139616722
Short name T893
Test name
Test status
Simulation time 154258752 ps
CPU time 2.42 seconds
Started Mar 19 01:16:33 PM PDT 24
Finished Mar 19 01:16:35 PM PDT 24
Peak memory 218088 kb
Host smart-9e44629e-42c5-4060-a732-213eb2367ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139616722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1139616722
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.984468746
Short name T295
Test name
Test status
Simulation time 16430493 ps
CPU time 0.74 seconds
Started Mar 19 01:16:33 PM PDT 24
Finished Mar 19 01:16:33 PM PDT 24
Peak memory 205708 kb
Host smart-36777bb4-362a-4e8a-ad34-40b3d5ed9301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984468746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.984468746
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.4149448403
Short name T233
Test name
Test status
Simulation time 10882636961 ps
CPU time 107.67 seconds
Started Mar 19 01:16:36 PM PDT 24
Finished Mar 19 01:18:23 PM PDT 24
Peak memory 262824 kb
Host smart-131ffa76-6531-42c8-92ac-ccced955163a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149448403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.4149448403
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.624977678
Short name T225
Test name
Test status
Simulation time 4718344417 ps
CPU time 113.05 seconds
Started Mar 19 01:16:39 PM PDT 24
Finished Mar 19 01:18:33 PM PDT 24
Peak memory 263616 kb
Host smart-1328e13f-ea4b-474b-8b78-43e42dc47c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624977678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.624977678
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.594182395
Short name T265
Test name
Test status
Simulation time 1035679305 ps
CPU time 17.32 seconds
Started Mar 19 01:16:31 PM PDT 24
Finished Mar 19 01:16:48 PM PDT 24
Peak memory 227836 kb
Host smart-2f73cb1b-c617-4a9a-bad5-46306f0416c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594182395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.594182395
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2356345229
Short name T773
Test name
Test status
Simulation time 307279622 ps
CPU time 3.22 seconds
Started Mar 19 01:16:32 PM PDT 24
Finished Mar 19 01:16:35 PM PDT 24
Peak memory 234244 kb
Host smart-71bc83f3-7927-47e5-b603-e0e866f72967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356345229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2356345229
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1347089602
Short name T675
Test name
Test status
Simulation time 4082792601 ps
CPU time 16.31 seconds
Started Mar 19 01:16:31 PM PDT 24
Finished Mar 19 01:16:47 PM PDT 24
Peak memory 237188 kb
Host smart-49e5fc2b-d2dd-4246-88e6-559f9cdd5a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347089602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1347089602
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1724238237
Short name T57
Test name
Test status
Simulation time 247146666 ps
CPU time 2.9 seconds
Started Mar 19 01:16:33 PM PDT 24
Finished Mar 19 01:16:36 PM PDT 24
Peak memory 232184 kb
Host smart-66fa1706-4142-42f5-b118-2915409983de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724238237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1724238237
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3720112671
Short name T635
Test name
Test status
Simulation time 2052077909 ps
CPU time 3.46 seconds
Started Mar 19 01:16:32 PM PDT 24
Finished Mar 19 01:16:36 PM PDT 24
Peak memory 217968 kb
Host smart-caeeecb5-3f81-4996-8549-2615cd46339f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720112671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3720112671
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3205935541
Short name T731
Test name
Test status
Simulation time 816610792 ps
CPU time 5.21 seconds
Started Mar 19 01:16:34 PM PDT 24
Finished Mar 19 01:16:40 PM PDT 24
Peak memory 221964 kb
Host smart-085d93fd-8b99-4fb3-9137-3dd4d2059d87
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3205935541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3205935541
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2810101568
Short name T828
Test name
Test status
Simulation time 55103101 ps
CPU time 0.95 seconds
Started Mar 19 01:16:42 PM PDT 24
Finished Mar 19 01:16:43 PM PDT 24
Peak memory 206180 kb
Host smart-e135045e-e506-43f6-989a-5980f10adac0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810101568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2810101568
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3710612726
Short name T450
Test name
Test status
Simulation time 10317367990 ps
CPU time 60.06 seconds
Started Mar 19 01:16:33 PM PDT 24
Finished Mar 19 01:17:33 PM PDT 24
Peak memory 215868 kb
Host smart-b5108b17-af2a-4653-8dcd-afcf62242c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710612726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3710612726
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1940059477
Short name T395
Test name
Test status
Simulation time 76995269899 ps
CPU time 23.03 seconds
Started Mar 19 01:16:32 PM PDT 24
Finished Mar 19 01:16:56 PM PDT 24
Peak memory 215832 kb
Host smart-dd4eacae-827c-4d21-abee-e22734627934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940059477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1940059477
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.293172620
Short name T345
Test name
Test status
Simulation time 350542323 ps
CPU time 1.62 seconds
Started Mar 19 01:16:33 PM PDT 24
Finished Mar 19 01:16:34 PM PDT 24
Peak memory 215460 kb
Host smart-3aaa87ec-e4e2-4536-a458-36dc8bad674c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293172620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.293172620
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1717629871
Short name T559
Test name
Test status
Simulation time 315326162 ps
CPU time 0.99 seconds
Started Mar 19 01:16:31 PM PDT 24
Finished Mar 19 01:16:32 PM PDT 24
Peak memory 205864 kb
Host smart-46d326e4-14b5-40b0-8e22-9a2e81148645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717629871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1717629871
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3513125336
Short name T443
Test name
Test status
Simulation time 275268156 ps
CPU time 2.78 seconds
Started Mar 19 01:16:32 PM PDT 24
Finished Mar 19 01:16:35 PM PDT 24
Peak memory 216904 kb
Host smart-323b1b34-a2c9-4846-a505-4e96176e3365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513125336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3513125336
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1233248071
Short name T697
Test name
Test status
Simulation time 22042521 ps
CPU time 0.69 seconds
Started Mar 19 01:16:46 PM PDT 24
Finished Mar 19 01:16:46 PM PDT 24
Peak memory 205212 kb
Host smart-a414550c-9be8-49d8-9fe5-dbb2d803bd44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233248071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1233248071
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.636172740
Short name T360
Test name
Test status
Simulation time 455043362 ps
CPU time 3.43 seconds
Started Mar 19 01:16:41 PM PDT 24
Finished Mar 19 01:16:45 PM PDT 24
Peak memory 233328 kb
Host smart-fd70a88c-4419-4bd8-a8bf-ca7ed2215306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636172740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.636172740
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3950777674
Short name T854
Test name
Test status
Simulation time 14210197 ps
CPU time 0.75 seconds
Started Mar 19 01:16:41 PM PDT 24
Finished Mar 19 01:16:42 PM PDT 24
Peak memory 205320 kb
Host smart-d010d807-074f-41f7-9073-247987e3b2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950777674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3950777674
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2966908380
Short name T201
Test name
Test status
Simulation time 69398530139 ps
CPU time 258.02 seconds
Started Mar 19 01:16:47 PM PDT 24
Finished Mar 19 01:21:05 PM PDT 24
Peak memory 264600 kb
Host smart-5a3b77aa-556c-48bf-a0f0-51364ceccaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966908380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2966908380
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2935589453
Short name T904
Test name
Test status
Simulation time 72828274254 ps
CPU time 564.18 seconds
Started Mar 19 01:16:49 PM PDT 24
Finished Mar 19 01:26:14 PM PDT 24
Peak memory 250408 kb
Host smart-853b0c63-65b4-42aa-9cef-67e13366a3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935589453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2935589453
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2470834295
Short name T775
Test name
Test status
Simulation time 15104626136 ps
CPU time 37.93 seconds
Started Mar 19 01:16:41 PM PDT 24
Finished Mar 19 01:17:19 PM PDT 24
Peak memory 236944 kb
Host smart-c6b98f63-715f-42a5-8504-fdf2023a87fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470834295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2470834295
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1495895503
Short name T521
Test name
Test status
Simulation time 3863662538 ps
CPU time 11.16 seconds
Started Mar 19 01:16:41 PM PDT 24
Finished Mar 19 01:16:53 PM PDT 24
Peak memory 233352 kb
Host smart-3f2e883b-3509-4692-8af7-c897731716ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495895503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1495895503
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.367739015
Short name T468
Test name
Test status
Simulation time 9072460735 ps
CPU time 31.34 seconds
Started Mar 19 01:16:39 PM PDT 24
Finished Mar 19 01:17:10 PM PDT 24
Peak memory 248560 kb
Host smart-11869b92-d292-4f4a-a096-c33ed1265988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367739015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.367739015
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.721815383
Short name T687
Test name
Test status
Simulation time 517630746 ps
CPU time 4.38 seconds
Started Mar 19 01:16:39 PM PDT 24
Finished Mar 19 01:16:43 PM PDT 24
Peak memory 232652 kb
Host smart-10cea248-80aa-4eca-8298-2bbb2209734c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721815383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.721815383
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.484755577
Short name T83
Test name
Test status
Simulation time 386481538 ps
CPU time 4.27 seconds
Started Mar 19 01:16:41 PM PDT 24
Finished Mar 19 01:16:46 PM PDT 24
Peak memory 232840 kb
Host smart-9c9343d8-535a-4d8e-9c82-18d07ceda9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484755577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.484755577
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2899309538
Short name T431
Test name
Test status
Simulation time 6441097443 ps
CPU time 4.94 seconds
Started Mar 19 01:16:41 PM PDT 24
Finished Mar 19 01:16:46 PM PDT 24
Peak memory 221952 kb
Host smart-f9f590c7-a273-4751-8ed7-86632a74ec92
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2899309538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2899309538
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1646576185
Short name T750
Test name
Test status
Simulation time 108627423 ps
CPU time 1.09 seconds
Started Mar 19 01:16:50 PM PDT 24
Finished Mar 19 01:16:51 PM PDT 24
Peak memory 206492 kb
Host smart-e227161d-470b-4aca-971c-f57e45ef9226
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646576185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1646576185
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1080445203
Short name T566
Test name
Test status
Simulation time 1827632845 ps
CPU time 4.77 seconds
Started Mar 19 01:16:41 PM PDT 24
Finished Mar 19 01:16:46 PM PDT 24
Peak memory 215988 kb
Host smart-9b62b59f-2c75-4cc6-9308-1c01ff37c222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080445203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1080445203
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1329925225
Short name T305
Test name
Test status
Simulation time 598847366 ps
CPU time 4.89 seconds
Started Mar 19 01:16:41 PM PDT 24
Finished Mar 19 01:16:46 PM PDT 24
Peak memory 215828 kb
Host smart-a46f1596-9fb3-4025-8189-8c3f77d3db03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329925225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1329925225
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3820673610
Short name T803
Test name
Test status
Simulation time 174437359 ps
CPU time 2.73 seconds
Started Mar 19 01:16:41 PM PDT 24
Finished Mar 19 01:16:44 PM PDT 24
Peak memory 215908 kb
Host smart-839eeb0a-971a-4712-942a-4adbbde1f8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820673610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3820673610
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3440077096
Short name T99
Test name
Test status
Simulation time 720227088 ps
CPU time 0.98 seconds
Started Mar 19 01:16:40 PM PDT 24
Finished Mar 19 01:16:41 PM PDT 24
Peak memory 206204 kb
Host smart-b0968d97-408e-42a4-ada6-4b47ba4f6193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440077096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3440077096
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2197291219
Short name T208
Test name
Test status
Simulation time 7560634444 ps
CPU time 23.36 seconds
Started Mar 19 01:16:43 PM PDT 24
Finished Mar 19 01:17:07 PM PDT 24
Peak memory 219052 kb
Host smart-b69d4d68-1254-40de-a9d5-4aee6c26c2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197291219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2197291219
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.4252803636
Short name T403
Test name
Test status
Simulation time 14698615 ps
CPU time 0.75 seconds
Started Mar 19 01:16:46 PM PDT 24
Finished Mar 19 01:16:47 PM PDT 24
Peak memory 204904 kb
Host smart-e931fc23-7727-4aff-8296-45aa8311504f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252803636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
4252803636
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.3181155159
Short name T879
Test name
Test status
Simulation time 1164271602 ps
CPU time 4 seconds
Started Mar 19 01:16:48 PM PDT 24
Finished Mar 19 01:16:52 PM PDT 24
Peak memory 218788 kb
Host smart-9db185cf-7829-4184-bfda-80893c1c5ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181155159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3181155159
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2054754377
Short name T59
Test name
Test status
Simulation time 17893141 ps
CPU time 0.77 seconds
Started Mar 19 01:16:46 PM PDT 24
Finished Mar 19 01:16:47 PM PDT 24
Peak memory 206316 kb
Host smart-9e38b1a4-ebd5-4fdb-9f30-02afaaabd972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054754377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2054754377
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1866209460
Short name T224
Test name
Test status
Simulation time 245561542719 ps
CPU time 135.16 seconds
Started Mar 19 01:16:45 PM PDT 24
Finished Mar 19 01:19:01 PM PDT 24
Peak memory 248648 kb
Host smart-5ae93428-0aef-47ae-a69a-b0656d944ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866209460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1866209460
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3329830272
Short name T574
Test name
Test status
Simulation time 11540404747 ps
CPU time 46.39 seconds
Started Mar 19 01:16:49 PM PDT 24
Finished Mar 19 01:17:36 PM PDT 24
Peak memory 240580 kb
Host smart-adcdf83c-bd39-47cb-a0e3-7c948185306f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329830272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3329830272
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3671605252
Short name T178
Test name
Test status
Simulation time 15027812380 ps
CPU time 127.29 seconds
Started Mar 19 01:16:46 PM PDT 24
Finished Mar 19 01:18:54 PM PDT 24
Peak memory 287992 kb
Host smart-6d756bd4-e0b3-4cb4-82bc-ea2dd284a749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671605252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.3671605252
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3970549521
Short name T257
Test name
Test status
Simulation time 3213963564 ps
CPU time 13.35 seconds
Started Mar 19 01:16:47 PM PDT 24
Finished Mar 19 01:17:01 PM PDT 24
Peak memory 232244 kb
Host smart-d7c28425-52a9-41d5-bd04-1802ade18438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970549521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3970549521
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.4000122841
Short name T35
Test name
Test status
Simulation time 9498863690 ps
CPU time 8.44 seconds
Started Mar 19 01:16:46 PM PDT 24
Finished Mar 19 01:16:55 PM PDT 24
Peak memory 219584 kb
Host smart-3cf7ce84-5e4f-4a32-baa3-269a561ae097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000122841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.4000122841
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.98767987
Short name T899
Test name
Test status
Simulation time 6421398569 ps
CPU time 23.07 seconds
Started Mar 19 01:16:48 PM PDT 24
Finished Mar 19 01:17:11 PM PDT 24
Peak memory 223608 kb
Host smart-34370ff3-fc8d-4d30-9fb8-157471b62ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98767987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.98767987
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1114600801
Short name T212
Test name
Test status
Simulation time 2633942410 ps
CPU time 16.22 seconds
Started Mar 19 01:16:48 PM PDT 24
Finished Mar 19 01:17:05 PM PDT 24
Peak memory 240192 kb
Host smart-153306d7-dffa-4e8f-b845-17e7bfeac9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114600801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1114600801
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1038955432
Short name T786
Test name
Test status
Simulation time 46080768852 ps
CPU time 32.59 seconds
Started Mar 19 01:16:50 PM PDT 24
Finished Mar 19 01:17:23 PM PDT 24
Peak memory 249572 kb
Host smart-a7003940-80f0-4036-a843-f70f06797c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038955432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1038955432
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.4218813090
Short name T514
Test name
Test status
Simulation time 148062336 ps
CPU time 3.48 seconds
Started Mar 19 01:16:46 PM PDT 24
Finished Mar 19 01:16:50 PM PDT 24
Peak memory 221916 kb
Host smart-8b95957b-d12e-42f9-95b4-455db20d6532
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4218813090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.4218813090
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.2103228337
Short name T218
Test name
Test status
Simulation time 238248576238 ps
CPU time 643.26 seconds
Started Mar 19 01:16:47 PM PDT 24
Finished Mar 19 01:27:31 PM PDT 24
Peak memory 273236 kb
Host smart-d5b81e7c-18a1-4b3e-8ac9-f897345c0adb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103228337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.2103228337
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.4027590611
Short name T409
Test name
Test status
Simulation time 12522454979 ps
CPU time 24.49 seconds
Started Mar 19 01:16:50 PM PDT 24
Finished Mar 19 01:17:15 PM PDT 24
Peak memory 215932 kb
Host smart-c6d850f4-1503-44cd-81da-4ec43ed73aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027590611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.4027590611
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1344703977
Short name T956
Test name
Test status
Simulation time 10536892053 ps
CPU time 6.7 seconds
Started Mar 19 01:16:49 PM PDT 24
Finished Mar 19 01:16:55 PM PDT 24
Peak memory 215808 kb
Host smart-9ef17e3f-e459-4696-a2e6-692bc453ed3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344703977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1344703977
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3982539001
Short name T390
Test name
Test status
Simulation time 178910423 ps
CPU time 1.13 seconds
Started Mar 19 01:16:47 PM PDT 24
Finished Mar 19 01:16:48 PM PDT 24
Peak memory 206364 kb
Host smart-be937ac9-1a17-471e-ade0-e672350912ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982539001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3982539001
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2219628332
Short name T526
Test name
Test status
Simulation time 56002070 ps
CPU time 0.72 seconds
Started Mar 19 01:16:50 PM PDT 24
Finished Mar 19 01:16:51 PM PDT 24
Peak memory 205324 kb
Host smart-08b5270b-20a8-4fe0-9168-c7de80140de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219628332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2219628332
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.833246201
Short name T343
Test name
Test status
Simulation time 4285311105 ps
CPU time 9.09 seconds
Started Mar 19 01:16:47 PM PDT 24
Finished Mar 19 01:16:56 PM PDT 24
Peak memory 219496 kb
Host smart-3f1ffab6-25a4-4ba4-a6d3-6d27e2d4c9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833246201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.833246201
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1968019815
Short name T358
Test name
Test status
Simulation time 39711799 ps
CPU time 0.72 seconds
Started Mar 19 01:17:02 PM PDT 24
Finished Mar 19 01:17:03 PM PDT 24
Peak memory 204224 kb
Host smart-aac701f7-4d9e-46a7-bfee-c2b35b3a27a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968019815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1968019815
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3162171801
Short name T200
Test name
Test status
Simulation time 673576511 ps
CPU time 4.3 seconds
Started Mar 19 01:16:55 PM PDT 24
Finished Mar 19 01:17:00 PM PDT 24
Peak memory 219436 kb
Host smart-635612f8-86f2-4097-bce8-88887b721c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162171801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3162171801
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3708027571
Short name T609
Test name
Test status
Simulation time 66526950 ps
CPU time 0.75 seconds
Started Mar 19 01:16:49 PM PDT 24
Finished Mar 19 01:16:50 PM PDT 24
Peak memory 205012 kb
Host smart-7df43350-80ef-41a0-b75b-11127bad1ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708027571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3708027571
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.496621939
Short name T601
Test name
Test status
Simulation time 86054118307 ps
CPU time 188.57 seconds
Started Mar 19 01:17:02 PM PDT 24
Finished Mar 19 01:20:11 PM PDT 24
Peak memory 264260 kb
Host smart-0f0f0767-fc87-4c8c-a39d-c1b0d57d231b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496621939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.496621939
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.795013643
Short name T464
Test name
Test status
Simulation time 146626147052 ps
CPU time 232.32 seconds
Started Mar 19 01:17:01 PM PDT 24
Finished Mar 19 01:20:53 PM PDT 24
Peak memory 249260 kb
Host smart-cc26b7f4-9c59-428f-8106-6aa045c2cb2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795013643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.795013643
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2259451321
Short name T56
Test name
Test status
Simulation time 27234099712 ps
CPU time 131.84 seconds
Started Mar 19 01:17:02 PM PDT 24
Finished Mar 19 01:19:15 PM PDT 24
Peak memory 254952 kb
Host smart-fbf27e72-232a-4529-b115-59bae80c6441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259451321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2259451321
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.4083673007
Short name T407
Test name
Test status
Simulation time 22070540843 ps
CPU time 21.84 seconds
Started Mar 19 01:16:58 PM PDT 24
Finished Mar 19 01:17:20 PM PDT 24
Peak memory 224140 kb
Host smart-f902260a-6b94-4a4c-b2f8-44c0a3b416df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083673007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.4083673007
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2740841257
Short name T757
Test name
Test status
Simulation time 8231043251 ps
CPU time 10.12 seconds
Started Mar 19 01:16:54 PM PDT 24
Finished Mar 19 01:17:05 PM PDT 24
Peak memory 235400 kb
Host smart-4fca06cc-0c1e-469e-8093-6299201a2f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740841257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2740841257
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.4091136627
Short name T845
Test name
Test status
Simulation time 5591175582 ps
CPU time 21.4 seconds
Started Mar 19 01:16:57 PM PDT 24
Finished Mar 19 01:17:19 PM PDT 24
Peak memory 229692 kb
Host smart-363b16ca-1076-4b22-8388-4aecc0a9cb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091136627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.4091136627
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.4099391195
Short name T373
Test name
Test status
Simulation time 28720928265 ps
CPU time 20.25 seconds
Started Mar 19 01:16:57 PM PDT 24
Finished Mar 19 01:17:17 PM PDT 24
Peak memory 224080 kb
Host smart-0684661a-e0b0-4cb3-96ee-b9dded9e7029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099391195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.4099391195
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3202448649
Short name T392
Test name
Test status
Simulation time 9851875942 ps
CPU time 26.01 seconds
Started Mar 19 01:16:57 PM PDT 24
Finished Mar 19 01:17:23 PM PDT 24
Peak memory 232872 kb
Host smart-8da95768-df64-4ab6-a6dd-9f4f1d5084c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202448649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3202448649
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3620586192
Short name T453
Test name
Test status
Simulation time 405976490 ps
CPU time 3.81 seconds
Started Mar 19 01:16:55 PM PDT 24
Finished Mar 19 01:16:58 PM PDT 24
Peak memory 221696 kb
Host smart-f9fbf0ca-cee7-4a2b-b845-e80a0e1f6824
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3620586192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3620586192
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.4028406146
Short name T156
Test name
Test status
Simulation time 9689719674 ps
CPU time 93.76 seconds
Started Mar 19 01:17:03 PM PDT 24
Finished Mar 19 01:18:37 PM PDT 24
Peak memory 253480 kb
Host smart-c1642853-248f-44af-9b61-313e683594af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028406146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.4028406146
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2355032425
Short name T833
Test name
Test status
Simulation time 836381868 ps
CPU time 5.54 seconds
Started Mar 19 01:16:47 PM PDT 24
Finished Mar 19 01:16:53 PM PDT 24
Peak memory 215816 kb
Host smart-66313db0-a32d-4844-91d0-af6063f5b46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355032425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2355032425
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.4215412868
Short name T296
Test name
Test status
Simulation time 1091402969 ps
CPU time 5 seconds
Started Mar 19 01:16:47 PM PDT 24
Finished Mar 19 01:16:52 PM PDT 24
Peak memory 215776 kb
Host smart-dbdb9ede-00cd-49de-be5c-336096259938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215412868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.4215412868
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.792393593
Short name T309
Test name
Test status
Simulation time 74664661 ps
CPU time 1.2 seconds
Started Mar 19 01:16:57 PM PDT 24
Finished Mar 19 01:16:59 PM PDT 24
Peak memory 207112 kb
Host smart-ffe2589b-5667-47f9-ac4a-73c2f4bb8ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792393593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.792393593
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2747228104
Short name T704
Test name
Test status
Simulation time 60341094 ps
CPU time 0.72 seconds
Started Mar 19 01:16:50 PM PDT 24
Finished Mar 19 01:16:51 PM PDT 24
Peak memory 205300 kb
Host smart-b224ccf1-dfbb-4b7c-a7e4-c62511fbdde8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747228104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2747228104
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.297781719
Short name T849
Test name
Test status
Simulation time 28700963929 ps
CPU time 47.14 seconds
Started Mar 19 01:16:58 PM PDT 24
Finished Mar 19 01:17:45 PM PDT 24
Peak memory 239960 kb
Host smart-39627cda-202a-4a3f-b3fe-117793909d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297781719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.297781719
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1878347695
Short name T804
Test name
Test status
Simulation time 11404395 ps
CPU time 0.72 seconds
Started Mar 19 01:17:01 PM PDT 24
Finished Mar 19 01:17:02 PM PDT 24
Peak memory 204880 kb
Host smart-f18c2c32-e1a5-43bf-a155-659efcba063f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878347695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1878347695
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.4143895565
Short name T909
Test name
Test status
Simulation time 446147716 ps
CPU time 5.17 seconds
Started Mar 19 01:17:02 PM PDT 24
Finished Mar 19 01:17:08 PM PDT 24
Peak memory 221356 kb
Host smart-bdcc341b-6b60-4ad5-b9bf-c28793b873d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143895565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.4143895565
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.131623113
Short name T936
Test name
Test status
Simulation time 36516821 ps
CPU time 0.82 seconds
Started Mar 19 01:17:03 PM PDT 24
Finished Mar 19 01:17:04 PM PDT 24
Peak memory 206044 kb
Host smart-7b7a81db-df59-4399-bf19-bc117e25a136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131623113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.131623113
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.2990749839
Short name T698
Test name
Test status
Simulation time 9017828853 ps
CPU time 28.08 seconds
Started Mar 19 01:17:03 PM PDT 24
Finished Mar 19 01:17:31 PM PDT 24
Peak memory 248264 kb
Host smart-e9311de4-2360-41a3-901d-36721c6f2e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990749839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2990749839
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2202107493
Short name T13
Test name
Test status
Simulation time 58444024193 ps
CPU time 106.97 seconds
Started Mar 19 01:17:03 PM PDT 24
Finished Mar 19 01:18:50 PM PDT 24
Peak memory 236484 kb
Host smart-07901d41-e3a8-4b6f-a564-27fef6e9f194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202107493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2202107493
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3655873533
Short name T25
Test name
Test status
Simulation time 4577227435 ps
CPU time 54.95 seconds
Started Mar 19 01:17:02 PM PDT 24
Finished Mar 19 01:17:57 PM PDT 24
Peak memory 248680 kb
Host smart-1616f86c-c389-4254-b8b0-a74ead1c9401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655873533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.3655873533
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.905834525
Short name T966
Test name
Test status
Simulation time 12818399612 ps
CPU time 16.36 seconds
Started Mar 19 01:17:02 PM PDT 24
Finished Mar 19 01:17:18 PM PDT 24
Peak memory 234840 kb
Host smart-afed84f7-b23a-4516-806a-db2a59e167d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905834525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.905834525
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.278648926
Short name T203
Test name
Test status
Simulation time 832955246 ps
CPU time 3.22 seconds
Started Mar 19 01:17:03 PM PDT 24
Finished Mar 19 01:17:07 PM PDT 24
Peak memory 233788 kb
Host smart-ad77a799-47da-47a0-8f3b-3af69418688b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278648926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.278648926
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.943551990
Short name T585
Test name
Test status
Simulation time 32138151992 ps
CPU time 25.31 seconds
Started Mar 19 01:17:06 PM PDT 24
Finished Mar 19 01:17:32 PM PDT 24
Peak memory 235888 kb
Host smart-f26f615a-37d6-4d02-9e41-e04057dea1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943551990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.943551990
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3398317732
Short name T780
Test name
Test status
Simulation time 700325588 ps
CPU time 7.6 seconds
Started Mar 19 01:17:05 PM PDT 24
Finished Mar 19 01:17:13 PM PDT 24
Peak memory 232676 kb
Host smart-d9dd1100-2e0d-44bb-b285-5b114dd017bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398317732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3398317732
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2407701762
Short name T183
Test name
Test status
Simulation time 117448101648 ps
CPU time 25.58 seconds
Started Mar 19 01:17:02 PM PDT 24
Finished Mar 19 01:17:28 PM PDT 24
Peak memory 216560 kb
Host smart-d72af1b8-432b-4e1a-8221-3ccc6fde6521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407701762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2407701762
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2488767796
Short name T683
Test name
Test status
Simulation time 1157954496 ps
CPU time 5.16 seconds
Started Mar 19 01:17:02 PM PDT 24
Finished Mar 19 01:17:07 PM PDT 24
Peak memory 218892 kb
Host smart-9defd1e8-b234-4a0e-8cc4-4ba99cde3cde
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2488767796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2488767796
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.322003141
Short name T884
Test name
Test status
Simulation time 256995933817 ps
CPU time 463.72 seconds
Started Mar 19 01:17:04 PM PDT 24
Finished Mar 19 01:24:48 PM PDT 24
Peak memory 281512 kb
Host smart-435e80ce-8f68-4ff2-8137-0536384c980e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322003141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.322003141
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2448792298
Short name T467
Test name
Test status
Simulation time 625987009 ps
CPU time 6.12 seconds
Started Mar 19 01:17:07 PM PDT 24
Finished Mar 19 01:17:13 PM PDT 24
Peak memory 215752 kb
Host smart-e1cf3cc6-4575-4958-a2d5-397f0f266754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448792298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2448792298
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1893052696
Short name T616
Test name
Test status
Simulation time 14067375033 ps
CPU time 13.13 seconds
Started Mar 19 01:17:04 PM PDT 24
Finished Mar 19 01:17:17 PM PDT 24
Peak memory 215784 kb
Host smart-00bad161-933b-4229-8153-7c4721b23105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893052696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1893052696
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1846748196
Short name T642
Test name
Test status
Simulation time 70032870 ps
CPU time 1.99 seconds
Started Mar 19 01:17:04 PM PDT 24
Finished Mar 19 01:17:06 PM PDT 24
Peak memory 215848 kb
Host smart-85e512c0-3ff2-4089-9cd6-89ea99337c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846748196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1846748196
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2094825757
Short name T856
Test name
Test status
Simulation time 211772358 ps
CPU time 0.88 seconds
Started Mar 19 01:17:05 PM PDT 24
Finished Mar 19 01:17:06 PM PDT 24
Peak memory 205312 kb
Host smart-aa01976b-de07-4d47-b33a-56752cd6e24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094825757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2094825757
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3027508279
Short name T680
Test name
Test status
Simulation time 19483089886 ps
CPU time 21.59 seconds
Started Mar 19 01:17:05 PM PDT 24
Finished Mar 19 01:17:26 PM PDT 24
Peak memory 232388 kb
Host smart-f53f8b53-c4af-4131-af9d-9189fe0820e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027508279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3027508279
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2391885614
Short name T483
Test name
Test status
Simulation time 37011419 ps
CPU time 0.77 seconds
Started Mar 19 01:17:13 PM PDT 24
Finished Mar 19 01:17:14 PM PDT 24
Peak memory 204292 kb
Host smart-67bce04c-14ea-4d30-979e-dc7bcbe83dab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391885614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2391885614
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1286935080
Short name T406
Test name
Test status
Simulation time 275769927 ps
CPU time 2.25 seconds
Started Mar 19 01:17:10 PM PDT 24
Finished Mar 19 01:17:13 PM PDT 24
Peak memory 224076 kb
Host smart-07ca8428-21d7-442d-a7fd-05f77748f999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286935080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1286935080
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2003555297
Short name T842
Test name
Test status
Simulation time 38732368 ps
CPU time 0.83 seconds
Started Mar 19 01:17:03 PM PDT 24
Finished Mar 19 01:17:05 PM PDT 24
Peak memory 206328 kb
Host smart-4e93a463-3016-427a-b8c6-def422fba0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003555297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2003555297
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3740463814
Short name T239
Test name
Test status
Simulation time 42401774522 ps
CPU time 85.57 seconds
Started Mar 19 01:17:10 PM PDT 24
Finished Mar 19 01:18:36 PM PDT 24
Peak memory 239800 kb
Host smart-99421efb-8adc-404d-a089-e01314108a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740463814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3740463814
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1367987131
Short name T668
Test name
Test status
Simulation time 4190048065 ps
CPU time 96.44 seconds
Started Mar 19 01:17:11 PM PDT 24
Finished Mar 19 01:18:48 PM PDT 24
Peak memory 261948 kb
Host smart-ed5c9c31-20e6-43e1-86f5-f6e58e97db54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367987131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1367987131
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.4044920723
Short name T266
Test name
Test status
Simulation time 11221159806 ps
CPU time 30.03 seconds
Started Mar 19 01:17:10 PM PDT 24
Finished Mar 19 01:17:40 PM PDT 24
Peak memory 238148 kb
Host smart-c59a7262-eac9-4150-9c40-9f47a5fd0308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044920723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.4044920723
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1509588119
Short name T744
Test name
Test status
Simulation time 2285286265 ps
CPU time 5.51 seconds
Started Mar 19 01:17:09 PM PDT 24
Finished Mar 19 01:17:15 PM PDT 24
Peak memory 218016 kb
Host smart-447e0f67-a861-4acf-b1e0-e3abd95a3372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509588119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1509588119
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.4178180758
Short name T947
Test name
Test status
Simulation time 7276790604 ps
CPU time 14.23 seconds
Started Mar 19 01:17:11 PM PDT 24
Finished Mar 19 01:17:26 PM PDT 24
Peak memory 233508 kb
Host smart-b2182717-41bc-4a62-986c-9321e67d98eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178180758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.4178180758
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1446166518
Short name T327
Test name
Test status
Simulation time 26259042882 ps
CPU time 20.81 seconds
Started Mar 19 01:17:11 PM PDT 24
Finished Mar 19 01:17:32 PM PDT 24
Peak memory 238396 kb
Host smart-441e6c4e-dead-4924-b652-d9aef5f982cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446166518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1446166518
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2348130538
Short name T329
Test name
Test status
Simulation time 832959985 ps
CPU time 3.99 seconds
Started Mar 19 01:17:11 PM PDT 24
Finished Mar 19 01:17:15 PM PDT 24
Peak memory 221856 kb
Host smart-47b7988a-568d-4ab5-b09a-8f3881779e44
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2348130538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2348130538
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.3240288451
Short name T160
Test name
Test status
Simulation time 60478050760 ps
CPU time 118.68 seconds
Started Mar 19 01:17:11 PM PDT 24
Finished Mar 19 01:19:09 PM PDT 24
Peak memory 232372 kb
Host smart-a5633884-8c93-4cfc-b4bc-9817b71bae65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240288451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.3240288451
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2208693898
Short name T741
Test name
Test status
Simulation time 499317245 ps
CPU time 7.37 seconds
Started Mar 19 01:17:10 PM PDT 24
Finished Mar 19 01:17:18 PM PDT 24
Peak memory 215804 kb
Host smart-33c0a8ea-f83a-45db-8826-dc0a9f947618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208693898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2208693898
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.423477432
Short name T336
Test name
Test status
Simulation time 23751734713 ps
CPU time 19.19 seconds
Started Mar 19 01:17:04 PM PDT 24
Finished Mar 19 01:17:23 PM PDT 24
Peak memory 215832 kb
Host smart-ed5b48a1-1adc-455b-a7e0-de215c113b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423477432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.423477432
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1707389072
Short name T537
Test name
Test status
Simulation time 77283442 ps
CPU time 0.96 seconds
Started Mar 19 01:17:10 PM PDT 24
Finished Mar 19 01:17:11 PM PDT 24
Peak memory 206312 kb
Host smart-1f6375bb-9ea1-4712-a849-aba48cbb4480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707389072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1707389072
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.846542397
Short name T920
Test name
Test status
Simulation time 174575978 ps
CPU time 0.83 seconds
Started Mar 19 01:17:11 PM PDT 24
Finished Mar 19 01:17:12 PM PDT 24
Peak memory 205320 kb
Host smart-e23944ca-e205-4ec5-98ae-d0af6e5175c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846542397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.846542397
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.707527112
Short name T648
Test name
Test status
Simulation time 6185232080 ps
CPU time 11.77 seconds
Started Mar 19 01:17:13 PM PDT 24
Finished Mar 19 01:17:25 PM PDT 24
Peak memory 218348 kb
Host smart-2beb0d13-444a-4968-9912-2375a40202f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707527112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.707527112
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3602645443
Short name T941
Test name
Test status
Simulation time 16253777 ps
CPU time 0.72 seconds
Started Mar 19 01:17:24 PM PDT 24
Finished Mar 19 01:17:25 PM PDT 24
Peak memory 204872 kb
Host smart-a6229a37-3a4d-4785-b438-79b5d6887f2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602645443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3602645443
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1776487639
Short name T516
Test name
Test status
Simulation time 8741482953 ps
CPU time 8.56 seconds
Started Mar 19 01:17:27 PM PDT 24
Finished Mar 19 01:17:36 PM PDT 24
Peak memory 233528 kb
Host smart-25e1d3ec-73f7-4983-be76-8b372ba88045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776487639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1776487639
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.249093891
Short name T333
Test name
Test status
Simulation time 23726456 ps
CPU time 0.76 seconds
Started Mar 19 01:17:10 PM PDT 24
Finished Mar 19 01:17:11 PM PDT 24
Peak memory 204968 kb
Host smart-e18ed0ce-31ff-4391-af87-cc108a0a06aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249093891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.249093891
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3990844659
Short name T384
Test name
Test status
Simulation time 1362409149 ps
CPU time 14.74 seconds
Started Mar 19 01:17:22 PM PDT 24
Finished Mar 19 01:17:37 PM PDT 24
Peak memory 240336 kb
Host smart-2e7c64fb-fd4e-4fc5-8868-d076cde04f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990844659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3990844659
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.434482842
Short name T251
Test name
Test status
Simulation time 770860832 ps
CPU time 3.71 seconds
Started Mar 19 01:17:23 PM PDT 24
Finished Mar 19 01:17:27 PM PDT 24
Peak memory 223908 kb
Host smart-60489d7d-905d-4515-85a1-3203e467e141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434482842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.434482842
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.717296676
Short name T264
Test name
Test status
Simulation time 47927240811 ps
CPU time 20.52 seconds
Started Mar 19 01:17:23 PM PDT 24
Finished Mar 19 01:17:44 PM PDT 24
Peak memory 228004 kb
Host smart-a2dcada6-0721-46fa-9904-97271c03abb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717296676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.717296676
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.647122626
Short name T870
Test name
Test status
Simulation time 3195770982 ps
CPU time 4.69 seconds
Started Mar 19 01:17:26 PM PDT 24
Finished Mar 19 01:17:31 PM PDT 24
Peak memory 232276 kb
Host smart-612e40a7-4e9c-467c-9c1d-0548f5ceeab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647122626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.647122626
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.4098206187
Short name T836
Test name
Test status
Simulation time 217451698345 ps
CPU time 61.78 seconds
Started Mar 19 01:17:23 PM PDT 24
Finished Mar 19 01:18:25 PM PDT 24
Peak memory 229508 kb
Host smart-98aa91c2-7c4d-49b9-a20c-2655e2e62aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098206187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.4098206187
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.999559278
Short name T37
Test name
Test status
Simulation time 19498555349 ps
CPU time 5.47 seconds
Started Mar 19 01:17:24 PM PDT 24
Finished Mar 19 01:17:30 PM PDT 24
Peak memory 218040 kb
Host smart-5509ac29-0d62-4907-8460-0d331dea77ff
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=999559278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.999559278
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.4146497026
Short name T922
Test name
Test status
Simulation time 26519004398 ps
CPU time 41.63 seconds
Started Mar 19 01:17:23 PM PDT 24
Finished Mar 19 01:18:05 PM PDT 24
Peak memory 215784 kb
Host smart-c7597d58-3216-4f89-b625-6eb1fd2bd857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146497026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.4146497026
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.4236494177
Short name T888
Test name
Test status
Simulation time 1390660865 ps
CPU time 3.9 seconds
Started Mar 19 01:17:24 PM PDT 24
Finished Mar 19 01:17:28 PM PDT 24
Peak memory 215784 kb
Host smart-d5504d58-2e4b-41f3-91fe-0bd4c7a1818f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236494177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.4236494177
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.10379724
Short name T577
Test name
Test status
Simulation time 57659113 ps
CPU time 0.94 seconds
Started Mar 19 01:17:23 PM PDT 24
Finished Mar 19 01:17:24 PM PDT 24
Peak memory 207404 kb
Host smart-3b6ffca1-8059-468c-aece-dfc7260146f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10379724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.10379724
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.4032844647
Short name T897
Test name
Test status
Simulation time 125515697 ps
CPU time 0.85 seconds
Started Mar 19 01:17:23 PM PDT 24
Finished Mar 19 01:17:24 PM PDT 24
Peak memory 205284 kb
Host smart-d49da19d-1db9-4b67-858c-4bb29c20dbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032844647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.4032844647
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1388233643
Short name T900
Test name
Test status
Simulation time 1358397753 ps
CPU time 6.34 seconds
Started Mar 19 01:17:25 PM PDT 24
Finished Mar 19 01:17:32 PM PDT 24
Peak memory 233816 kb
Host smart-5580da1d-5995-47e2-87e4-99fe66a22c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388233643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1388233643
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3306620541
Short name T359
Test name
Test status
Simulation time 12843994 ps
CPU time 0.76 seconds
Started Mar 19 01:17:34 PM PDT 24
Finished Mar 19 01:17:36 PM PDT 24
Peak memory 204836 kb
Host smart-9310a774-45a9-4faf-a48e-0bbd9bd95d5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306620541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3306620541
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.19267820
Short name T473
Test name
Test status
Simulation time 631091732 ps
CPU time 4.05 seconds
Started Mar 19 01:17:35 PM PDT 24
Finished Mar 19 01:17:39 PM PDT 24
Peak memory 233784 kb
Host smart-b66c9d74-a3b4-4555-894d-3d6d3b3ec258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19267820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.19267820
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1303466941
Short name T834
Test name
Test status
Simulation time 19909710 ps
CPU time 0.8 seconds
Started Mar 19 01:17:23 PM PDT 24
Finished Mar 19 01:17:24 PM PDT 24
Peak memory 205000 kb
Host smart-ab18f1a8-cee7-4097-ae06-379ffae0e92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303466941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1303466941
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2368796079
Short name T730
Test name
Test status
Simulation time 2935777978 ps
CPU time 56.96 seconds
Started Mar 19 01:17:34 PM PDT 24
Finished Mar 19 01:18:32 PM PDT 24
Peak memory 255964 kb
Host smart-323a6780-8465-4cf1-ac50-d991d885dc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368796079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2368796079
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1770699059
Short name T34
Test name
Test status
Simulation time 19777456356 ps
CPU time 80.34 seconds
Started Mar 19 01:17:36 PM PDT 24
Finished Mar 19 01:18:57 PM PDT 24
Peak memory 266376 kb
Host smart-f855e75a-9509-45ad-9035-136284856a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770699059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1770699059
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.258677224
Short name T957
Test name
Test status
Simulation time 55048218773 ps
CPU time 290.67 seconds
Started Mar 19 01:17:34 PM PDT 24
Finished Mar 19 01:22:25 PM PDT 24
Peak memory 255592 kb
Host smart-28944a83-feba-44e3-bcc3-af3d8efe7a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258677224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle
.258677224
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2681907089
Short name T478
Test name
Test status
Simulation time 1726583121 ps
CPU time 4.74 seconds
Started Mar 19 01:17:36 PM PDT 24
Finished Mar 19 01:17:42 PM PDT 24
Peak memory 219128 kb
Host smart-6201e21b-6f04-4710-9cb3-315adcf94028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681907089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2681907089
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.103428801
Short name T263
Test name
Test status
Simulation time 4924594119 ps
CPU time 16.87 seconds
Started Mar 19 01:17:35 PM PDT 24
Finished Mar 19 01:17:52 PM PDT 24
Peak memory 219460 kb
Host smart-e3643c61-2d32-4ed0-934f-7683811f6720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103428801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.103428801
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1868608358
Short name T692
Test name
Test status
Simulation time 163268447 ps
CPU time 2.09 seconds
Started Mar 19 01:17:36 PM PDT 24
Finished Mar 19 01:17:38 PM PDT 24
Peak memory 216292 kb
Host smart-55e150b7-42f4-4cce-9771-5eae3d2a5cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868608358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1868608358
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2692622180
Short name T396
Test name
Test status
Simulation time 1072181774 ps
CPU time 7.27 seconds
Started Mar 19 01:17:37 PM PDT 24
Finished Mar 19 01:17:45 PM PDT 24
Peak memory 232460 kb
Host smart-b27f4c72-15a3-4806-8560-f05bd06840f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692622180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2692622180
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.4201322509
Short name T374
Test name
Test status
Simulation time 1047412055 ps
CPU time 4.94 seconds
Started Mar 19 01:17:39 PM PDT 24
Finished Mar 19 01:17:44 PM PDT 24
Peak memory 218484 kb
Host smart-2c9be463-653c-40b5-9465-ed74d072536b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4201322509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.4201322509
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2776820449
Short name T626
Test name
Test status
Simulation time 65376672 ps
CPU time 1.19 seconds
Started Mar 19 01:17:38 PM PDT 24
Finished Mar 19 01:17:40 PM PDT 24
Peak memory 206420 kb
Host smart-898c780f-a065-491d-9fe9-546fd0d19386
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776820449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2776820449
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.4030317141
Short name T711
Test name
Test status
Simulation time 40133545405 ps
CPU time 57.26 seconds
Started Mar 19 01:17:35 PM PDT 24
Finished Mar 19 01:18:32 PM PDT 24
Peak memory 215720 kb
Host smart-a690b37c-a80d-45ad-a071-9e43478083f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030317141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.4030317141
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3419058308
Short name T691
Test name
Test status
Simulation time 9919765106 ps
CPU time 4.86 seconds
Started Mar 19 01:17:35 PM PDT 24
Finished Mar 19 01:17:41 PM PDT 24
Peak memory 215880 kb
Host smart-9091844e-550e-40d8-99a5-4048f1540a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419058308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3419058308
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1890193119
Short name T865
Test name
Test status
Simulation time 580728675 ps
CPU time 5.66 seconds
Started Mar 19 01:17:34 PM PDT 24
Finished Mar 19 01:17:40 PM PDT 24
Peak memory 215956 kb
Host smart-b4b13606-cfbe-420d-9f68-5c213dde13b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890193119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1890193119
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2406995298
Short name T427
Test name
Test status
Simulation time 53148520 ps
CPU time 0.72 seconds
Started Mar 19 01:17:38 PM PDT 24
Finished Mar 19 01:17:39 PM PDT 24
Peak memory 205224 kb
Host smart-52c19d89-30e9-4dfb-bedc-9a295a7914a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406995298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2406995298
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3082586627
Short name T881
Test name
Test status
Simulation time 1066203244 ps
CPU time 4.43 seconds
Started Mar 19 01:17:35 PM PDT 24
Finished Mar 19 01:17:40 PM PDT 24
Peak memory 233404 kb
Host smart-4ceca517-e032-42fd-8f36-9c51f256a142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082586627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3082586627
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.830411730
Short name T389
Test name
Test status
Simulation time 11511421 ps
CPU time 0.69 seconds
Started Mar 19 01:17:42 PM PDT 24
Finished Mar 19 01:17:43 PM PDT 24
Peak memory 204952 kb
Host smart-015bc8e9-110f-4364-9198-042f5a662a19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830411730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.830411730
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2401578148
Short name T772
Test name
Test status
Simulation time 5751513411 ps
CPU time 3.04 seconds
Started Mar 19 01:17:36 PM PDT 24
Finished Mar 19 01:17:39 PM PDT 24
Peak memory 218360 kb
Host smart-fb08fc70-9e0b-48ad-8910-0363bced132b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401578148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2401578148
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1608277139
Short name T284
Test name
Test status
Simulation time 73686756 ps
CPU time 0.79 seconds
Started Mar 19 01:17:37 PM PDT 24
Finished Mar 19 01:17:38 PM PDT 24
Peak memory 206040 kb
Host smart-e025389c-0ada-4de3-8766-7ee56ef5cd20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608277139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1608277139
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3222042221
Short name T89
Test name
Test status
Simulation time 11258212432 ps
CPU time 39.56 seconds
Started Mar 19 01:17:40 PM PDT 24
Finished Mar 19 01:18:20 PM PDT 24
Peak memory 249860 kb
Host smart-46b90fae-1342-4f18-8591-86802a1cc03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222042221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3222042221
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.4039740541
Short name T926
Test name
Test status
Simulation time 50388465772 ps
CPU time 116.68 seconds
Started Mar 19 01:17:42 PM PDT 24
Finished Mar 19 01:19:39 PM PDT 24
Peak memory 250924 kb
Host smart-7c606547-ede7-4b0a-81d3-94935562446c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039740541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.4039740541
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2189542192
Short name T907
Test name
Test status
Simulation time 15516553796 ps
CPU time 109.19 seconds
Started Mar 19 01:17:44 PM PDT 24
Finished Mar 19 01:19:33 PM PDT 24
Peak memory 248768 kb
Host smart-3639b238-a93b-4e5b-aedf-97c0630e3971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189542192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2189542192
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1630617190
Short name T876
Test name
Test status
Simulation time 10497397989 ps
CPU time 20.25 seconds
Started Mar 19 01:17:36 PM PDT 24
Finished Mar 19 01:17:57 PM PDT 24
Peak memory 238132 kb
Host smart-c7fd4da8-507d-4e3e-9b24-59da970c9e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630617190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1630617190
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1408428612
Short name T655
Test name
Test status
Simulation time 9097720412 ps
CPU time 8.76 seconds
Started Mar 19 01:17:36 PM PDT 24
Finished Mar 19 01:17:46 PM PDT 24
Peak memory 218480 kb
Host smart-d31a8429-7bc0-46dd-a3dd-537339e9b178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408428612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1408428612
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.4126863739
Short name T846
Test name
Test status
Simulation time 10383152587 ps
CPU time 17.84 seconds
Started Mar 19 01:17:38 PM PDT 24
Finished Mar 19 01:17:56 PM PDT 24
Peak memory 238596 kb
Host smart-a367d215-6985-4db9-b1a2-3e7ef730cf5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126863739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.4126863739
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1884656164
Short name T387
Test name
Test status
Simulation time 793110486 ps
CPU time 5.27 seconds
Started Mar 19 01:17:35 PM PDT 24
Finished Mar 19 01:17:41 PM PDT 24
Peak memory 233252 kb
Host smart-37962231-6cd8-4390-822d-b5f46c8ca66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884656164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1884656164
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3832076125
Short name T501
Test name
Test status
Simulation time 4026575143 ps
CPU time 11.24 seconds
Started Mar 19 01:17:36 PM PDT 24
Finished Mar 19 01:17:48 PM PDT 24
Peak memory 224044 kb
Host smart-7cf446a5-70ef-4755-8e32-245846dcdf38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832076125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3832076125
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2861862565
Short name T351
Test name
Test status
Simulation time 1787706611 ps
CPU time 5.22 seconds
Started Mar 19 01:17:34 PM PDT 24
Finished Mar 19 01:17:39 PM PDT 24
Peak memory 222228 kb
Host smart-a2c5e6ed-df48-4a0a-ac2d-f70472035e01
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2861862565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2861862565
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1818410287
Short name T597
Test name
Test status
Simulation time 5184240638 ps
CPU time 28.37 seconds
Started Mar 19 01:17:37 PM PDT 24
Finished Mar 19 01:18:05 PM PDT 24
Peak memory 215856 kb
Host smart-5f8be04c-396c-4c29-a104-58cde86b3161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818410287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1818410287
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1271078248
Short name T686
Test name
Test status
Simulation time 33187913888 ps
CPU time 22.47 seconds
Started Mar 19 01:17:34 PM PDT 24
Finished Mar 19 01:17:56 PM PDT 24
Peak memory 215908 kb
Host smart-f14d3f05-36dd-4e52-8609-135e2f014097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271078248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1271078248
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2455646210
Short name T441
Test name
Test status
Simulation time 3284841371 ps
CPU time 4.01 seconds
Started Mar 19 01:17:37 PM PDT 24
Finished Mar 19 01:17:41 PM PDT 24
Peak memory 215856 kb
Host smart-b44b5888-3aec-4d39-b474-b4fdc41c81e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455646210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2455646210
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2352358770
Short name T283
Test name
Test status
Simulation time 142242028 ps
CPU time 0.82 seconds
Started Mar 19 01:17:36 PM PDT 24
Finished Mar 19 01:17:38 PM PDT 24
Peak memory 205300 kb
Host smart-c9836558-deee-4f49-96a6-a7be957eed06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352358770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2352358770
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2878819700
Short name T968
Test name
Test status
Simulation time 7019104291 ps
CPU time 3.51 seconds
Started Mar 19 01:17:35 PM PDT 24
Finished Mar 19 01:17:39 PM PDT 24
Peak memory 216972 kb
Host smart-62d32633-cfdc-48ad-ad54-aec1295a94f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878819700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2878819700
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1929965508
Short name T316
Test name
Test status
Simulation time 35246918 ps
CPU time 0.71 seconds
Started Mar 19 01:13:32 PM PDT 24
Finished Mar 19 01:13:33 PM PDT 24
Peak memory 205248 kb
Host smart-a79ea94e-0c6e-4e6c-85a4-1017b5630a15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929965508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
929965508
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.4005099418
Short name T531
Test name
Test status
Simulation time 56966232 ps
CPU time 2.48 seconds
Started Mar 19 01:13:27 PM PDT 24
Finished Mar 19 01:13:30 PM PDT 24
Peak memory 233112 kb
Host smart-a48f045b-512b-4b63-a969-1d22cc6e1ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005099418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.4005099418
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3021488477
Short name T332
Test name
Test status
Simulation time 59694188 ps
CPU time 0.76 seconds
Started Mar 19 01:13:15 PM PDT 24
Finished Mar 19 01:13:16 PM PDT 24
Peak memory 204936 kb
Host smart-70212b18-6a8d-4600-ac88-e425959c9de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021488477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3021488477
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.2448143985
Short name T756
Test name
Test status
Simulation time 99817899007 ps
CPU time 497.27 seconds
Started Mar 19 01:13:28 PM PDT 24
Finished Mar 19 01:21:45 PM PDT 24
Peak memory 265108 kb
Host smart-5dd9c8d9-7e2b-4bab-9f7c-efb22e983ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448143985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2448143985
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1427831560
Short name T624
Test name
Test status
Simulation time 11455728989 ps
CPU time 63.05 seconds
Started Mar 19 01:13:29 PM PDT 24
Finished Mar 19 01:14:32 PM PDT 24
Peak memory 252408 kb
Host smart-3a012f9e-f554-4c6d-bf42-c499d3e61413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427831560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1427831560
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2062649801
Short name T493
Test name
Test status
Simulation time 2140125871 ps
CPU time 15.2 seconds
Started Mar 19 01:13:28 PM PDT 24
Finished Mar 19 01:13:45 PM PDT 24
Peak memory 238424 kb
Host smart-ea350a03-0c37-409d-b972-f2695a4b9c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062649801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2062649801
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1373802246
Short name T660
Test name
Test status
Simulation time 581765534 ps
CPU time 2.75 seconds
Started Mar 19 01:13:30 PM PDT 24
Finished Mar 19 01:13:34 PM PDT 24
Peak memory 234788 kb
Host smart-d2860ea2-4486-43dc-b8c2-6eafb7536315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373802246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1373802246
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3159442383
Short name T617
Test name
Test status
Simulation time 22462040114 ps
CPU time 20.25 seconds
Started Mar 19 01:13:29 PM PDT 24
Finished Mar 19 01:13:50 PM PDT 24
Peak memory 229924 kb
Host smart-c9ccbb39-94ea-4450-baf8-a5b18122df80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159442383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3159442383
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2323283953
Short name T481
Test name
Test status
Simulation time 81819274393 ps
CPU time 32.01 seconds
Started Mar 19 01:13:29 PM PDT 24
Finished Mar 19 01:14:01 PM PDT 24
Peak memory 226928 kb
Host smart-72098619-a277-4346-b891-8ad9cb449484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323283953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2323283953
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.244265457
Short name T194
Test name
Test status
Simulation time 4647454361 ps
CPU time 5.51 seconds
Started Mar 19 01:13:29 PM PDT 24
Finished Mar 19 01:13:35 PM PDT 24
Peak memory 232260 kb
Host smart-e1c782f5-0bc3-4e46-8f20-5175de596993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244265457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.244265457
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.3331449586
Short name T289
Test name
Test status
Simulation time 18506019 ps
CPU time 0.79 seconds
Started Mar 19 01:13:17 PM PDT 24
Finished Mar 19 01:13:18 PM PDT 24
Peak memory 215788 kb
Host smart-20ff6b14-2c6e-4549-a636-561a20b0b491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331449586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.3331449586
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.492760727
Short name T571
Test name
Test status
Simulation time 795470693 ps
CPU time 4.21 seconds
Started Mar 19 01:13:30 PM PDT 24
Finished Mar 19 01:13:35 PM PDT 24
Peak memory 221916 kb
Host smart-a42c80e9-208b-4f7e-b394-51e009cb5bfb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=492760727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.492760727
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1718301447
Short name T77
Test name
Test status
Simulation time 61497795 ps
CPU time 1.07 seconds
Started Mar 19 01:13:28 PM PDT 24
Finished Mar 19 01:13:30 PM PDT 24
Peak memory 234440 kb
Host smart-242270d0-3277-4c04-a30f-dcf11e2334bb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718301447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1718301447
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1584874314
Short name T154
Test name
Test status
Simulation time 3645103333 ps
CPU time 69.87 seconds
Started Mar 19 01:13:28 PM PDT 24
Finished Mar 19 01:14:39 PM PDT 24
Peak memory 254804 kb
Host smart-a860dd92-f93a-4f36-875c-a79762f20bc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584874314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1584874314
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3426435561
Short name T474
Test name
Test status
Simulation time 543202003 ps
CPU time 4.85 seconds
Started Mar 19 01:13:15 PM PDT 24
Finished Mar 19 01:13:20 PM PDT 24
Peak memory 215800 kb
Host smart-3ce45946-a244-4a6d-8c47-00795d9a3918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426435561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3426435561
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.4212303953
Short name T669
Test name
Test status
Simulation time 931893056 ps
CPU time 6.51 seconds
Started Mar 19 01:13:17 PM PDT 24
Finished Mar 19 01:13:24 PM PDT 24
Peak memory 215796 kb
Host smart-b4dfc6f9-a9e4-439d-a83a-2de6cdf82aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212303953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.4212303953
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1298801538
Short name T280
Test name
Test status
Simulation time 324252675 ps
CPU time 4.6 seconds
Started Mar 19 01:13:29 PM PDT 24
Finished Mar 19 01:13:34 PM PDT 24
Peak memory 215852 kb
Host smart-9e0f557b-1f47-46f9-9469-9b440e660b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298801538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1298801538
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3673455095
Short name T504
Test name
Test status
Simulation time 162732709 ps
CPU time 0.9 seconds
Started Mar 19 01:13:30 PM PDT 24
Finished Mar 19 01:13:31 PM PDT 24
Peak memory 205244 kb
Host smart-c5d2c717-965a-462d-b2b0-22c9c06bdca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673455095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3673455095
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2363228
Short name T465
Test name
Test status
Simulation time 290842295 ps
CPU time 2.88 seconds
Started Mar 19 01:13:31 PM PDT 24
Finished Mar 19 01:13:34 PM PDT 24
Peak memory 218240 kb
Host smart-57dd69ba-b115-427d-b9c6-9a05f6b5b64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2363228
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3254627230
Short name T716
Test name
Test status
Simulation time 40906562 ps
CPU time 0.71 seconds
Started Mar 19 01:17:48 PM PDT 24
Finished Mar 19 01:17:49 PM PDT 24
Peak memory 204816 kb
Host smart-890cd5e8-8939-404d-bfd7-5a9896c62585
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254627230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3254627230
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1780818578
Short name T261
Test name
Test status
Simulation time 878554353 ps
CPU time 3.26 seconds
Started Mar 19 01:17:41 PM PDT 24
Finished Mar 19 01:17:45 PM PDT 24
Peak memory 218540 kb
Host smart-500a596c-31d8-4dd5-9a70-23f2dff8090d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780818578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1780818578
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.976250479
Short name T325
Test name
Test status
Simulation time 40895164 ps
CPU time 0.73 seconds
Started Mar 19 01:17:39 PM PDT 24
Finished Mar 19 01:17:40 PM PDT 24
Peak memory 204936 kb
Host smart-5a5ccbe0-f4e6-464b-9a4e-635818a3f2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976250479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.976250479
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.437296464
Short name T87
Test name
Test status
Simulation time 30882034789 ps
CPU time 152.77 seconds
Started Mar 19 01:17:51 PM PDT 24
Finished Mar 19 01:20:23 PM PDT 24
Peak memory 251428 kb
Host smart-2b984d26-3e97-413d-b97d-fabb59d5a179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437296464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.437296464
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.2344690118
Short name T48
Test name
Test status
Simulation time 98731529384 ps
CPU time 345.96 seconds
Started Mar 19 01:17:49 PM PDT 24
Finished Mar 19 01:23:35 PM PDT 24
Peak memory 256940 kb
Host smart-4fa5361c-3178-416b-868a-bbe701f9291d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344690118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2344690118
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1305981282
Short name T674
Test name
Test status
Simulation time 89846209662 ps
CPU time 258.07 seconds
Started Mar 19 01:17:48 PM PDT 24
Finished Mar 19 01:22:06 PM PDT 24
Peak memory 271260 kb
Host smart-b80c5dcb-62b5-47e5-ab83-4fb293f82a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305981282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1305981282
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_intercept.320937771
Short name T820
Test name
Test status
Simulation time 424687934 ps
CPU time 4.64 seconds
Started Mar 19 01:17:41 PM PDT 24
Finished Mar 19 01:17:46 PM PDT 24
Peak memory 233420 kb
Host smart-c2c1cadb-8df0-44a9-8411-ad1ea9668701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320937771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.320937771
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1822827910
Short name T882
Test name
Test status
Simulation time 2150008806 ps
CPU time 15.98 seconds
Started Mar 19 01:17:40 PM PDT 24
Finished Mar 19 01:17:56 PM PDT 24
Peak memory 231348 kb
Host smart-9e0dde5f-37b4-41cf-a6ce-4d4557582b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822827910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1822827910
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3726932661
Short name T932
Test name
Test status
Simulation time 7698925704 ps
CPU time 10.83 seconds
Started Mar 19 01:17:39 PM PDT 24
Finished Mar 19 01:17:50 PM PDT 24
Peak memory 218144 kb
Host smart-6ff9cd3d-67ae-4ac3-b969-ab177209360f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726932661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3726932661
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.432105433
Short name T693
Test name
Test status
Simulation time 44238871 ps
CPU time 2.59 seconds
Started Mar 19 01:17:40 PM PDT 24
Finished Mar 19 01:17:43 PM PDT 24
Peak memory 232260 kb
Host smart-66ccec77-4231-49fe-a0d3-de8bda0a58a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432105433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.432105433
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2355913572
Short name T375
Test name
Test status
Simulation time 8745314949 ps
CPU time 4.64 seconds
Started Mar 19 01:17:47 PM PDT 24
Finished Mar 19 01:17:52 PM PDT 24
Peak memory 218556 kb
Host smart-a71f80ec-31b1-43c6-a558-40186ec6b1e8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2355913572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2355913572
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3485369596
Short name T874
Test name
Test status
Simulation time 101672583 ps
CPU time 0.9 seconds
Started Mar 19 01:17:48 PM PDT 24
Finished Mar 19 01:17:49 PM PDT 24
Peak memory 205380 kb
Host smart-a57517c0-38e0-457b-ad98-3844ecc34f28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485369596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3485369596
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3345551732
Short name T353
Test name
Test status
Simulation time 12301435893 ps
CPU time 19.02 seconds
Started Mar 19 01:17:39 PM PDT 24
Finished Mar 19 01:17:58 PM PDT 24
Peak memory 215864 kb
Host smart-41996f15-2840-4b6b-bb15-eecdfc44cae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345551732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3345551732
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2294154024
Short name T350
Test name
Test status
Simulation time 2317250748 ps
CPU time 4.05 seconds
Started Mar 19 01:17:44 PM PDT 24
Finished Mar 19 01:17:48 PM PDT 24
Peak memory 215844 kb
Host smart-ec36995a-3f98-427e-8a2b-1ae750b6ddfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294154024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2294154024
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3128161892
Short name T487
Test name
Test status
Simulation time 278216824 ps
CPU time 4.56 seconds
Started Mar 19 01:17:42 PM PDT 24
Finished Mar 19 01:17:46 PM PDT 24
Peak memory 215768 kb
Host smart-a91628ab-4d61-4f9c-8a95-c32c54b75be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128161892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3128161892
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2811558914
Short name T98
Test name
Test status
Simulation time 183804926 ps
CPU time 0.91 seconds
Started Mar 19 01:17:41 PM PDT 24
Finished Mar 19 01:17:42 PM PDT 24
Peak memory 205212 kb
Host smart-edeab4f7-b700-4e96-be04-cbba37422965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811558914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2811558914
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3567383602
Short name T610
Test name
Test status
Simulation time 7134517343 ps
CPU time 19.57 seconds
Started Mar 19 01:17:44 PM PDT 24
Finished Mar 19 01:18:04 PM PDT 24
Peak memory 240436 kb
Host smart-da3e86f4-2b48-48c8-b2b3-fcf9de61c699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567383602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3567383602
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.131714060
Short name T313
Test name
Test status
Simulation time 19031990 ps
CPU time 0.71 seconds
Started Mar 19 01:17:47 PM PDT 24
Finished Mar 19 01:17:48 PM PDT 24
Peak memory 204828 kb
Host smart-7515cbd0-ba0e-42cf-afc2-30057e02959c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131714060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.131714060
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2308320550
Short name T613
Test name
Test status
Simulation time 207073534 ps
CPU time 4.21 seconds
Started Mar 19 01:17:46 PM PDT 24
Finished Mar 19 01:17:50 PM PDT 24
Peak memory 233164 kb
Host smart-66066e28-4f1e-4d69-b5e6-ce558b4acfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308320550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2308320550
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2686735134
Short name T524
Test name
Test status
Simulation time 78286357 ps
CPU time 0.79 seconds
Started Mar 19 01:17:47 PM PDT 24
Finished Mar 19 01:17:48 PM PDT 24
Peak memory 205968 kb
Host smart-85af141b-5c52-4491-90d0-baaa1b24d8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686735134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2686735134
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2978288851
Short name T214
Test name
Test status
Simulation time 4146081464 ps
CPU time 19.5 seconds
Started Mar 19 01:17:47 PM PDT 24
Finished Mar 19 01:18:07 PM PDT 24
Peak memory 220248 kb
Host smart-e15479ba-ff7b-44c9-8829-539e3053c4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978288851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2978288851
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.263883625
Short name T268
Test name
Test status
Simulation time 2519576237 ps
CPU time 22.85 seconds
Started Mar 19 01:17:47 PM PDT 24
Finished Mar 19 01:18:10 PM PDT 24
Peak memory 244580 kb
Host smart-28eb4368-899d-4d5c-877e-348fa38978d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263883625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.263883625
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1095909884
Short name T608
Test name
Test status
Simulation time 658450178 ps
CPU time 3.38 seconds
Started Mar 19 01:17:50 PM PDT 24
Finished Mar 19 01:17:54 PM PDT 24
Peak memory 224004 kb
Host smart-c31f6e24-2dc4-439b-8422-fdc414a2cdf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095909884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1095909884
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.48071650
Short name T578
Test name
Test status
Simulation time 8580004448 ps
CPU time 16.16 seconds
Started Mar 19 01:17:53 PM PDT 24
Finished Mar 19 01:18:09 PM PDT 24
Peak memory 249452 kb
Host smart-3274a156-0ad0-4e37-b38b-b6204d862f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48071650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.48071650
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1841520619
Short name T594
Test name
Test status
Simulation time 110982639 ps
CPU time 2.13 seconds
Started Mar 19 01:17:48 PM PDT 24
Finished Mar 19 01:17:50 PM PDT 24
Peak memory 217860 kb
Host smart-710d1d6a-efae-47b5-bb6e-3cbe22682baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841520619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1841520619
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2805023984
Short name T308
Test name
Test status
Simulation time 2055685924 ps
CPU time 6.58 seconds
Started Mar 19 01:17:49 PM PDT 24
Finished Mar 19 01:17:55 PM PDT 24
Peak memory 232240 kb
Host smart-45bffc21-b25b-446a-9fd1-9fe72c4b135c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805023984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2805023984
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.563225106
Short name T426
Test name
Test status
Simulation time 12335518067 ps
CPU time 6.99 seconds
Started Mar 19 01:17:51 PM PDT 24
Finished Mar 19 01:17:58 PM PDT 24
Peak memory 221908 kb
Host smart-75c20964-4342-42c7-be5c-25047355cca8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=563225106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.563225106
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3376853706
Short name T511
Test name
Test status
Simulation time 9352628506 ps
CPU time 92.48 seconds
Started Mar 19 01:17:48 PM PDT 24
Finished Mar 19 01:19:20 PM PDT 24
Peak memory 252636 kb
Host smart-9ae86110-506f-4441-b5db-1d1c297eb880
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376853706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3376853706
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3447444057
Short name T278
Test name
Test status
Simulation time 7202004816 ps
CPU time 23.34 seconds
Started Mar 19 01:17:48 PM PDT 24
Finished Mar 19 01:18:11 PM PDT 24
Peak memory 218096 kb
Host smart-39f37e1a-96a2-4acc-9375-3729ad787850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447444057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3447444057
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3950555819
Short name T3
Test name
Test status
Simulation time 984579921 ps
CPU time 7.05 seconds
Started Mar 19 01:17:51 PM PDT 24
Finished Mar 19 01:17:58 PM PDT 24
Peak memory 215640 kb
Host smart-af118149-93a5-4ce4-9409-4dc8ac1b60cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950555819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3950555819
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2964472040
Short name T650
Test name
Test status
Simulation time 672569925 ps
CPU time 3.4 seconds
Started Mar 19 01:17:53 PM PDT 24
Finished Mar 19 01:17:56 PM PDT 24
Peak memory 215828 kb
Host smart-4cd1fd69-a66c-4c08-8020-eaff83cfbe75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964472040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2964472040
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2552683600
Short name T592
Test name
Test status
Simulation time 68660234 ps
CPU time 0.81 seconds
Started Mar 19 01:17:50 PM PDT 24
Finished Mar 19 01:17:51 PM PDT 24
Peak memory 205228 kb
Host smart-c03a5b09-1289-4db7-9bf5-5dab18009f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552683600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2552683600
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.659205852
Short name T590
Test name
Test status
Simulation time 4362587085 ps
CPU time 15.1 seconds
Started Mar 19 01:17:49 PM PDT 24
Finished Mar 19 01:18:05 PM PDT 24
Peak memory 235192 kb
Host smart-ca7e3fd8-f004-481e-9f2f-9ce6c62c115c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659205852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.659205852
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3356230313
Short name T753
Test name
Test status
Simulation time 36408998 ps
CPU time 0.72 seconds
Started Mar 19 01:17:56 PM PDT 24
Finished Mar 19 01:17:57 PM PDT 24
Peak memory 204868 kb
Host smart-99909fa6-4d36-430d-972e-f0c046c05f72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356230313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3356230313
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.123281740
Short name T386
Test name
Test status
Simulation time 811351916 ps
CPU time 5.6 seconds
Started Mar 19 01:17:56 PM PDT 24
Finished Mar 19 01:18:02 PM PDT 24
Peak memory 232908 kb
Host smart-66e7ea81-09a1-4bde-bc4e-b44a95d232ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123281740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.123281740
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1977413403
Short name T356
Test name
Test status
Simulation time 129479892 ps
CPU time 0.76 seconds
Started Mar 19 01:17:54 PM PDT 24
Finished Mar 19 01:17:55 PM PDT 24
Peak memory 204972 kb
Host smart-d01bc488-7a47-4a77-80d4-d70cb3e864cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977413403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1977413403
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.461219273
Short name T234
Test name
Test status
Simulation time 4667238578 ps
CPU time 89.08 seconds
Started Mar 19 01:17:56 PM PDT 24
Finished Mar 19 01:19:25 PM PDT 24
Peak memory 256228 kb
Host smart-b8fa9162-e7a5-4fe4-911b-d2296ffbc4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461219273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.461219273
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2024885412
Short name T238
Test name
Test status
Simulation time 93599977068 ps
CPU time 161.03 seconds
Started Mar 19 01:17:59 PM PDT 24
Finished Mar 19 01:20:40 PM PDT 24
Peak memory 265104 kb
Host smart-13a5365e-9e48-48b6-b420-229bb267feba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024885412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2024885412
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1248676241
Short name T793
Test name
Test status
Simulation time 1981122690 ps
CPU time 15.41 seconds
Started Mar 19 01:17:55 PM PDT 24
Finished Mar 19 01:18:10 PM PDT 24
Peak memory 234648 kb
Host smart-f8bde0a4-5cca-4fd2-b496-298c78204616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248676241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1248676241
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2575749929
Short name T761
Test name
Test status
Simulation time 3782630119 ps
CPU time 5.55 seconds
Started Mar 19 01:18:01 PM PDT 24
Finished Mar 19 01:18:06 PM PDT 24
Peak memory 219288 kb
Host smart-e29be9c6-66e4-4c34-8013-5f10f0eecc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575749929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2575749929
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.1921346569
Short name T576
Test name
Test status
Simulation time 750213716 ps
CPU time 6.08 seconds
Started Mar 19 01:17:57 PM PDT 24
Finished Mar 19 01:18:03 PM PDT 24
Peak memory 229700 kb
Host smart-b51f1700-58c4-48be-ae1f-4170f60b84d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921346569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1921346569
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1220383538
Short name T503
Test name
Test status
Simulation time 5987517888 ps
CPU time 24.06 seconds
Started Mar 19 01:18:00 PM PDT 24
Finished Mar 19 01:18:24 PM PDT 24
Peak memory 248620 kb
Host smart-cf73d01d-9c6a-4206-89f9-0763e81c36ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220383538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1220383538
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3194175007
Short name T27
Test name
Test status
Simulation time 1967909505 ps
CPU time 9.01 seconds
Started Mar 19 01:17:58 PM PDT 24
Finished Mar 19 01:18:07 PM PDT 24
Peak memory 236552 kb
Host smart-b58d512c-4da7-49ac-8be6-594af6e0adcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194175007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3194175007
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.4284814301
Short name T855
Test name
Test status
Simulation time 427551707 ps
CPU time 3.49 seconds
Started Mar 19 01:17:55 PM PDT 24
Finished Mar 19 01:17:58 PM PDT 24
Peak memory 221256 kb
Host smart-c3152415-51f0-44ba-b1b4-3f42e08e1b9c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4284814301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.4284814301
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3332147338
Short name T891
Test name
Test status
Simulation time 1719734953 ps
CPU time 11.24 seconds
Started Mar 19 01:17:55 PM PDT 24
Finished Mar 19 01:18:06 PM PDT 24
Peak memory 218272 kb
Host smart-1c12f268-7471-4ad7-b581-16f7a14037ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332147338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3332147338
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3410152499
Short name T430
Test name
Test status
Simulation time 605953355 ps
CPU time 3.77 seconds
Started Mar 19 01:18:01 PM PDT 24
Finished Mar 19 01:18:05 PM PDT 24
Peak memory 215720 kb
Host smart-b054bdd5-f0f5-453b-a137-a00d5e2ef914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410152499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3410152499
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3996667864
Short name T393
Test name
Test status
Simulation time 69921594 ps
CPU time 0.83 seconds
Started Mar 19 01:18:00 PM PDT 24
Finished Mar 19 01:18:01 PM PDT 24
Peak memory 205272 kb
Host smart-2c2c338f-bb83-432d-99c4-cb1e065014e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996667864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3996667864
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1853407641
Short name T817
Test name
Test status
Simulation time 121084691 ps
CPU time 0.82 seconds
Started Mar 19 01:18:00 PM PDT 24
Finished Mar 19 01:18:01 PM PDT 24
Peak memory 205272 kb
Host smart-3b6fbdae-d343-41ac-86c4-0b7d9cca7f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853407641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1853407641
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.2422082301
Short name T562
Test name
Test status
Simulation time 5899867941 ps
CPU time 19.84 seconds
Started Mar 19 01:17:58 PM PDT 24
Finished Mar 19 01:18:18 PM PDT 24
Peak memory 233912 kb
Host smart-ddd4fdce-c672-4c6c-ace1-713d81ed1ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422082301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2422082301
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3971483739
Short name T798
Test name
Test status
Simulation time 11326375 ps
CPU time 0.74 seconds
Started Mar 19 01:18:05 PM PDT 24
Finished Mar 19 01:18:05 PM PDT 24
Peak memory 204872 kb
Host smart-c3e76b98-ce5d-4539-b0ba-4f9b988ae4b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971483739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3971483739
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.4066574165
Short name T908
Test name
Test status
Simulation time 354646543 ps
CPU time 3.63 seconds
Started Mar 19 01:18:08 PM PDT 24
Finished Mar 19 01:18:11 PM PDT 24
Peak memory 218984 kb
Host smart-d78d7640-271f-45d2-b7f4-a9198fda9603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066574165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.4066574165
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.965527134
Short name T702
Test name
Test status
Simulation time 18629903 ps
CPU time 0.79 seconds
Started Mar 19 01:18:00 PM PDT 24
Finished Mar 19 01:18:01 PM PDT 24
Peak memory 205300 kb
Host smart-83b7990a-fd1b-4cb7-9435-b02eddd54ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965527134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.965527134
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.913800052
Short name T221
Test name
Test status
Simulation time 67193467321 ps
CPU time 342.83 seconds
Started Mar 19 01:18:07 PM PDT 24
Finished Mar 19 01:23:50 PM PDT 24
Peak memory 270716 kb
Host smart-cfcc85a4-27ef-445c-9248-b7ecc3962d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913800052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.913800052
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1113456606
Short name T934
Test name
Test status
Simulation time 60736450160 ps
CPU time 120.38 seconds
Started Mar 19 01:18:11 PM PDT 24
Finished Mar 19 01:20:11 PM PDT 24
Peak memory 256928 kb
Host smart-19ab6f14-a749-4e9d-9d35-5d5b46ddb47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113456606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1113456606
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2672348829
Short name T222
Test name
Test status
Simulation time 178603034765 ps
CPU time 391.51 seconds
Started Mar 19 01:18:07 PM PDT 24
Finished Mar 19 01:24:39 PM PDT 24
Peak memory 271640 kb
Host smart-4f9463fd-7665-4ac2-8db2-dfc39ee417e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672348829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2672348829
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.508774304
Short name T366
Test name
Test status
Simulation time 11180545648 ps
CPU time 57.36 seconds
Started Mar 19 01:18:04 PM PDT 24
Finished Mar 19 01:19:01 PM PDT 24
Peak memory 248596 kb
Host smart-2ae1d8eb-78d4-4e19-91a9-c7716fb4de48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508774304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.508774304
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1392288669
Short name T199
Test name
Test status
Simulation time 5801268991 ps
CPU time 10.7 seconds
Started Mar 19 01:18:08 PM PDT 24
Finished Mar 19 01:18:19 PM PDT 24
Peak memory 233284 kb
Host smart-fe8b867a-af36-4681-a6bb-061e1801a0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392288669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1392288669
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3888596789
Short name T818
Test name
Test status
Simulation time 5152308934 ps
CPU time 10.23 seconds
Started Mar 19 01:18:05 PM PDT 24
Finished Mar 19 01:18:15 PM PDT 24
Peak memory 220328 kb
Host smart-0bcf3788-bac9-4026-9483-6e7746f2666e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888596789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3888596789
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1969852077
Short name T205
Test name
Test status
Simulation time 289975874 ps
CPU time 3.14 seconds
Started Mar 19 01:18:08 PM PDT 24
Finished Mar 19 01:18:12 PM PDT 24
Peak memory 224016 kb
Host smart-8592b892-4943-49b6-811d-b00a673ee4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969852077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1969852077
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1982121885
Short name T619
Test name
Test status
Simulation time 3305456056 ps
CPU time 12.77 seconds
Started Mar 19 01:18:05 PM PDT 24
Finished Mar 19 01:18:18 PM PDT 24
Peak memory 232728 kb
Host smart-a1ec38c6-480a-42cc-96d2-167b847da7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982121885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1982121885
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3956627421
Short name T508
Test name
Test status
Simulation time 185472630 ps
CPU time 3.99 seconds
Started Mar 19 01:18:06 PM PDT 24
Finished Mar 19 01:18:11 PM PDT 24
Peak memory 221896 kb
Host smart-657e9e0b-cdfd-4923-855a-eb93421b179a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3956627421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3956627421
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2159120207
Short name T229
Test name
Test status
Simulation time 79580983055 ps
CPU time 531.91 seconds
Started Mar 19 01:18:07 PM PDT 24
Finished Mar 19 01:26:59 PM PDT 24
Peak memory 273016 kb
Host smart-2ed23f4c-6de6-4be6-b6e5-38e2e2c27cd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159120207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2159120207
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.4025852682
Short name T596
Test name
Test status
Simulation time 2026592110 ps
CPU time 17.66 seconds
Started Mar 19 01:18:04 PM PDT 24
Finished Mar 19 01:18:21 PM PDT 24
Peak memory 215796 kb
Host smart-9d064205-c23e-4d08-9298-b622f30e0f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025852682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.4025852682
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3476091967
Short name T784
Test name
Test status
Simulation time 4506899837 ps
CPU time 11.63 seconds
Started Mar 19 01:18:07 PM PDT 24
Finished Mar 19 01:18:18 PM PDT 24
Peak memory 215840 kb
Host smart-32f12730-76e6-4f14-82fb-55b886a22442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476091967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3476091967
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.4134416958
Short name T310
Test name
Test status
Simulation time 1214035897 ps
CPU time 3.9 seconds
Started Mar 19 01:18:04 PM PDT 24
Finished Mar 19 01:18:08 PM PDT 24
Peak memory 215776 kb
Host smart-38a0a1d3-16ee-4e4c-905d-803fd4e3e6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134416958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.4134416958
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1769539947
Short name T678
Test name
Test status
Simulation time 118637923 ps
CPU time 0.89 seconds
Started Mar 19 01:18:07 PM PDT 24
Finished Mar 19 01:18:08 PM PDT 24
Peak memory 205268 kb
Host smart-b63fb6cc-e466-46ff-9d89-1b23ace0291e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769539947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1769539947
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.917749065
Short name T623
Test name
Test status
Simulation time 122550285 ps
CPU time 2.96 seconds
Started Mar 19 01:18:05 PM PDT 24
Finished Mar 19 01:18:08 PM PDT 24
Peak memory 233232 kb
Host smart-85fc1d09-8d7d-4355-957e-9b1287d51293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917749065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.917749065
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1945993105
Short name T715
Test name
Test status
Simulation time 11580695 ps
CPU time 0.72 seconds
Started Mar 19 01:18:21 PM PDT 24
Finished Mar 19 01:18:22 PM PDT 24
Peak memory 204892 kb
Host smart-30445af8-3e52-40d1-91c8-83d06b77ae6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945993105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1945993105
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2975934677
Short name T630
Test name
Test status
Simulation time 98315383 ps
CPU time 2.38 seconds
Started Mar 19 01:18:14 PM PDT 24
Finished Mar 19 01:18:17 PM PDT 24
Peak memory 233400 kb
Host smart-9f48bb4d-d8cf-4b06-87c9-54ad04299019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975934677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2975934677
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.297789489
Short name T286
Test name
Test status
Simulation time 58079365 ps
CPU time 0.77 seconds
Started Mar 19 01:18:07 PM PDT 24
Finished Mar 19 01:18:08 PM PDT 24
Peak memory 205296 kb
Host smart-87026da8-f777-48c8-90b7-59fb95b42ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297789489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.297789489
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1802312173
Short name T583
Test name
Test status
Simulation time 29949679422 ps
CPU time 155.2 seconds
Started Mar 19 01:18:12 PM PDT 24
Finished Mar 19 01:20:48 PM PDT 24
Peak memory 251884 kb
Host smart-b10ce034-5f58-42d6-b27f-459c0e9a63c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802312173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1802312173
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2327806616
Short name T242
Test name
Test status
Simulation time 16303669841 ps
CPU time 93.13 seconds
Started Mar 19 01:18:14 PM PDT 24
Finished Mar 19 01:19:47 PM PDT 24
Peak memory 264532 kb
Host smart-c428e214-aba0-410c-8781-8fdd86418217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327806616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2327806616
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.471918430
Short name T179
Test name
Test status
Simulation time 3865580242 ps
CPU time 67.39 seconds
Started Mar 19 01:18:14 PM PDT 24
Finished Mar 19 01:19:22 PM PDT 24
Peak memory 267448 kb
Host smart-bb854dc2-54c9-406f-a4e6-63d8f88de731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471918430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle
.471918430
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2865193042
Short name T472
Test name
Test status
Simulation time 8692362172 ps
CPU time 24.47 seconds
Started Mar 19 01:18:16 PM PDT 24
Finished Mar 19 01:18:41 PM PDT 24
Peak memory 238972 kb
Host smart-b783f3ee-7f9b-463b-a1dd-937e4d410bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865193042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2865193042
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3396812579
Short name T86
Test name
Test status
Simulation time 712427596 ps
CPU time 4.05 seconds
Started Mar 19 01:18:10 PM PDT 24
Finished Mar 19 01:18:14 PM PDT 24
Peak memory 217392 kb
Host smart-2f263312-e6b4-497c-b883-dfb680d5d2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396812579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3396812579
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3699029853
Short name T852
Test name
Test status
Simulation time 123675976 ps
CPU time 2.58 seconds
Started Mar 19 01:18:13 PM PDT 24
Finished Mar 19 01:18:16 PM PDT 24
Peak memory 217924 kb
Host smart-8ee5e64b-ae80-4832-ad87-8aba970ed7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699029853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3699029853
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.430985362
Short name T709
Test name
Test status
Simulation time 1525631302 ps
CPU time 7.89 seconds
Started Mar 19 01:18:11 PM PDT 24
Finished Mar 19 01:18:19 PM PDT 24
Peak memory 219896 kb
Host smart-38cf1645-dce4-4e7a-8c7d-56a106df1f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430985362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.430985362
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2059250042
Short name T298
Test name
Test status
Simulation time 3888232101 ps
CPU time 6.29 seconds
Started Mar 19 01:18:15 PM PDT 24
Finished Mar 19 01:18:22 PM PDT 24
Peak memory 238932 kb
Host smart-530b2b40-edbd-4943-be7f-671c45aaa365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059250042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2059250042
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1649067475
Short name T853
Test name
Test status
Simulation time 392602318 ps
CPU time 4.18 seconds
Started Mar 19 01:18:14 PM PDT 24
Finished Mar 19 01:18:18 PM PDT 24
Peak memory 218716 kb
Host smart-d04bfb1b-2f74-45f9-a1aa-9ee94fccd12a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1649067475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1649067475
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2859861344
Short name T706
Test name
Test status
Simulation time 250526087412 ps
CPU time 245.04 seconds
Started Mar 19 01:18:21 PM PDT 24
Finished Mar 19 01:22:26 PM PDT 24
Peak memory 267456 kb
Host smart-e5e2b0cb-7c35-4788-afb5-3a887b906942
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859861344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2859861344
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1266161848
Short name T937
Test name
Test status
Simulation time 17539947657 ps
CPU time 29.95 seconds
Started Mar 19 01:18:11 PM PDT 24
Finished Mar 19 01:18:41 PM PDT 24
Peak memory 215860 kb
Host smart-2ba953eb-fd81-4677-b2a2-8bf0fde9b987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266161848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1266161848
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3776130575
Short name T502
Test name
Test status
Simulation time 3147927060 ps
CPU time 7.19 seconds
Started Mar 19 01:18:07 PM PDT 24
Finished Mar 19 01:18:15 PM PDT 24
Peak memory 215776 kb
Host smart-ad0a0068-fa8e-40dc-8e93-4a25689b5c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776130575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3776130575
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.689076820
Short name T24
Test name
Test status
Simulation time 2117774298 ps
CPU time 3.52 seconds
Started Mar 19 01:18:12 PM PDT 24
Finished Mar 19 01:18:16 PM PDT 24
Peak memory 215868 kb
Host smart-cbe037c5-37e1-4ca8-b660-60590a4892b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689076820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.689076820
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3570851821
Short name T632
Test name
Test status
Simulation time 130060581 ps
CPU time 1 seconds
Started Mar 19 01:18:12 PM PDT 24
Finished Mar 19 01:18:13 PM PDT 24
Peak memory 205848 kb
Host smart-0318f71d-4788-4213-b976-96db7dae79d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570851821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3570851821
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1956971621
Short name T689
Test name
Test status
Simulation time 21181495200 ps
CPU time 32.17 seconds
Started Mar 19 01:18:13 PM PDT 24
Finished Mar 19 01:18:45 PM PDT 24
Peak memory 236912 kb
Host smart-005445b5-4ef8-4fe9-b3a0-aabbc17b4baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956971621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1956971621
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.326880638
Short name T303
Test name
Test status
Simulation time 17856839 ps
CPU time 0.73 seconds
Started Mar 19 01:18:22 PM PDT 24
Finished Mar 19 01:18:23 PM PDT 24
Peak memory 204320 kb
Host smart-e03fe75e-838a-441e-b89d-6bfd0dfc2980
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326880638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.326880638
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.573753137
Short name T921
Test name
Test status
Simulation time 504524740 ps
CPU time 4.04 seconds
Started Mar 19 01:18:21 PM PDT 24
Finished Mar 19 01:18:26 PM PDT 24
Peak memory 218192 kb
Host smart-716c16a2-cc84-4642-81c3-e29357719c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573753137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.573753137
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3403097245
Short name T344
Test name
Test status
Simulation time 49786862 ps
CPU time 0.75 seconds
Started Mar 19 01:18:19 PM PDT 24
Finished Mar 19 01:18:20 PM PDT 24
Peak memory 206036 kb
Host smart-ebdcb9ea-14a6-447b-b021-44279996e50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403097245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3403097245
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1101522349
Short name T749
Test name
Test status
Simulation time 8209748246 ps
CPU time 82.79 seconds
Started Mar 19 01:18:22 PM PDT 24
Finished Mar 19 01:19:45 PM PDT 24
Peak memory 256876 kb
Host smart-0437ac0e-af8d-4293-9cfb-d84384e9dd40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101522349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1101522349
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2059612024
Short name T232
Test name
Test status
Simulation time 14323112929 ps
CPU time 146.03 seconds
Started Mar 19 01:18:21 PM PDT 24
Finished Mar 19 01:20:48 PM PDT 24
Peak memory 265036 kb
Host smart-8a6af57c-b6ef-452a-bf74-8464445d9d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059612024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2059612024
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2031741974
Short name T235
Test name
Test status
Simulation time 70439659480 ps
CPU time 465.79 seconds
Started Mar 19 01:18:22 PM PDT 24
Finished Mar 19 01:26:08 PM PDT 24
Peak memory 264112 kb
Host smart-98758d98-fc2f-4d4e-93af-d37cc77558f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031741974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2031741974
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1839004755
Short name T825
Test name
Test status
Simulation time 1344201762 ps
CPU time 9.16 seconds
Started Mar 19 01:18:22 PM PDT 24
Finished Mar 19 01:18:32 PM PDT 24
Peak memory 224028 kb
Host smart-e81310de-f450-4cba-b85e-9e78f85585ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839004755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1839004755
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3336336677
Short name T719
Test name
Test status
Simulation time 15237626557 ps
CPU time 12.81 seconds
Started Mar 19 01:18:19 PM PDT 24
Finished Mar 19 01:18:32 PM PDT 24
Peak memory 233120 kb
Host smart-7ad30f8e-e0a9-4179-828b-1389dfe79e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336336677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3336336677
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3274648221
Short name T736
Test name
Test status
Simulation time 2284437088 ps
CPU time 5.59 seconds
Started Mar 19 01:18:20 PM PDT 24
Finished Mar 19 01:18:26 PM PDT 24
Peak memory 216800 kb
Host smart-44c5824f-8ee5-41bc-ba2e-f1b2721266c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274648221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3274648221
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1561617289
Short name T546
Test name
Test status
Simulation time 552200690 ps
CPU time 5.91 seconds
Started Mar 19 01:18:21 PM PDT 24
Finished Mar 19 01:18:28 PM PDT 24
Peak memory 232804 kb
Host smart-ff937ac3-d106-4259-acfa-c8d71e0dd970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561617289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1561617289
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1763304818
Short name T933
Test name
Test status
Simulation time 431435089 ps
CPU time 4.01 seconds
Started Mar 19 01:18:21 PM PDT 24
Finished Mar 19 01:18:26 PM PDT 24
Peak memory 233236 kb
Host smart-7b75fc40-36e4-4a2b-bb98-9f70226f3f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763304818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1763304818
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1083915061
Short name T541
Test name
Test status
Simulation time 4729211253 ps
CPU time 5.91 seconds
Started Mar 19 01:18:20 PM PDT 24
Finished Mar 19 01:18:26 PM PDT 24
Peak memory 218780 kb
Host smart-bba3593f-f484-4fce-8783-44013eea9ca2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1083915061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1083915061
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1054730827
Short name T770
Test name
Test status
Simulation time 176005715536 ps
CPU time 367.88 seconds
Started Mar 19 01:18:22 PM PDT 24
Finished Mar 19 01:24:30 PM PDT 24
Peak memory 278268 kb
Host smart-90f213ba-e1ab-4f26-be76-2b1dbff106fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054730827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1054730827
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1165768877
Short name T539
Test name
Test status
Simulation time 1583278861 ps
CPU time 25.28 seconds
Started Mar 19 01:18:19 PM PDT 24
Finished Mar 19 01:18:44 PM PDT 24
Peak memory 215768 kb
Host smart-0617214d-7675-4749-9a5d-eec7920645af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165768877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1165768877
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2528553050
Short name T670
Test name
Test status
Simulation time 1640598260 ps
CPU time 3.99 seconds
Started Mar 19 01:18:22 PM PDT 24
Finished Mar 19 01:18:27 PM PDT 24
Peak memory 215772 kb
Host smart-229937f0-903a-44b6-b37d-f035077d7c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528553050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2528553050
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.571872169
Short name T959
Test name
Test status
Simulation time 329344685 ps
CPU time 2.03 seconds
Started Mar 19 01:18:23 PM PDT 24
Finished Mar 19 01:18:25 PM PDT 24
Peak memory 215500 kb
Host smart-0fd3f1aa-2785-419d-bd87-b59e4e93546e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571872169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.571872169
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.507644779
Short name T604
Test name
Test status
Simulation time 217435952 ps
CPU time 0.86 seconds
Started Mar 19 01:18:19 PM PDT 24
Finished Mar 19 01:18:20 PM PDT 24
Peak memory 205272 kb
Host smart-19a5a637-86f7-489f-a4b5-a1f33835e1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507644779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.507644779
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.3281450471
Short name T569
Test name
Test status
Simulation time 2057477478 ps
CPU time 11.15 seconds
Started Mar 19 01:18:20 PM PDT 24
Finished Mar 19 01:18:31 PM PDT 24
Peak memory 221340 kb
Host smart-87ba0f7e-27f8-4758-ac13-5ae030a6d53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281450471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3281450471
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1815964626
Short name T469
Test name
Test status
Simulation time 14543397 ps
CPU time 0.76 seconds
Started Mar 19 01:18:29 PM PDT 24
Finished Mar 19 01:18:30 PM PDT 24
Peak memory 204860 kb
Host smart-0e160cf2-73b1-403e-b669-d5e57eb69bac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815964626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1815964626
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2743163991
Short name T432
Test name
Test status
Simulation time 33891908 ps
CPU time 2.69 seconds
Started Mar 19 01:18:28 PM PDT 24
Finished Mar 19 01:18:31 PM PDT 24
Peak memory 234740 kb
Host smart-c11e27db-b78d-4a96-9b43-527767b83b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743163991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2743163991
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.4135060094
Short name T19
Test name
Test status
Simulation time 34727776 ps
CPU time 0.77 seconds
Started Mar 19 01:18:21 PM PDT 24
Finished Mar 19 01:18:22 PM PDT 24
Peak memory 205040 kb
Host smart-59836507-fcb6-4c51-9cfc-23ee3dc2c914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135060094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.4135060094
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2141751196
Short name T479
Test name
Test status
Simulation time 47667315318 ps
CPU time 42.2 seconds
Started Mar 19 01:18:31 PM PDT 24
Finished Mar 19 01:19:14 PM PDT 24
Peak memory 248720 kb
Host smart-0d7d89c2-294d-4560-91c6-4f208a50b869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141751196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2141751196
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1599901511
Short name T190
Test name
Test status
Simulation time 42598113244 ps
CPU time 377.17 seconds
Started Mar 19 01:18:28 PM PDT 24
Finished Mar 19 01:24:46 PM PDT 24
Peak memory 264484 kb
Host smart-c12005fb-6e97-4b89-bd96-9a8a1fc742f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599901511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1599901511
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.4000159716
Short name T939
Test name
Test status
Simulation time 69580519250 ps
CPU time 70.86 seconds
Started Mar 19 01:18:32 PM PDT 24
Finished Mar 19 01:19:43 PM PDT 24
Peak memory 234824 kb
Host smart-8e20a686-7cac-419a-aa5b-d2df700ff957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000159716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.4000159716
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.222252174
Short name T740
Test name
Test status
Simulation time 16634868430 ps
CPU time 34.51 seconds
Started Mar 19 01:18:28 PM PDT 24
Finished Mar 19 01:19:03 PM PDT 24
Peak memory 224116 kb
Host smart-8c3972dc-c07c-43e9-bf32-48c40239fbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222252174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.222252174
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1436704670
Short name T444
Test name
Test status
Simulation time 13567607923 ps
CPU time 10.79 seconds
Started Mar 19 01:18:21 PM PDT 24
Finished Mar 19 01:18:32 PM PDT 24
Peak memory 224140 kb
Host smart-bac53e6c-bddf-4445-a1ba-eb9fd7efce5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436704670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1436704670
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2241052761
Short name T944
Test name
Test status
Simulation time 594909471 ps
CPU time 2.5 seconds
Started Mar 19 01:18:19 PM PDT 24
Finished Mar 19 01:18:21 PM PDT 24
Peak memory 216268 kb
Host smart-1b14c207-62e3-4195-b3bd-a7a1da5bfe16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241052761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2241052761
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3071308684
Short name T422
Test name
Test status
Simulation time 2423809551 ps
CPU time 5.59 seconds
Started Mar 19 01:18:21 PM PDT 24
Finished Mar 19 01:18:26 PM PDT 24
Peak memory 233908 kb
Host smart-85f33c18-98eb-4b8a-9d4f-cdf817feaf43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071308684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3071308684
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3895995301
Short name T776
Test name
Test status
Simulation time 444994638 ps
CPU time 6.49 seconds
Started Mar 19 01:18:23 PM PDT 24
Finished Mar 19 01:18:30 PM PDT 24
Peak memory 234328 kb
Host smart-52d30bc9-9bb5-4630-8805-0c66d385861e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895995301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3895995301
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2905866332
Short name T141
Test name
Test status
Simulation time 1377518387 ps
CPU time 3.98 seconds
Started Mar 19 01:18:27 PM PDT 24
Finished Mar 19 01:18:31 PM PDT 24
Peak memory 221736 kb
Host smart-7538a77f-ac5c-414d-9c74-d883538d2717
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2905866332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2905866332
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3167645877
Short name T733
Test name
Test status
Simulation time 49120706355 ps
CPU time 265.19 seconds
Started Mar 19 01:18:29 PM PDT 24
Finished Mar 19 01:22:54 PM PDT 24
Peak memory 256700 kb
Host smart-b7a538d2-cee3-4540-b42b-a6f0d3a8a66e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167645877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3167645877
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1127074190
Short name T456
Test name
Test status
Simulation time 1694956456 ps
CPU time 8.45 seconds
Started Mar 19 01:18:23 PM PDT 24
Finished Mar 19 01:18:32 PM PDT 24
Peak memory 219152 kb
Host smart-928883aa-a574-4038-bf49-93bdf4477234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127074190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1127074190
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3574444346
Short name T726
Test name
Test status
Simulation time 4926488858 ps
CPU time 12.24 seconds
Started Mar 19 01:18:22 PM PDT 24
Finished Mar 19 01:18:35 PM PDT 24
Peak memory 215912 kb
Host smart-ee53cad9-51ce-42de-a92d-2b1884cb1c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574444346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3574444346
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1928191322
Short name T428
Test name
Test status
Simulation time 55359208 ps
CPU time 0.87 seconds
Started Mar 19 01:18:19 PM PDT 24
Finished Mar 19 01:18:20 PM PDT 24
Peak memory 206000 kb
Host smart-fd3445f9-a47e-494e-bd7c-b91c84330a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928191322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1928191322
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2418669920
Short name T434
Test name
Test status
Simulation time 340367474 ps
CPU time 0.91 seconds
Started Mar 19 01:18:22 PM PDT 24
Finished Mar 19 01:18:23 PM PDT 24
Peak memory 205308 kb
Host smart-31b7755b-0475-46e8-a103-2ae87d545afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418669920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2418669920
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.791653148
Short name T742
Test name
Test status
Simulation time 2039860559 ps
CPU time 6.07 seconds
Started Mar 19 01:18:20 PM PDT 24
Finished Mar 19 01:18:26 PM PDT 24
Peak memory 234000 kb
Host smart-9679e81d-8f05-49cb-885f-83960b51ea5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791653148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.791653148
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2698740496
Short name T671
Test name
Test status
Simulation time 23062411 ps
CPU time 0.76 seconds
Started Mar 19 01:18:39 PM PDT 24
Finished Mar 19 01:18:39 PM PDT 24
Peak memory 205200 kb
Host smart-0be0ee15-0fd7-4cfc-9c91-a9d0cd1dd209
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698740496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2698740496
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.532649916
Short name T372
Test name
Test status
Simulation time 3000136444 ps
CPU time 5.94 seconds
Started Mar 19 01:18:29 PM PDT 24
Finished Mar 19 01:18:35 PM PDT 24
Peak memory 237408 kb
Host smart-a66d6f8c-23b8-4db2-b830-eb8180a7ed65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532649916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.532649916
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2436465744
Short name T477
Test name
Test status
Simulation time 42900003 ps
CPU time 0.78 seconds
Started Mar 19 01:18:30 PM PDT 24
Finished Mar 19 01:18:32 PM PDT 24
Peak memory 205028 kb
Host smart-389aef1d-8b3f-4a21-b692-017fe3090700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436465744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2436465744
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.90565795
Short name T600
Test name
Test status
Simulation time 9924129861 ps
CPU time 33.56 seconds
Started Mar 19 01:18:29 PM PDT 24
Finished Mar 19 01:19:03 PM PDT 24
Peak memory 240448 kb
Host smart-87d6f9df-6452-4720-8ee8-a9d755e8b972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90565795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.90565795
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3864090939
Short name T875
Test name
Test status
Simulation time 122485760382 ps
CPU time 454.42 seconds
Started Mar 19 01:18:31 PM PDT 24
Finished Mar 19 01:26:06 PM PDT 24
Peak memory 266504 kb
Host smart-68710535-c70b-4c12-96bd-d8458763d327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864090939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3864090939
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2345616978
Short name T489
Test name
Test status
Simulation time 1981594513 ps
CPU time 17.56 seconds
Started Mar 19 01:18:29 PM PDT 24
Finished Mar 19 01:18:47 PM PDT 24
Peak memory 248712 kb
Host smart-7b4e213a-ec79-419a-a176-557f9e8bfd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345616978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2345616978
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2845591293
Short name T728
Test name
Test status
Simulation time 4440824021 ps
CPU time 14.27 seconds
Started Mar 19 01:18:28 PM PDT 24
Finished Mar 19 01:18:43 PM PDT 24
Peak memory 233232 kb
Host smart-d4cbfcca-0c7c-45bf-a387-3e55969286b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845591293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2845591293
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1035782061
Short name T924
Test name
Test status
Simulation time 1082899004 ps
CPU time 7.74 seconds
Started Mar 19 01:18:38 PM PDT 24
Finished Mar 19 01:18:46 PM PDT 24
Peak memory 248604 kb
Host smart-b2d51d29-6bcb-4dab-8ad3-7a1263b554a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035782061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1035782061
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.4123214731
Short name T913
Test name
Test status
Simulation time 43925153631 ps
CPU time 22.79 seconds
Started Mar 19 01:18:37 PM PDT 24
Finished Mar 19 01:19:00 PM PDT 24
Peak memory 217048 kb
Host smart-02dcea7b-94e7-4ab1-85c0-51cdb9d64038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123214731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.4123214731
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2474536607
Short name T382
Test name
Test status
Simulation time 25033128489 ps
CPU time 29.69 seconds
Started Mar 19 01:18:28 PM PDT 24
Finished Mar 19 01:18:58 PM PDT 24
Peak memory 232236 kb
Host smart-3e04b9aa-6ef2-4266-afb6-48c9191455ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474536607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2474536607
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.385837157
Short name T885
Test name
Test status
Simulation time 126101483 ps
CPU time 3.3 seconds
Started Mar 19 01:18:29 PM PDT 24
Finished Mar 19 01:18:32 PM PDT 24
Peak memory 219976 kb
Host smart-80e2892d-dddb-43b2-ab65-ac5bb71e1a82
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=385837157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.385837157
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2790096217
Short name T157
Test name
Test status
Simulation time 100518518 ps
CPU time 1.01 seconds
Started Mar 19 01:18:35 PM PDT 24
Finished Mar 19 01:18:36 PM PDT 24
Peak memory 206232 kb
Host smart-f93b29cf-c6d3-456a-a201-448b61da5536
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790096217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2790096217
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1100081376
Short name T357
Test name
Test status
Simulation time 22756152588 ps
CPU time 34.26 seconds
Started Mar 19 01:18:38 PM PDT 24
Finished Mar 19 01:19:12 PM PDT 24
Peak memory 215504 kb
Host smart-c3687e76-cf06-4d5b-a6ac-f741b17837b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100081376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1100081376
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1230464278
Short name T644
Test name
Test status
Simulation time 8742538468 ps
CPU time 5.92 seconds
Started Mar 19 01:18:37 PM PDT 24
Finished Mar 19 01:18:43 PM PDT 24
Peak memory 215552 kb
Host smart-736eaacf-a4b1-43fd-a18a-9d52c1d8653c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230464278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1230464278
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3954800284
Short name T695
Test name
Test status
Simulation time 87590320 ps
CPU time 1.28 seconds
Started Mar 19 01:18:37 PM PDT 24
Finished Mar 19 01:18:38 PM PDT 24
Peak memory 215464 kb
Host smart-8dd121ad-8ccb-49af-ab69-da265ff07674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954800284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3954800284
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1810979969
Short name T81
Test name
Test status
Simulation time 68622741 ps
CPU time 0.72 seconds
Started Mar 19 01:18:37 PM PDT 24
Finished Mar 19 01:18:39 PM PDT 24
Peak memory 204988 kb
Host smart-acc71eaf-3ae1-486b-a364-da5b147ad53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810979969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1810979969
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3458336416
Short name T724
Test name
Test status
Simulation time 427694818 ps
CPU time 2.22 seconds
Started Mar 19 01:18:32 PM PDT 24
Finished Mar 19 01:18:35 PM PDT 24
Peak memory 215856 kb
Host smart-c2c8d96c-e4fe-4ce4-8f7f-aa16882d6ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458336416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3458336416
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.398813299
Short name T965
Test name
Test status
Simulation time 26339980 ps
CPU time 0.72 seconds
Started Mar 19 01:18:44 PM PDT 24
Finished Mar 19 01:18:45 PM PDT 24
Peak memory 204200 kb
Host smart-fa9eeefe-4f6d-4845-81f6-ad0c6adfa804
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398813299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.398813299
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3976502044
Short name T714
Test name
Test status
Simulation time 157111679 ps
CPU time 3.58 seconds
Started Mar 19 01:18:38 PM PDT 24
Finished Mar 19 01:18:42 PM PDT 24
Peak memory 218048 kb
Host smart-5493ab45-3a9b-4cdd-88f2-ec2e3cb5dc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976502044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3976502044
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2101090833
Short name T713
Test name
Test status
Simulation time 80081040 ps
CPU time 0.83 seconds
Started Mar 19 01:18:38 PM PDT 24
Finished Mar 19 01:18:39 PM PDT 24
Peak memory 206304 kb
Host smart-ba6e3b8b-b10d-4d5f-ae3a-ba08c1516934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101090833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2101090833
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2963110874
Short name T174
Test name
Test status
Simulation time 28536821769 ps
CPU time 95.43 seconds
Started Mar 19 01:18:37 PM PDT 24
Finished Mar 19 01:20:13 PM PDT 24
Peak memory 269572 kb
Host smart-e5f655af-0d46-4ee0-ac27-19b30189f23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963110874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2963110874
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.933284971
Short name T955
Test name
Test status
Simulation time 122954405427 ps
CPU time 220.22 seconds
Started Mar 19 01:18:39 PM PDT 24
Finished Mar 19 01:22:19 PM PDT 24
Peak memory 248764 kb
Host smart-c0934ef8-3e22-410c-a129-2787a76448ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933284971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.933284971
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1679136856
Short name T791
Test name
Test status
Simulation time 32527388843 ps
CPU time 108.63 seconds
Started Mar 19 01:18:39 PM PDT 24
Finished Mar 19 01:20:28 PM PDT 24
Peak memory 255292 kb
Host smart-1fdf0ec8-8a4a-4bdc-aae1-5cebcaf9e516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679136856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1679136856
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3384378341
Short name T883
Test name
Test status
Simulation time 4872635678 ps
CPU time 17.86 seconds
Started Mar 19 01:18:39 PM PDT 24
Finished Mar 19 01:18:57 PM PDT 24
Peak memory 248488 kb
Host smart-a3423e16-f038-4840-a2af-ec24d90b40f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384378341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3384378341
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2374596890
Short name T294
Test name
Test status
Simulation time 286283202 ps
CPU time 2.97 seconds
Started Mar 19 01:18:35 PM PDT 24
Finished Mar 19 01:18:38 PM PDT 24
Peak memory 218076 kb
Host smart-b7021089-556f-4872-9362-715e3a4b64b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374596890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2374596890
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2020503316
Short name T949
Test name
Test status
Simulation time 1174390397 ps
CPU time 2.93 seconds
Started Mar 19 01:18:38 PM PDT 24
Finished Mar 19 01:18:41 PM PDT 24
Peak memory 218016 kb
Host smart-1ee22242-8147-4d84-82e5-6219786c8945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020503316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2020503316
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1707057573
Short name T207
Test name
Test status
Simulation time 50757124070 ps
CPU time 17.12 seconds
Started Mar 19 01:18:37 PM PDT 24
Finished Mar 19 01:18:55 PM PDT 24
Peak memory 218148 kb
Host smart-b99bd05a-cb66-4611-83d7-52aba420c862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707057573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1707057573
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2945715339
Short name T628
Test name
Test status
Simulation time 15482122809 ps
CPU time 18.2 seconds
Started Mar 19 01:18:36 PM PDT 24
Finished Mar 19 01:18:55 PM PDT 24
Peak memory 233128 kb
Host smart-d2fe0f46-5ded-4d09-a1f1-18cd6d02533c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945715339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2945715339
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3720982925
Short name T739
Test name
Test status
Simulation time 3770687869 ps
CPU time 5.32 seconds
Started Mar 19 01:18:39 PM PDT 24
Finished Mar 19 01:18:45 PM PDT 24
Peak memory 222180 kb
Host smart-5c9aac05-48de-48aa-8609-d30a0c8c8194
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3720982925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3720982925
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3497131534
Short name T68
Test name
Test status
Simulation time 188141291 ps
CPU time 0.97 seconds
Started Mar 19 01:18:36 PM PDT 24
Finished Mar 19 01:18:37 PM PDT 24
Peak memory 206020 kb
Host smart-5b021730-a522-4df4-90d6-8fa31b66bc92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497131534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3497131534
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3123762570
Short name T866
Test name
Test status
Simulation time 29111698505 ps
CPU time 80.07 seconds
Started Mar 19 01:18:38 PM PDT 24
Finished Mar 19 01:19:58 PM PDT 24
Peak memory 215840 kb
Host smart-9f897111-ae64-4432-814e-e696a2d7731e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123762570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3123762570
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3272133610
Short name T755
Test name
Test status
Simulation time 13048538152 ps
CPU time 8.95 seconds
Started Mar 19 01:18:38 PM PDT 24
Finished Mar 19 01:18:47 PM PDT 24
Peak memory 215856 kb
Host smart-feaf603f-0f02-4497-ad9a-14310d0a02a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272133610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3272133610
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1241023891
Short name T321
Test name
Test status
Simulation time 51981077 ps
CPU time 1.87 seconds
Started Mar 19 01:18:35 PM PDT 24
Finished Mar 19 01:18:37 PM PDT 24
Peak memory 215760 kb
Host smart-94455abf-0b81-4065-a349-7836d1bc9370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241023891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1241023891
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3728700283
Short name T317
Test name
Test status
Simulation time 117744020 ps
CPU time 0.85 seconds
Started Mar 19 01:18:36 PM PDT 24
Finished Mar 19 01:18:37 PM PDT 24
Peak memory 205288 kb
Host smart-4b2271f6-ddc7-430f-b309-441e19e71ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728700283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3728700283
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1599795378
Short name T209
Test name
Test status
Simulation time 636814209 ps
CPU time 5.65 seconds
Started Mar 19 01:18:39 PM PDT 24
Finished Mar 19 01:18:45 PM PDT 24
Peak memory 233108 kb
Host smart-fc25bdeb-fe80-4115-b0a7-e827b60868ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599795378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1599795378
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1551795390
Short name T659
Test name
Test status
Simulation time 84115240 ps
CPU time 0.7 seconds
Started Mar 19 01:18:53 PM PDT 24
Finished Mar 19 01:18:54 PM PDT 24
Peak memory 205212 kb
Host smart-eb15bf13-cb48-44b4-b647-b21f35dc8f88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551795390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1551795390
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2177044146
Short name T339
Test name
Test status
Simulation time 738634464 ps
CPU time 4.81 seconds
Started Mar 19 01:18:44 PM PDT 24
Finished Mar 19 01:18:49 PM PDT 24
Peak memory 234260 kb
Host smart-48298d43-3cdc-4d2c-b506-44544532e376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177044146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2177044146
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2602969561
Short name T822
Test name
Test status
Simulation time 18764291 ps
CPU time 0.71 seconds
Started Mar 19 01:18:44 PM PDT 24
Finished Mar 19 01:18:45 PM PDT 24
Peak memory 205020 kb
Host smart-35d54fb9-94ec-474a-870d-547f82c6fcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602969561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2602969561
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.723881706
Short name T663
Test name
Test status
Simulation time 26988740601 ps
CPU time 30.29 seconds
Started Mar 19 01:18:43 PM PDT 24
Finished Mar 19 01:19:14 PM PDT 24
Peak memory 237816 kb
Host smart-a3c38de0-ebb3-4aa7-af9d-87611bf9b82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723881706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.723881706
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.4264886838
Short name T228
Test name
Test status
Simulation time 22308472471 ps
CPU time 228.61 seconds
Started Mar 19 01:18:44 PM PDT 24
Finished Mar 19 01:22:33 PM PDT 24
Peak memory 255524 kb
Host smart-1f53b0ed-ad7f-4749-87ee-4da96d3d33ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264886838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.4264886838
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.26667595
Short name T491
Test name
Test status
Simulation time 128185479318 ps
CPU time 273.54 seconds
Started Mar 19 01:18:43 PM PDT 24
Finished Mar 19 01:23:17 PM PDT 24
Peak memory 249868 kb
Host smart-e6c34839-173c-41db-b20a-88cfe92c7faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26667595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle.26667595
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1347714391
Short name T651
Test name
Test status
Simulation time 3583095364 ps
CPU time 11.89 seconds
Started Mar 19 01:18:47 PM PDT 24
Finished Mar 19 01:18:59 PM PDT 24
Peak memory 247224 kb
Host smart-5debdbf9-cb4f-465e-9c1c-9e6fe34fcb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347714391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1347714391
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1358808176
Short name T318
Test name
Test status
Simulation time 3853241757 ps
CPU time 6.22 seconds
Started Mar 19 01:18:45 PM PDT 24
Finished Mar 19 01:18:51 PM PDT 24
Peak memory 233172 kb
Host smart-a0d25d27-c57f-42f5-9483-f2a5a7983334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358808176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1358808176
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2750816822
Short name T598
Test name
Test status
Simulation time 37365409239 ps
CPU time 34.57 seconds
Started Mar 19 01:18:44 PM PDT 24
Finished Mar 19 01:19:19 PM PDT 24
Peak memory 247512 kb
Host smart-fcd9427a-a9b9-47b5-ad8e-b6bc67328112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750816822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2750816822
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.738181569
Short name T765
Test name
Test status
Simulation time 246410816 ps
CPU time 2.99 seconds
Started Mar 19 01:18:48 PM PDT 24
Finished Mar 19 01:18:51 PM PDT 24
Peak memory 233136 kb
Host smart-ffac52bd-afa0-460f-83b0-53fc9d5cb565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738181569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.738181569
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2022678065
Short name T331
Test name
Test status
Simulation time 9795452095 ps
CPU time 11.02 seconds
Started Mar 19 01:18:45 PM PDT 24
Finished Mar 19 01:18:56 PM PDT 24
Peak memory 218020 kb
Host smart-d629e68d-2e84-4458-be5c-216bf25347cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022678065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2022678065
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.274732675
Short name T542
Test name
Test status
Simulation time 12050691426 ps
CPU time 5.81 seconds
Started Mar 19 01:18:45 PM PDT 24
Finished Mar 19 01:18:51 PM PDT 24
Peak memory 222440 kb
Host smart-dcd31de6-fccc-45d5-9532-d5130b4e4c41
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=274732675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.274732675
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.792542947
Short name T667
Test name
Test status
Simulation time 178806684667 ps
CPU time 666.95 seconds
Started Mar 19 01:18:43 PM PDT 24
Finished Mar 19 01:29:50 PM PDT 24
Peak memory 255872 kb
Host smart-8155b246-e890-4749-a21f-85ade5675fcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792542947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.792542947
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1920961774
Short name T629
Test name
Test status
Simulation time 20461278607 ps
CPU time 20.04 seconds
Started Mar 19 01:18:44 PM PDT 24
Finished Mar 19 01:19:05 PM PDT 24
Peak memory 215844 kb
Host smart-0e4b51d0-f761-43d9-85cf-4189c992fb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920961774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1920961774
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3904412134
Short name T767
Test name
Test status
Simulation time 29352208 ps
CPU time 1.55 seconds
Started Mar 19 01:18:43 PM PDT 24
Finished Mar 19 01:18:45 PM PDT 24
Peak memory 215772 kb
Host smart-6b145ba1-7f38-40f8-8404-87555dbc6178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904412134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3904412134
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3610843258
Short name T100
Test name
Test status
Simulation time 143691892 ps
CPU time 1.15 seconds
Started Mar 19 01:18:44 PM PDT 24
Finished Mar 19 01:18:46 PM PDT 24
Peak memory 206320 kb
Host smart-cb16e433-de7f-4e09-9a53-48df41eb9c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610843258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3610843258
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3140361443
Short name T560
Test name
Test status
Simulation time 15227140719 ps
CPU time 46.49 seconds
Started Mar 19 01:18:45 PM PDT 24
Finished Mar 19 01:19:32 PM PDT 24
Peak memory 248608 kb
Host smart-503c0171-4a21-4b7c-b0a1-d33fa83e35fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140361443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3140361443
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1803332669
Short name T591
Test name
Test status
Simulation time 26287192 ps
CPU time 0.71 seconds
Started Mar 19 01:13:37 PM PDT 24
Finished Mar 19 01:13:39 PM PDT 24
Peak memory 205208 kb
Host smart-42e8cc4b-17a7-4f4f-876c-159cba332875
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803332669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
803332669
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3599432830
Short name T342
Test name
Test status
Simulation time 269514009 ps
CPU time 4.45 seconds
Started Mar 19 01:13:39 PM PDT 24
Finished Mar 19 01:13:44 PM PDT 24
Peak memory 224048 kb
Host smart-b7ed42bb-c345-4783-aa97-e4492cd8ba0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599432830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3599432830
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2456178190
Short name T634
Test name
Test status
Simulation time 15290637 ps
CPU time 0.79 seconds
Started Mar 19 01:13:30 PM PDT 24
Finished Mar 19 01:13:30 PM PDT 24
Peak memory 205020 kb
Host smart-eec6ac32-7d09-4c6f-a52f-0fee013231bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456178190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2456178190
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.2540470156
Short name T754
Test name
Test status
Simulation time 50644014535 ps
CPU time 71.83 seconds
Started Mar 19 01:13:37 PM PDT 24
Finished Mar 19 01:14:49 PM PDT 24
Peak memory 265108 kb
Host smart-7673403d-9517-499f-8b12-1a52c4890786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540470156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2540470156
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2673290253
Short name T49
Test name
Test status
Simulation time 3481689126 ps
CPU time 35.25 seconds
Started Mar 19 01:13:37 PM PDT 24
Finished Mar 19 01:14:12 PM PDT 24
Peak memory 233668 kb
Host smart-2fc28a55-6245-4ea3-a37d-0c1820021da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673290253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2673290253
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3401546561
Short name T729
Test name
Test status
Simulation time 62419763760 ps
CPU time 159.61 seconds
Started Mar 19 01:13:38 PM PDT 24
Finished Mar 19 01:16:17 PM PDT 24
Peak memory 265220 kb
Host smart-819ffe27-3d21-4a9f-af43-f439655f5be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401546561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3401546561
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.366580316
Short name T82
Test name
Test status
Simulation time 730863680 ps
CPU time 11.99 seconds
Started Mar 19 01:13:37 PM PDT 24
Finished Mar 19 01:13:50 PM PDT 24
Peak memory 248148 kb
Host smart-bf95c8a8-906e-4344-bfc1-66045b4a6168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366580316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.366580316
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.519194139
Short name T466
Test name
Test status
Simulation time 6850720749 ps
CPU time 4.94 seconds
Started Mar 19 01:13:36 PM PDT 24
Finished Mar 19 01:13:41 PM PDT 24
Peak memory 220116 kb
Host smart-3b1541a1-2289-478d-ae3d-39212d9837d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519194139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.519194139
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.4046357666
Short name T191
Test name
Test status
Simulation time 1019426808 ps
CPU time 4.09 seconds
Started Mar 19 01:13:37 PM PDT 24
Finished Mar 19 01:13:42 PM PDT 24
Peak memory 218308 kb
Host smart-48ac95cf-b52b-4b32-973d-8405b1f189f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046357666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.4046357666
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3615139618
Short name T377
Test name
Test status
Simulation time 53128704242 ps
CPU time 41.13 seconds
Started Mar 19 01:13:36 PM PDT 24
Finished Mar 19 01:14:17 PM PDT 24
Peak memory 240444 kb
Host smart-4ddaf607-12f5-4ee1-873c-7bb98bb23901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615139618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3615139618
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2499218169
Short name T165
Test name
Test status
Simulation time 14443040556 ps
CPU time 15.25 seconds
Started Mar 19 01:13:36 PM PDT 24
Finished Mar 19 01:13:51 PM PDT 24
Peak memory 239648 kb
Host smart-a431ea40-8a13-4580-8df7-8255092f6ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499218169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2499218169
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.3963423661
Short name T419
Test name
Test status
Simulation time 22427733 ps
CPU time 0.74 seconds
Started Mar 19 01:13:37 PM PDT 24
Finished Mar 19 01:13:38 PM PDT 24
Peak memory 215816 kb
Host smart-b711eb51-1942-4ead-b4a8-3508c21fdc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963423661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.3963423661
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.704161765
Short name T492
Test name
Test status
Simulation time 24787826358 ps
CPU time 7.16 seconds
Started Mar 19 01:13:37 PM PDT 24
Finished Mar 19 01:13:44 PM PDT 24
Peak memory 222480 kb
Host smart-266ca130-467b-4cb1-a767-f449cb46361d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=704161765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.704161765
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.352952498
Short name T76
Test name
Test status
Simulation time 111519640 ps
CPU time 1.06 seconds
Started Mar 19 01:13:38 PM PDT 24
Finished Mar 19 01:13:40 PM PDT 24
Peak memory 234304 kb
Host smart-0052449a-bfa3-4a50-9bb1-f9580605406c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352952498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.352952498
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3434618474
Short name T679
Test name
Test status
Simulation time 68985868 ps
CPU time 1.19 seconds
Started Mar 19 01:13:39 PM PDT 24
Finished Mar 19 01:13:41 PM PDT 24
Peak memory 206632 kb
Host smart-c208d96c-6dfc-4f67-aa49-20b9bdaff500
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434618474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3434618474
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.399653746
Short name T532
Test name
Test status
Simulation time 5958999563 ps
CPU time 23.63 seconds
Started Mar 19 01:13:36 PM PDT 24
Finished Mar 19 01:14:01 PM PDT 24
Peak memory 215900 kb
Host smart-61355cce-5942-438f-9e9c-ab9720022496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399653746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.399653746
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3976987947
Short name T783
Test name
Test status
Simulation time 1967207671 ps
CPU time 3.51 seconds
Started Mar 19 01:13:36 PM PDT 24
Finished Mar 19 01:13:40 PM PDT 24
Peak memory 215792 kb
Host smart-cdfb171c-6dd8-450a-b9cd-cca2c307acce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976987947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3976987947
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1690317611
Short name T494
Test name
Test status
Simulation time 131902174 ps
CPU time 2.58 seconds
Started Mar 19 01:13:41 PM PDT 24
Finished Mar 19 01:13:44 PM PDT 24
Peak memory 215768 kb
Host smart-a95ce256-965c-478d-9513-0716079322aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690317611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1690317611
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.943002466
Short name T948
Test name
Test status
Simulation time 28215209 ps
CPU time 0.77 seconds
Started Mar 19 01:13:36 PM PDT 24
Finished Mar 19 01:13:38 PM PDT 24
Peak memory 205188 kb
Host smart-70709bb0-fb58-44a8-bead-1b8867641dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943002466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.943002466
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.1078929565
Short name T778
Test name
Test status
Simulation time 1228305492 ps
CPU time 4.35 seconds
Started Mar 19 01:13:37 PM PDT 24
Finished Mar 19 01:13:42 PM PDT 24
Peak memory 216452 kb
Host smart-111981d7-af75-4fb4-8a47-4cf734cda9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078929565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1078929565
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1272219007
Short name T768
Test name
Test status
Simulation time 38441958 ps
CPU time 0.72 seconds
Started Mar 19 01:19:05 PM PDT 24
Finished Mar 19 01:19:06 PM PDT 24
Peak memory 204856 kb
Host smart-a52617d1-a747-4ccb-aef2-eb1fedad460b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272219007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1272219007
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1289009301
Short name T641
Test name
Test status
Simulation time 736821013 ps
CPU time 3.23 seconds
Started Mar 19 01:18:51 PM PDT 24
Finished Mar 19 01:18:54 PM PDT 24
Peak memory 233776 kb
Host smart-e5dd6a60-a579-4af6-bcc1-cce1fd49203d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289009301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1289009301
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.4053490771
Short name T322
Test name
Test status
Simulation time 30566267 ps
CPU time 0.79 seconds
Started Mar 19 01:18:54 PM PDT 24
Finished Mar 19 01:18:55 PM PDT 24
Peak memory 205996 kb
Host smart-845dcd1d-ea35-4a5a-801b-2f7baed2f9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053490771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.4053490771
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3510635352
Short name T7
Test name
Test status
Simulation time 54264993458 ps
CPU time 138.9 seconds
Started Mar 19 01:18:52 PM PDT 24
Finished Mar 19 01:21:11 PM PDT 24
Peak memory 240492 kb
Host smart-93940987-b340-413c-ba23-fe12f95ef4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510635352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3510635352
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2878155435
Short name T543
Test name
Test status
Simulation time 2580912910 ps
CPU time 32.63 seconds
Started Mar 19 01:18:53 PM PDT 24
Finished Mar 19 01:19:26 PM PDT 24
Peak memory 237520 kb
Host smart-4c30940c-c8fd-4b0c-aa6a-48f4bb460683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878155435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2878155435
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3291769243
Short name T712
Test name
Test status
Simulation time 22418880670 ps
CPU time 170.47 seconds
Started Mar 19 01:18:58 PM PDT 24
Finished Mar 19 01:21:49 PM PDT 24
Peak memory 248748 kb
Host smart-1e5b8e72-af33-4fcd-aade-20e3b3b6d075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291769243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3291769243
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2729453944
Short name T703
Test name
Test status
Simulation time 1115619304 ps
CPU time 11.07 seconds
Started Mar 19 01:18:54 PM PDT 24
Finished Mar 19 01:19:06 PM PDT 24
Peak memory 240388 kb
Host smart-436bb9fb-8776-49f1-adfd-4c94fe3d281e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729453944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2729453944
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3980962608
Short name T734
Test name
Test status
Simulation time 252173665 ps
CPU time 3.72 seconds
Started Mar 19 01:18:53 PM PDT 24
Finished Mar 19 01:18:57 PM PDT 24
Peak memory 217416 kb
Host smart-1edddffa-db7b-47d1-bcda-bcf6e9669635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980962608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3980962608
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1739361400
Short name T694
Test name
Test status
Simulation time 36654250 ps
CPU time 2.46 seconds
Started Mar 19 01:18:52 PM PDT 24
Finished Mar 19 01:18:54 PM PDT 24
Peak memory 223984 kb
Host smart-eaf70525-b6dc-482d-9660-ccb835d8b676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739361400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1739361400
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2198607662
Short name T769
Test name
Test status
Simulation time 30854644352 ps
CPU time 24.75 seconds
Started Mar 19 01:18:52 PM PDT 24
Finished Mar 19 01:19:18 PM PDT 24
Peak memory 226740 kb
Host smart-0f79b21d-d3f7-46b2-b986-4c942f742eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198607662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2198607662
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2233649473
Short name T643
Test name
Test status
Simulation time 1785368022 ps
CPU time 9.06 seconds
Started Mar 19 01:18:51 PM PDT 24
Finished Mar 19 01:19:01 PM PDT 24
Peak memory 218068 kb
Host smart-c9966673-ac99-4b0e-8511-c7672658c4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233649473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2233649473
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1968463953
Short name T636
Test name
Test status
Simulation time 1559693290 ps
CPU time 3.63 seconds
Started Mar 19 01:18:51 PM PDT 24
Finished Mar 19 01:18:55 PM PDT 24
Peak memory 222456 kb
Host smart-de248dd6-9bdf-4b77-b809-d56913a1e1be
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1968463953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1968463953
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3833294290
Short name T219
Test name
Test status
Simulation time 27449586380 ps
CPU time 143.91 seconds
Started Mar 19 01:19:01 PM PDT 24
Finished Mar 19 01:21:26 PM PDT 24
Peak memory 264864 kb
Host smart-fbb0611e-1104-4647-a0b6-a4a1a80f86c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833294290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3833294290
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.673646721
Short name T41
Test name
Test status
Simulation time 7627591704 ps
CPU time 22.05 seconds
Started Mar 19 01:18:52 PM PDT 24
Finished Mar 19 01:19:14 PM PDT 24
Peak memory 215932 kb
Host smart-e00148e8-b070-429e-8a63-34958b88cfc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673646721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.673646721
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2661141456
Short name T281
Test name
Test status
Simulation time 4509738781 ps
CPU time 8.55 seconds
Started Mar 19 01:18:51 PM PDT 24
Finished Mar 19 01:19:00 PM PDT 24
Peak memory 215892 kb
Host smart-a77911c8-b9eb-48be-904e-aaaead3fd95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661141456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2661141456
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3939845895
Short name T18
Test name
Test status
Simulation time 179391987 ps
CPU time 2.67 seconds
Started Mar 19 01:18:54 PM PDT 24
Finished Mar 19 01:18:57 PM PDT 24
Peak memory 215868 kb
Host smart-8a8227fd-3e61-461f-a264-6d15d5be1f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939845895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3939845895
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.542479650
Short name T681
Test name
Test status
Simulation time 198265562 ps
CPU time 0.79 seconds
Started Mar 19 01:18:53 PM PDT 24
Finished Mar 19 01:18:54 PM PDT 24
Peak memory 205348 kb
Host smart-6b87cfb4-d924-42ed-895b-0fcfb2a2d6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542479650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.542479650
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3247364258
Short name T646
Test name
Test status
Simulation time 127452273 ps
CPU time 2.36 seconds
Started Mar 19 01:18:53 PM PDT 24
Finished Mar 19 01:18:56 PM PDT 24
Peak memory 232232 kb
Host smart-b746999b-ed74-4fb9-bf1c-ede94bbf1730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247364258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3247364258
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3593624818
Short name T328
Test name
Test status
Simulation time 15064704 ps
CPU time 0.73 seconds
Started Mar 19 01:19:00 PM PDT 24
Finished Mar 19 01:19:01 PM PDT 24
Peak memory 204900 kb
Host smart-7c789758-1d45-406f-bbd3-c2ca2d3ec161
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593624818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3593624818
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3427485748
Short name T498
Test name
Test status
Simulation time 974944900 ps
CPU time 2.89 seconds
Started Mar 19 01:19:01 PM PDT 24
Finished Mar 19 01:19:04 PM PDT 24
Peak memory 216872 kb
Host smart-befc87ae-3282-4098-8da9-cb8346518ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427485748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3427485748
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3531236783
Short name T510
Test name
Test status
Simulation time 53220052 ps
CPU time 0.72 seconds
Started Mar 19 01:19:03 PM PDT 24
Finished Mar 19 01:19:04 PM PDT 24
Peak memory 205312 kb
Host smart-4f4d2ba4-1b18-4c41-ae99-43a443109d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531236783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3531236783
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.26904583
Short name T809
Test name
Test status
Simulation time 99417707466 ps
CPU time 156.4 seconds
Started Mar 19 01:19:01 PM PDT 24
Finished Mar 19 01:21:37 PM PDT 24
Peak memory 269280 kb
Host smart-03f1cd62-c41b-4e87-87d9-da209966c527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26904583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.26904583
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3864788751
Short name T349
Test name
Test status
Simulation time 9001823761 ps
CPU time 75.26 seconds
Started Mar 19 01:18:58 PM PDT 24
Finished Mar 19 01:20:14 PM PDT 24
Peak memory 253868 kb
Host smart-f32585dc-0ba9-4725-a085-3768528742e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864788751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3864788751
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3582371321
Short name T872
Test name
Test status
Simulation time 15519167673 ps
CPU time 64.44 seconds
Started Mar 19 01:19:00 PM PDT 24
Finished Mar 19 01:20:05 PM PDT 24
Peak memory 254944 kb
Host smart-a95dbd64-46b4-475d-952a-67892db65c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582371321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3582371321
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3701794116
Short name T806
Test name
Test status
Simulation time 1955040664 ps
CPU time 6.65 seconds
Started Mar 19 01:18:59 PM PDT 24
Finished Mar 19 01:19:06 PM PDT 24
Peak memory 221128 kb
Host smart-150ecf2c-107b-4cfd-85e3-bd60d6377f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701794116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3701794116
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3457973102
Short name T414
Test name
Test status
Simulation time 2021747631 ps
CPU time 4.89 seconds
Started Mar 19 01:19:00 PM PDT 24
Finished Mar 19 01:19:06 PM PDT 24
Peak memory 234316 kb
Host smart-09c574ab-45ca-48ea-af35-79e2add41ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457973102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3457973102
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.306495279
Short name T654
Test name
Test status
Simulation time 9061103941 ps
CPU time 24.73 seconds
Started Mar 19 01:19:00 PM PDT 24
Finished Mar 19 01:19:25 PM PDT 24
Peak memory 217008 kb
Host smart-a3836bd3-c1c4-425b-ac79-b995c8bf013f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306495279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.306495279
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1514860323
Short name T505
Test name
Test status
Simulation time 2023183384 ps
CPU time 5.79 seconds
Started Mar 19 01:19:02 PM PDT 24
Finished Mar 19 01:19:08 PM PDT 24
Peak memory 226552 kb
Host smart-715737e4-9c24-46c8-9a77-14c76a37c70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514860323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1514860323
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.4197332701
Short name T581
Test name
Test status
Simulation time 1082983575 ps
CPU time 5.45 seconds
Started Mar 19 01:19:01 PM PDT 24
Finished Mar 19 01:19:06 PM PDT 24
Peak memory 219616 kb
Host smart-c9499b64-e4d2-40f3-b02a-bfaa20f7d62c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4197332701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.4197332701
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.211696404
Short name T536
Test name
Test status
Simulation time 73591832620 ps
CPU time 54.65 seconds
Started Mar 19 01:19:00 PM PDT 24
Finished Mar 19 01:19:55 PM PDT 24
Peak memory 240208 kb
Host smart-87636535-0b81-4f61-9661-ba31c08a799f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211696404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.211696404
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2428977133
Short name T676
Test name
Test status
Simulation time 20245548864 ps
CPU time 31.53 seconds
Started Mar 19 01:19:04 PM PDT 24
Finished Mar 19 01:19:36 PM PDT 24
Peak memory 215868 kb
Host smart-7a24d00b-6a4e-4dde-a38e-5387c51d589c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428977133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2428977133
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2951664750
Short name T708
Test name
Test status
Simulation time 1784187171 ps
CPU time 4.79 seconds
Started Mar 19 01:18:59 PM PDT 24
Finished Mar 19 01:19:04 PM PDT 24
Peak memory 215716 kb
Host smart-56287331-e311-451e-9a88-027c969f4519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951664750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2951664750
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.580282790
Short name T420
Test name
Test status
Simulation time 50755490 ps
CPU time 0.77 seconds
Started Mar 19 01:18:59 PM PDT 24
Finished Mar 19 01:19:00 PM PDT 24
Peak memory 205896 kb
Host smart-8605959b-b909-4fd8-94b0-984b21958ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580282790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.580282790
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.388318850
Short name T306
Test name
Test status
Simulation time 56127375 ps
CPU time 0.76 seconds
Started Mar 19 01:18:58 PM PDT 24
Finished Mar 19 01:19:00 PM PDT 24
Peak memory 205184 kb
Host smart-702cd827-3e4d-4ec9-a3b0-2bf3ec9e562d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388318850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.388318850
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1061929952
Short name T211
Test name
Test status
Simulation time 13241113677 ps
CPU time 20.49 seconds
Started Mar 19 01:19:00 PM PDT 24
Finished Mar 19 01:19:21 PM PDT 24
Peak memory 235960 kb
Host smart-85ee02f4-ea19-4456-a165-ad94254d1368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061929952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1061929952
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2598364941
Short name T63
Test name
Test status
Simulation time 12569810 ps
CPU time 0.72 seconds
Started Mar 19 01:19:08 PM PDT 24
Finished Mar 19 01:19:09 PM PDT 24
Peak memory 204776 kb
Host smart-12a3858f-c53c-4ff1-9739-d900be35b949
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598364941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2598364941
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.680484346
Short name T621
Test name
Test status
Simulation time 5473949267 ps
CPU time 7.08 seconds
Started Mar 19 01:19:04 PM PDT 24
Finished Mar 19 01:19:12 PM PDT 24
Peak memory 233228 kb
Host smart-9c3fa55e-957d-4a8e-817c-677a9d43ee6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680484346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.680484346
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1923359892
Short name T579
Test name
Test status
Simulation time 14113766 ps
CPU time 0.79 seconds
Started Mar 19 01:19:02 PM PDT 24
Finished Mar 19 01:19:03 PM PDT 24
Peak memory 206244 kb
Host smart-efe8aa88-91ce-4529-9506-5fc9cd63fa54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923359892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1923359892
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1084293365
Short name T379
Test name
Test status
Simulation time 56878085973 ps
CPU time 157.67 seconds
Started Mar 19 01:19:07 PM PDT 24
Finished Mar 19 01:21:45 PM PDT 24
Peak memory 250288 kb
Host smart-649265a0-dbd8-4402-8c38-b0ea1efedffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084293365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1084293365
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1074366026
Short name T51
Test name
Test status
Simulation time 49173863177 ps
CPU time 341.06 seconds
Started Mar 19 01:19:11 PM PDT 24
Finished Mar 19 01:24:52 PM PDT 24
Peak memory 263848 kb
Host smart-6640867b-418c-41d1-a4f8-97e586d7154c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074366026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1074366026
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2918698979
Short name T38
Test name
Test status
Simulation time 22261852165 ps
CPU time 24.88 seconds
Started Mar 19 01:19:09 PM PDT 24
Finished Mar 19 01:19:34 PM PDT 24
Peak memory 235920 kb
Host smart-2654cfcd-913f-486d-94f3-da400078fca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918698979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2918698979
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1513084571
Short name T705
Test name
Test status
Simulation time 2982699605 ps
CPU time 4.05 seconds
Started Mar 19 01:19:10 PM PDT 24
Finished Mar 19 01:19:14 PM PDT 24
Peak memory 218376 kb
Host smart-c96a0183-1d90-49d6-97a2-3e5cac4a17d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513084571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1513084571
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2704213761
Short name T950
Test name
Test status
Simulation time 1992345952 ps
CPU time 4.82 seconds
Started Mar 19 01:19:11 PM PDT 24
Finished Mar 19 01:19:16 PM PDT 24
Peak memory 228496 kb
Host smart-8ddb6012-eb12-4d82-af13-5c7b6b985581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704213761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2704213761
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2427921876
Short name T182
Test name
Test status
Simulation time 14883744680 ps
CPU time 10.55 seconds
Started Mar 19 01:19:09 PM PDT 24
Finished Mar 19 01:19:20 PM PDT 24
Peak memory 238796 kb
Host smart-03f15542-426b-4737-aa0c-2db1e24f8f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427921876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2427921876
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2547339288
Short name T625
Test name
Test status
Simulation time 4671154283 ps
CPU time 5.93 seconds
Started Mar 19 01:19:07 PM PDT 24
Finished Mar 19 01:19:13 PM PDT 24
Peak memory 218016 kb
Host smart-3a6f3a75-1c4d-44e4-b4b6-a4a2c2c5c468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547339288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2547339288
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3346185923
Short name T522
Test name
Test status
Simulation time 4544317906 ps
CPU time 6.08 seconds
Started Mar 19 01:19:08 PM PDT 24
Finished Mar 19 01:19:14 PM PDT 24
Peak memory 221900 kb
Host smart-f944ac1b-724f-4db1-97cb-3692a83a4fc3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3346185923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3346185923
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.4149764088
Short name T217
Test name
Test status
Simulation time 195336528000 ps
CPU time 849.17 seconds
Started Mar 19 01:19:11 PM PDT 24
Finished Mar 19 01:33:20 PM PDT 24
Peak memory 271968 kb
Host smart-58efe50c-21fd-4abf-8896-242370dcdd86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149764088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.4149764088
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.828430037
Short name T859
Test name
Test status
Simulation time 13437617618 ps
CPU time 33.12 seconds
Started Mar 19 01:19:06 PM PDT 24
Finished Mar 19 01:19:40 PM PDT 24
Peak memory 215776 kb
Host smart-90d20a8c-b0cf-4e88-a1fd-62e971080807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828430037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.828430037
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.503977892
Short name T815
Test name
Test status
Simulation time 3603956495 ps
CPU time 5.39 seconds
Started Mar 19 01:19:09 PM PDT 24
Finished Mar 19 01:19:14 PM PDT 24
Peak memory 215892 kb
Host smart-827ad23c-4915-424d-9d13-ef21df2ecb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503977892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.503977892
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.814055618
Short name T797
Test name
Test status
Simulation time 1570910412 ps
CPU time 3.68 seconds
Started Mar 19 01:19:09 PM PDT 24
Finished Mar 19 01:19:13 PM PDT 24
Peak memory 215744 kb
Host smart-f21d4507-66f3-413a-8bb8-5e68c5ca5d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814055618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.814055618
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.873505428
Short name T847
Test name
Test status
Simulation time 92938033 ps
CPU time 0.81 seconds
Started Mar 19 01:19:07 PM PDT 24
Finished Mar 19 01:19:08 PM PDT 24
Peak memory 204984 kb
Host smart-8505ecf4-90df-47d5-a96c-e1e598a950c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873505428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.873505428
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1794713649
Short name T361
Test name
Test status
Simulation time 3859131083 ps
CPU time 6.77 seconds
Started Mar 19 01:19:07 PM PDT 24
Finished Mar 19 01:19:14 PM PDT 24
Peak memory 234432 kb
Host smart-f9e80d3f-a80a-4d07-8f68-044d382722d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794713649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1794713649
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.4196950409
Short name T340
Test name
Test status
Simulation time 18005217 ps
CPU time 0.72 seconds
Started Mar 19 01:19:15 PM PDT 24
Finished Mar 19 01:19:16 PM PDT 24
Peak memory 204556 kb
Host smart-5a023d4f-2067-4d0b-b940-302c70344132
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196950409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
4196950409
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.987680671
Short name T411
Test name
Test status
Simulation time 32756088 ps
CPU time 2.38 seconds
Started Mar 19 01:19:07 PM PDT 24
Finished Mar 19 01:19:10 PM PDT 24
Peak memory 233728 kb
Host smart-c7424cda-9dd8-4aa9-967f-7c470b3a46eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987680671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.987680671
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.802041020
Short name T751
Test name
Test status
Simulation time 70126603 ps
CPU time 0.85 seconds
Started Mar 19 01:19:09 PM PDT 24
Finished Mar 19 01:19:10 PM PDT 24
Peak memory 206076 kb
Host smart-10f0e92b-022c-477a-9444-8e0967f03eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802041020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.802041020
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3064487846
Short name T400
Test name
Test status
Simulation time 11362833064 ps
CPU time 55.83 seconds
Started Mar 19 01:19:16 PM PDT 24
Finished Mar 19 01:20:12 PM PDT 24
Peak memory 224140 kb
Host smart-bfbb9e8e-0145-469a-853a-dd72d7f7d0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064487846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3064487846
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3962919791
Short name T763
Test name
Test status
Simulation time 18779513536 ps
CPU time 81.52 seconds
Started Mar 19 01:19:16 PM PDT 24
Finished Mar 19 01:20:38 PM PDT 24
Peak memory 266972 kb
Host smart-ee47da6f-541d-4ea2-b77b-9f3af646ee25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962919791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3962919791
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1919049661
Short name T457
Test name
Test status
Simulation time 28996617770 ps
CPU time 85.12 seconds
Started Mar 19 01:19:15 PM PDT 24
Finished Mar 19 01:20:41 PM PDT 24
Peak memory 265104 kb
Host smart-d55bd3be-3dc6-4b3d-b11d-307af1014762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919049661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1919049661
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2016582207
Short name T301
Test name
Test status
Simulation time 11060382618 ps
CPU time 25.31 seconds
Started Mar 19 01:19:11 PM PDT 24
Finished Mar 19 01:19:36 PM PDT 24
Peak memory 228372 kb
Host smart-5d2b21b5-a93f-46e7-b1da-f151a723eef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016582207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2016582207
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2436597542
Short name T752
Test name
Test status
Simulation time 6197485603 ps
CPU time 4.77 seconds
Started Mar 19 01:19:07 PM PDT 24
Finished Mar 19 01:19:12 PM PDT 24
Peak memory 220120 kb
Host smart-cc94cf20-5888-44fd-9fe3-fa32e6a92297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436597542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2436597542
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.228096541
Short name T647
Test name
Test status
Simulation time 185452533 ps
CPU time 4.18 seconds
Started Mar 19 01:19:08 PM PDT 24
Finished Mar 19 01:19:13 PM PDT 24
Peak memory 217340 kb
Host smart-fb6ac08d-2ba0-4276-a32a-44108a3e347d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228096541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.228096541
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2415283595
Short name T858
Test name
Test status
Simulation time 1695672440 ps
CPU time 8.14 seconds
Started Mar 19 01:19:09 PM PDT 24
Finished Mar 19 01:19:17 PM PDT 24
Peak memory 224076 kb
Host smart-b158ba38-dc84-4e8a-95d6-81de54d5e83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415283595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2415283595
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2750805021
Short name T177
Test name
Test status
Simulation time 11884624141 ps
CPU time 6.31 seconds
Started Mar 19 01:19:09 PM PDT 24
Finished Mar 19 01:19:16 PM PDT 24
Peak memory 233292 kb
Host smart-a820abb9-961e-494c-95e2-228bd3f3ddfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750805021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2750805021
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1992204384
Short name T661
Test name
Test status
Simulation time 560131620 ps
CPU time 4.21 seconds
Started Mar 19 01:19:19 PM PDT 24
Finished Mar 19 01:19:24 PM PDT 24
Peak memory 221688 kb
Host smart-17f08607-f0fe-41e4-b5be-7d4fb6e7ba3d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1992204384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1992204384
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.729994433
Short name T967
Test name
Test status
Simulation time 2727174842 ps
CPU time 13.41 seconds
Started Mar 19 01:19:09 PM PDT 24
Finished Mar 19 01:19:23 PM PDT 24
Peak memory 215756 kb
Host smart-66b83755-a03d-4bed-b4ed-901720a1768d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729994433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.729994433
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1499336796
Short name T627
Test name
Test status
Simulation time 1811316560 ps
CPU time 3.89 seconds
Started Mar 19 01:19:07 PM PDT 24
Finished Mar 19 01:19:11 PM PDT 24
Peak memory 215728 kb
Host smart-9dd9312a-4cf8-475d-a789-7eb10f9004a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499336796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1499336796
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.4116694662
Short name T279
Test name
Test status
Simulation time 33867922 ps
CPU time 1.58 seconds
Started Mar 19 01:19:10 PM PDT 24
Finished Mar 19 01:19:12 PM PDT 24
Peak memory 215736 kb
Host smart-34a16142-183b-467f-bab1-ea79bf6e7c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116694662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.4116694662
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.653811682
Short name T777
Test name
Test status
Simulation time 164966263 ps
CPU time 0.92 seconds
Started Mar 19 01:19:08 PM PDT 24
Finished Mar 19 01:19:10 PM PDT 24
Peak memory 205840 kb
Host smart-40090aed-3c90-4d18-b570-6850491148e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653811682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.653811682
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.2534895869
Short name T633
Test name
Test status
Simulation time 13332313027 ps
CPU time 12.01 seconds
Started Mar 19 01:19:08 PM PDT 24
Finished Mar 19 01:19:20 PM PDT 24
Peak memory 219392 kb
Host smart-5262e718-b272-4621-835b-4c7dbbafb6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534895869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2534895869
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.930509985
Short name T496
Test name
Test status
Simulation time 117755507 ps
CPU time 0.72 seconds
Started Mar 19 01:19:22 PM PDT 24
Finished Mar 19 01:19:23 PM PDT 24
Peak memory 204312 kb
Host smart-4ca4c511-1ab5-4a99-80d4-5275c6c97926
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930509985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.930509985
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1424909394
Short name T588
Test name
Test status
Simulation time 1817152385 ps
CPU time 5.24 seconds
Started Mar 19 01:19:19 PM PDT 24
Finished Mar 19 01:19:25 PM PDT 24
Peak memory 219968 kb
Host smart-58ce310b-dcf3-4a25-9203-741ea1d71f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424909394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1424909394
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.4049419982
Short name T700
Test name
Test status
Simulation time 17493675 ps
CPU time 0.76 seconds
Started Mar 19 01:19:16 PM PDT 24
Finished Mar 19 01:19:17 PM PDT 24
Peak memory 206376 kb
Host smart-edb70958-f076-4712-b103-08cf833c265f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049419982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.4049419982
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3494284598
Short name T710
Test name
Test status
Simulation time 150740002720 ps
CPU time 231.54 seconds
Started Mar 19 01:19:22 PM PDT 24
Finished Mar 19 01:23:14 PM PDT 24
Peak memory 235428 kb
Host smart-eafd6978-2d9c-4f60-80e2-84f627304cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494284598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3494284598
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.977540760
Short name T436
Test name
Test status
Simulation time 9237274986 ps
CPU time 60.9 seconds
Started Mar 19 01:19:23 PM PDT 24
Finished Mar 19 01:20:24 PM PDT 24
Peak memory 234508 kb
Host smart-f88cf758-5276-4dc2-971e-18aa16223f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977540760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.977540760
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.3630603294
Short name T144
Test name
Test status
Simulation time 12853493745 ps
CPU time 21.42 seconds
Started Mar 19 01:19:16 PM PDT 24
Finished Mar 19 01:19:38 PM PDT 24
Peak memory 236880 kb
Host smart-f3340615-0898-4331-8da7-59b9a7a0005c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630603294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3630603294
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3030006725
Short name T253
Test name
Test status
Simulation time 3119463422 ps
CPU time 11.62 seconds
Started Mar 19 01:19:13 PM PDT 24
Finished Mar 19 01:19:25 PM PDT 24
Peak memory 233176 kb
Host smart-88945793-3bae-4d3a-98eb-b3a27b3de44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030006725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3030006725
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2647183843
Short name T737
Test name
Test status
Simulation time 2450330684 ps
CPU time 11.61 seconds
Started Mar 19 01:19:16 PM PDT 24
Finished Mar 19 01:19:28 PM PDT 24
Peak memory 238112 kb
Host smart-2af5ed7e-cd53-4248-9531-4f1b3f6b9f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647183843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2647183843
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3930599643
Short name T175
Test name
Test status
Simulation time 8851753925 ps
CPU time 11.51 seconds
Started Mar 19 01:19:16 PM PDT 24
Finished Mar 19 01:19:28 PM PDT 24
Peak memory 223372 kb
Host smart-73e21b7e-03b5-4ab7-8714-951c827a3c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930599643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3930599643
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1079722258
Short name T488
Test name
Test status
Simulation time 26641431381 ps
CPU time 18.49 seconds
Started Mar 19 01:19:16 PM PDT 24
Finished Mar 19 01:19:34 PM PDT 24
Peak memory 238752 kb
Host smart-3eb0c92b-3b6a-49e3-ad44-6558a3a785bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079722258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1079722258
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2423552351
Short name T300
Test name
Test status
Simulation time 570251582 ps
CPU time 4.42 seconds
Started Mar 19 01:19:22 PM PDT 24
Finished Mar 19 01:19:26 PM PDT 24
Peak memory 222400 kb
Host smart-554dff34-ba96-4ad6-957a-4d8920bc7253
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2423552351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2423552351
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1344672119
Short name T462
Test name
Test status
Simulation time 246423809265 ps
CPU time 848.02 seconds
Started Mar 19 01:19:24 PM PDT 24
Finished Mar 19 01:33:32 PM PDT 24
Peak memory 289572 kb
Host smart-cb488701-0ac4-486c-b9c4-774035f914d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344672119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1344672119
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3094220811
Short name T410
Test name
Test status
Simulation time 2771797428 ps
CPU time 20.03 seconds
Started Mar 19 01:19:14 PM PDT 24
Finished Mar 19 01:19:34 PM PDT 24
Peak memory 215888 kb
Host smart-0278a332-aaf3-4226-84f4-13d4d988aeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094220811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3094220811
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1460459939
Short name T721
Test name
Test status
Simulation time 14044568799 ps
CPU time 22.78 seconds
Started Mar 19 01:19:15 PM PDT 24
Finished Mar 19 01:19:38 PM PDT 24
Peak memory 215848 kb
Host smart-a2a6bc88-1bb0-48f3-94e0-ea3a383595d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460459939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1460459939
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1867342017
Short name T274
Test name
Test status
Simulation time 182370616 ps
CPU time 3.15 seconds
Started Mar 19 01:19:15 PM PDT 24
Finished Mar 19 01:19:19 PM PDT 24
Peak memory 215760 kb
Host smart-cb0cabdb-e0e3-4bad-ac0e-113cab4eb1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867342017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1867342017
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3508809532
Short name T550
Test name
Test status
Simulation time 347599121 ps
CPU time 0.9 seconds
Started Mar 19 01:19:14 PM PDT 24
Finished Mar 19 01:19:15 PM PDT 24
Peak memory 205256 kb
Host smart-fdbc0204-5b3f-4006-b704-cbb9a889e21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508809532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3508809532
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2487815234
Short name T206
Test name
Test status
Simulation time 22732818190 ps
CPU time 19.47 seconds
Started Mar 19 01:19:19 PM PDT 24
Finished Mar 19 01:19:39 PM PDT 24
Peak memory 229936 kb
Host smart-18b29119-57a8-435f-98b6-0d8de78c7b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487815234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2487815234
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1608450747
Short name T640
Test name
Test status
Simulation time 15322885 ps
CPU time 0.74 seconds
Started Mar 19 01:19:33 PM PDT 24
Finished Mar 19 01:19:34 PM PDT 24
Peak memory 204820 kb
Host smart-c5dc31e1-e104-437c-af78-78bb0431b15c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608450747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1608450747
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1907728304
Short name T829
Test name
Test status
Simulation time 492223477 ps
CPU time 4.8 seconds
Started Mar 19 01:19:23 PM PDT 24
Finished Mar 19 01:19:28 PM PDT 24
Peak memory 233616 kb
Host smart-b188bf94-e9c4-45a7-8850-6d578f5937cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907728304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1907728304
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.900326743
Short name T334
Test name
Test status
Simulation time 37681151 ps
CPU time 0.74 seconds
Started Mar 19 01:19:22 PM PDT 24
Finished Mar 19 01:19:23 PM PDT 24
Peak memory 205332 kb
Host smart-88087d7a-48c9-4bee-95f6-b008f75e80c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900326743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.900326743
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.4050531948
Short name T886
Test name
Test status
Simulation time 430186152 ps
CPU time 4.11 seconds
Started Mar 19 01:19:23 PM PDT 24
Finished Mar 19 01:19:27 PM PDT 24
Peak memory 224016 kb
Host smart-b2261836-3934-4277-874e-5b3ee957cdd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050531948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.4050531948
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.2414268222
Short name T701
Test name
Test status
Simulation time 1674938366 ps
CPU time 27.95 seconds
Started Mar 19 01:19:22 PM PDT 24
Finished Mar 19 01:19:50 PM PDT 24
Peak memory 222456 kb
Host smart-c699c476-3fbb-45bf-8e5a-3d4396336351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414268222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2414268222
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.258628639
Short name T97
Test name
Test status
Simulation time 89467826750 ps
CPU time 91.44 seconds
Started Mar 19 01:19:22 PM PDT 24
Finished Mar 19 01:20:54 PM PDT 24
Peak memory 232408 kb
Host smart-7a043ab7-126e-4fb0-a36d-b3f3dda72b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258628639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.258628639
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1833566853
Short name T844
Test name
Test status
Simulation time 4990601292 ps
CPU time 11.74 seconds
Started Mar 19 01:19:24 PM PDT 24
Finished Mar 19 01:19:36 PM PDT 24
Peak memory 232256 kb
Host smart-ac672617-7556-4539-9c53-8c0ff017a888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833566853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1833566853
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3091485798
Short name T418
Test name
Test status
Simulation time 2090940643 ps
CPU time 5.09 seconds
Started Mar 19 01:19:24 PM PDT 24
Finished Mar 19 01:19:29 PM PDT 24
Peak memory 218204 kb
Host smart-6d252e50-bba4-4a01-8c8c-b7c39fc3558e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091485798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3091485798
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3202587249
Short name T260
Test name
Test status
Simulation time 14124108867 ps
CPU time 17.2 seconds
Started Mar 19 01:19:25 PM PDT 24
Finished Mar 19 01:19:42 PM PDT 24
Peak memory 218196 kb
Host smart-a112c85c-04e7-4ac2-8cc3-ec8b4885c3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202587249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3202587249
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3594359900
Short name T33
Test name
Test status
Simulation time 785330083 ps
CPU time 5.94 seconds
Started Mar 19 01:19:23 PM PDT 24
Finished Mar 19 01:19:29 PM PDT 24
Peak memory 234660 kb
Host smart-cc7175fc-aacc-40bb-a99a-8fd0280c4cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594359900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3594359900
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.4217521573
Short name T838
Test name
Test status
Simulation time 24291736749 ps
CPU time 18.12 seconds
Started Mar 19 01:19:23 PM PDT 24
Finished Mar 19 01:19:42 PM PDT 24
Peak memory 233344 kb
Host smart-92759c1d-628f-4eaf-a105-c7ba30d79649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217521573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.4217521573
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2305675448
Short name T413
Test name
Test status
Simulation time 202158001 ps
CPU time 4.4 seconds
Started Mar 19 01:19:25 PM PDT 24
Finished Mar 19 01:19:30 PM PDT 24
Peak memory 222388 kb
Host smart-99f8ed9f-6a31-44cb-9c54-77951fa66ab1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2305675448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2305675448
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1824231653
Short name T912
Test name
Test status
Simulation time 262327982 ps
CPU time 1.02 seconds
Started Mar 19 01:19:22 PM PDT 24
Finished Mar 19 01:19:24 PM PDT 24
Peak memory 205940 kb
Host smart-14009f70-8181-4243-ae99-386c83a7a8f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824231653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1824231653
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3390259389
Short name T861
Test name
Test status
Simulation time 4034059468 ps
CPU time 19.16 seconds
Started Mar 19 01:19:23 PM PDT 24
Finished Mar 19 01:19:42 PM PDT 24
Peak memory 215844 kb
Host smart-a668ca7b-4cc5-464f-91e1-4ba07c505515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390259389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3390259389
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1958850151
Short name T518
Test name
Test status
Simulation time 743643100 ps
CPU time 5.61 seconds
Started Mar 19 01:19:24 PM PDT 24
Finished Mar 19 01:19:30 PM PDT 24
Peak memory 215768 kb
Host smart-612e8ee0-b623-4b68-b91c-7a57429e4e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958850151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1958850151
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.1454928400
Short name T319
Test name
Test status
Simulation time 48304354 ps
CPU time 0.81 seconds
Started Mar 19 01:19:23 PM PDT 24
Finished Mar 19 01:19:24 PM PDT 24
Peak memory 205312 kb
Host smart-58a179f8-6b51-4f00-9e74-acf6eb344858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454928400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1454928400
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1070841316
Short name T880
Test name
Test status
Simulation time 303266818 ps
CPU time 1.1 seconds
Started Mar 19 01:19:25 PM PDT 24
Finished Mar 19 01:19:26 PM PDT 24
Peak memory 206216 kb
Host smart-d719e102-4986-4f62-ad10-a32ac40ff518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070841316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1070841316
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1338240870
Short name T611
Test name
Test status
Simulation time 6966692338 ps
CPU time 8.53 seconds
Started Mar 19 01:19:25 PM PDT 24
Finished Mar 19 01:19:33 PM PDT 24
Peak memory 237604 kb
Host smart-1fcce0c2-54c5-4827-a6a1-fcaae8b087ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338240870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1338240870
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.2625778229
Short name T917
Test name
Test status
Simulation time 30876666 ps
CPU time 0.72 seconds
Started Mar 19 01:19:42 PM PDT 24
Finished Mar 19 01:19:42 PM PDT 24
Peak memory 204856 kb
Host smart-cfdbcd46-11bb-4ed4-a981-baa626dd5831
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625778229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
2625778229
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3513836002
Short name T565
Test name
Test status
Simulation time 820706703 ps
CPU time 4.7 seconds
Started Mar 19 01:19:53 PM PDT 24
Finished Mar 19 01:19:58 PM PDT 24
Peak memory 218164 kb
Host smart-bca2f5b1-3a60-4917-932a-867cb6cd403c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513836002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3513836002
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.365892321
Short name T341
Test name
Test status
Simulation time 13022012 ps
CPU time 0.71 seconds
Started Mar 19 01:19:35 PM PDT 24
Finished Mar 19 01:19:36 PM PDT 24
Peak memory 205044 kb
Host smart-aca8efce-ae42-407d-88ee-4cf8de9a154c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365892321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.365892321
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.199172095
Short name T215
Test name
Test status
Simulation time 6301963141 ps
CPU time 56.93 seconds
Started Mar 19 01:19:32 PM PDT 24
Finished Mar 19 01:20:29 PM PDT 24
Peak memory 251264 kb
Host smart-5d418468-c8a6-447e-8f64-dd5d14683e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199172095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.199172095
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.2013734569
Short name T421
Test name
Test status
Simulation time 6324495111 ps
CPU time 64.79 seconds
Started Mar 19 01:19:33 PM PDT 24
Finished Mar 19 01:20:37 PM PDT 24
Peak memory 250772 kb
Host smart-97bfdfef-ccec-4f8e-8e01-9e20d36ae724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013734569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2013734569
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.426537486
Short name T43
Test name
Test status
Simulation time 66019059776 ps
CPU time 336.52 seconds
Started Mar 19 01:19:37 PM PDT 24
Finished Mar 19 01:25:13 PM PDT 24
Peak memory 256892 kb
Host smart-92972264-4bc4-45ba-99be-793e1b5d6291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426537486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.426537486
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2488921463
Short name T140
Test name
Test status
Simulation time 5760878662 ps
CPU time 36.42 seconds
Started Mar 19 01:19:51 PM PDT 24
Finished Mar 19 01:20:28 PM PDT 24
Peak memory 256892 kb
Host smart-e90dc432-70f6-4286-a96a-c302ba2fad08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488921463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2488921463
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1389159253
Short name T326
Test name
Test status
Simulation time 152309563 ps
CPU time 3.15 seconds
Started Mar 19 01:19:33 PM PDT 24
Finished Mar 19 01:19:36 PM PDT 24
Peak memory 233236 kb
Host smart-473fe594-caf3-4215-849a-bd42fbe7c670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389159253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1389159253
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3716824174
Short name T252
Test name
Test status
Simulation time 704069785 ps
CPU time 10.22 seconds
Started Mar 19 01:19:32 PM PDT 24
Finished Mar 19 01:19:42 PM PDT 24
Peak memory 245368 kb
Host smart-d0504bd3-aedc-48e9-a1b3-1e133423675f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716824174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3716824174
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.269359354
Short name T557
Test name
Test status
Simulation time 37321325245 ps
CPU time 24.2 seconds
Started Mar 19 01:19:51 PM PDT 24
Finished Mar 19 01:20:15 PM PDT 24
Peak memory 216816 kb
Host smart-c7e314fb-6607-4561-bdf3-c25378198f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269359354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.269359354
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1733452042
Short name T10
Test name
Test status
Simulation time 26778491412 ps
CPU time 19.16 seconds
Started Mar 19 01:19:50 PM PDT 24
Finished Mar 19 01:20:10 PM PDT 24
Peak memory 234828 kb
Host smart-944c4e44-14e4-4233-8919-dfca7cf20879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733452042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1733452042
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1352983045
Short name T938
Test name
Test status
Simulation time 325501641 ps
CPU time 4.13 seconds
Started Mar 19 01:19:50 PM PDT 24
Finished Mar 19 01:19:55 PM PDT 24
Peak memory 221248 kb
Host smart-5dfcddc1-50c2-4fe5-bbaf-f824be591030
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1352983045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1352983045
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1938929046
Short name T901
Test name
Test status
Simulation time 17878723270 ps
CPU time 217.15 seconds
Started Mar 19 01:19:50 PM PDT 24
Finished Mar 19 01:23:28 PM PDT 24
Peak memory 281456 kb
Host smart-0c280731-68c2-4cb6-8fc1-6f0eb93f6ae9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938929046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1938929046
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2622016813
Short name T554
Test name
Test status
Simulation time 4711970621 ps
CPU time 16.09 seconds
Started Mar 19 01:19:53 PM PDT 24
Finished Mar 19 01:20:09 PM PDT 24
Peak memory 215916 kb
Host smart-366e41e1-50a3-49ea-ab60-c50b799d3340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622016813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2622016813
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.567683772
Short name T748
Test name
Test status
Simulation time 11387279264 ps
CPU time 31.58 seconds
Started Mar 19 01:19:33 PM PDT 24
Finished Mar 19 01:20:04 PM PDT 24
Peak memory 215820 kb
Host smart-28dbd7fb-3a62-4b5d-8b28-a73f915b2283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567683772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.567683772
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2575062071
Short name T890
Test name
Test status
Simulation time 223013159 ps
CPU time 1.76 seconds
Started Mar 19 01:19:34 PM PDT 24
Finished Mar 19 01:19:36 PM PDT 24
Peak memory 215708 kb
Host smart-e9837153-6777-46c3-855a-4076736207f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575062071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2575062071
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3549674615
Short name T725
Test name
Test status
Simulation time 156584822 ps
CPU time 0.84 seconds
Started Mar 19 01:19:50 PM PDT 24
Finished Mar 19 01:19:52 PM PDT 24
Peak memory 205248 kb
Host smart-263904b7-e5db-431c-b98f-5ec87c0f028f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549674615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3549674615
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.785488730
Short name T963
Test name
Test status
Simulation time 406539552 ps
CPU time 6.05 seconds
Started Mar 19 01:19:51 PM PDT 24
Finished Mar 19 01:19:57 PM PDT 24
Peak memory 240332 kb
Host smart-f0347a50-2a15-4265-8c76-9ca2607cacb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785488730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.785488730
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2693901802
Short name T553
Test name
Test status
Simulation time 24690997 ps
CPU time 0.73 seconds
Started Mar 19 01:19:53 PM PDT 24
Finished Mar 19 01:19:53 PM PDT 24
Peak memory 204328 kb
Host smart-c3cf3138-162b-43d9-b663-cea31d1863d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693901802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2693901802
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2057027422
Short name T337
Test name
Test status
Simulation time 2190304139 ps
CPU time 5.72 seconds
Started Mar 19 01:19:44 PM PDT 24
Finished Mar 19 01:19:50 PM PDT 24
Peak memory 219480 kb
Host smart-3065041d-6034-4143-ada6-f9312b54146d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057027422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2057027422
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2405701069
Short name T17
Test name
Test status
Simulation time 47321327 ps
CPU time 0.76 seconds
Started Mar 19 01:19:43 PM PDT 24
Finished Mar 19 01:19:44 PM PDT 24
Peak memory 205028 kb
Host smart-8c84ee92-511e-42ed-8cb7-e3d5b1707c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405701069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2405701069
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.296044578
Short name T168
Test name
Test status
Simulation time 18394369533 ps
CPU time 98.73 seconds
Started Mar 19 01:19:50 PM PDT 24
Finished Mar 19 01:21:29 PM PDT 24
Peak memory 240492 kb
Host smart-468deb45-5afc-4784-83bd-efe48ce2ddb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296044578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.296044578
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2164948183
Short name T618
Test name
Test status
Simulation time 42489341820 ps
CPU time 99.75 seconds
Started Mar 19 01:19:42 PM PDT 24
Finished Mar 19 01:21:21 PM PDT 24
Peak memory 265200 kb
Host smart-0d56333c-4d9c-4a0b-ac1e-43fb7bd7fbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164948183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2164948183
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.653084020
Short name T88
Test name
Test status
Simulation time 234139020897 ps
CPU time 422.43 seconds
Started Mar 19 01:19:42 PM PDT 24
Finished Mar 19 01:26:45 PM PDT 24
Peak memory 254960 kb
Host smart-80d1c9ac-a803-4895-9362-97a3c6c75069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653084020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.653084020
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1313314169
Short name T269
Test name
Test status
Simulation time 11880598166 ps
CPU time 60.95 seconds
Started Mar 19 01:19:51 PM PDT 24
Finished Mar 19 01:20:52 PM PDT 24
Peak memory 248688 kb
Host smart-244f2dc5-a6df-4778-bc40-b39f1c45688c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313314169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1313314169
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2361823391
Short name T107
Test name
Test status
Simulation time 2800737044 ps
CPU time 5.57 seconds
Started Mar 19 01:19:45 PM PDT 24
Finished Mar 19 01:19:50 PM PDT 24
Peak memory 232840 kb
Host smart-2f00317e-b091-4928-b00e-ca781770c5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361823391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2361823391
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.366938744
Short name T718
Test name
Test status
Simulation time 1529174236 ps
CPU time 10.38 seconds
Started Mar 19 01:19:47 PM PDT 24
Finished Mar 19 01:19:57 PM PDT 24
Peak memory 223108 kb
Host smart-f6367f8b-49bc-4d7c-8df6-1d60130a8a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366938744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.366938744
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.496633147
Short name T307
Test name
Test status
Simulation time 69566186 ps
CPU time 2.34 seconds
Started Mar 19 01:19:49 PM PDT 24
Finished Mar 19 01:19:52 PM PDT 24
Peak memory 232772 kb
Host smart-fa28e002-8ddf-452e-85a8-8a148facf52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496633147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.496633147
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3584781777
Short name T84
Test name
Test status
Simulation time 3963636236 ps
CPU time 15.94 seconds
Started Mar 19 01:19:51 PM PDT 24
Finished Mar 19 01:20:08 PM PDT 24
Peak memory 232284 kb
Host smart-0f7892d7-c45c-4800-b374-0ac44f027861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584781777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3584781777
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2060402238
Short name T863
Test name
Test status
Simulation time 4525605194 ps
CPU time 5.53 seconds
Started Mar 19 01:19:52 PM PDT 24
Finished Mar 19 01:19:57 PM PDT 24
Peak memory 218796 kb
Host smart-7fdf6fc3-d742-45ac-b675-388368feb5f6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2060402238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2060402238
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.653047332
Short name T158
Test name
Test status
Simulation time 16318289432 ps
CPU time 144.82 seconds
Started Mar 19 01:19:41 PM PDT 24
Finished Mar 19 01:22:06 PM PDT 24
Peak memory 256124 kb
Host smart-9bd6c448-ebbd-499e-a9e9-a2756d41d0c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653047332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.653047332
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1704260696
Short name T677
Test name
Test status
Simulation time 14077736083 ps
CPU time 43.33 seconds
Started Mar 19 01:19:53 PM PDT 24
Finished Mar 19 01:20:37 PM PDT 24
Peak memory 215876 kb
Host smart-58a234f6-7186-4a48-a35e-605f6ff30ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704260696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1704260696
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3332599170
Short name T673
Test name
Test status
Simulation time 19545827555 ps
CPU time 25.88 seconds
Started Mar 19 01:19:52 PM PDT 24
Finished Mar 19 01:20:18 PM PDT 24
Peak memory 215796 kb
Host smart-33e64db0-25d2-44cd-9a67-d3de35090ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332599170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3332599170
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3302057479
Short name T378
Test name
Test status
Simulation time 182358931 ps
CPU time 2.86 seconds
Started Mar 19 01:19:42 PM PDT 24
Finished Mar 19 01:19:45 PM PDT 24
Peak memory 215920 kb
Host smart-6a465eec-74e9-479c-adfb-67b65c65671c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302057479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3302057479
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.4030769367
Short name T549
Test name
Test status
Simulation time 90169926 ps
CPU time 1.03 seconds
Started Mar 19 01:19:51 PM PDT 24
Finished Mar 19 01:19:53 PM PDT 24
Peak memory 206344 kb
Host smart-176be992-c166-408b-9a9b-15894184115b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030769367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.4030769367
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3253433859
Short name T170
Test name
Test status
Simulation time 1281623592 ps
CPU time 6.26 seconds
Started Mar 19 01:19:52 PM PDT 24
Finished Mar 19 01:19:59 PM PDT 24
Peak memory 233792 kb
Host smart-f3c11699-34a8-49cd-86a1-b277994fbcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253433859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3253433859
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2239917292
Short name T848
Test name
Test status
Simulation time 29777006 ps
CPU time 0.68 seconds
Started Mar 19 01:19:54 PM PDT 24
Finished Mar 19 01:19:55 PM PDT 24
Peak memory 204880 kb
Host smart-badf2ad5-0d1c-4915-b55a-a1a203757a9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239917292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2239917292
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.622274804
Short name T745
Test name
Test status
Simulation time 5416152884 ps
CPU time 6.99 seconds
Started Mar 19 01:19:53 PM PDT 24
Finished Mar 19 01:20:01 PM PDT 24
Peak memory 218976 kb
Host smart-e0a269c0-e4cc-4f78-b73b-76fd4a462bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622274804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.622274804
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.827169473
Short name T435
Test name
Test status
Simulation time 38748016 ps
CPU time 0.77 seconds
Started Mar 19 01:19:46 PM PDT 24
Finished Mar 19 01:19:48 PM PDT 24
Peak memory 206416 kb
Host smart-8f6c96a5-b21f-4e59-ac1d-3a3f69e17ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827169473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.827169473
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3966395886
Short name T346
Test name
Test status
Simulation time 139649825355 ps
CPU time 49.07 seconds
Started Mar 19 01:19:56 PM PDT 24
Finished Mar 19 01:20:45 PM PDT 24
Peak memory 248756 kb
Host smart-7ac4bad8-0a72-4293-811f-a1ceb55e3b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966395886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3966395886
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.1170749931
Short name T216
Test name
Test status
Simulation time 57573456156 ps
CPU time 127.98 seconds
Started Mar 19 01:19:49 PM PDT 24
Finished Mar 19 01:21:57 PM PDT 24
Peak memory 264904 kb
Host smart-c8bcddd3-1440-414c-905f-a48f7446131b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170749931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1170749931
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3488741736
Short name T795
Test name
Test status
Simulation time 34645874842 ps
CPU time 292.91 seconds
Started Mar 19 01:19:52 PM PDT 24
Finished Mar 19 01:24:45 PM PDT 24
Peak memory 261416 kb
Host smart-5b5e4b7e-51c3-4412-81fd-ad8ea7effe9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488741736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3488741736
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2146029843
Short name T497
Test name
Test status
Simulation time 9169966113 ps
CPU time 39.68 seconds
Started Mar 19 01:19:50 PM PDT 24
Finished Mar 19 01:20:30 PM PDT 24
Peak memory 237124 kb
Host smart-99654004-7ed1-41dd-9f72-637d9ac3c4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146029843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2146029843
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1835868522
Short name T653
Test name
Test status
Simulation time 3341399448 ps
CPU time 12.4 seconds
Started Mar 19 01:19:45 PM PDT 24
Finished Mar 19 01:19:57 PM PDT 24
Peak memory 219584 kb
Host smart-271fd0fb-8b28-4e93-8d0f-dded66f92a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835868522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1835868522
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3334461847
Short name T437
Test name
Test status
Simulation time 5289538426 ps
CPU time 10.59 seconds
Started Mar 19 01:19:52 PM PDT 24
Finished Mar 19 01:20:03 PM PDT 24
Peak memory 234864 kb
Host smart-5456a3ab-9b72-4373-bb6d-eb9197bbb808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334461847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3334461847
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1165630082
Short name T869
Test name
Test status
Simulation time 11028410808 ps
CPU time 14.19 seconds
Started Mar 19 01:19:52 PM PDT 24
Finished Mar 19 01:20:07 PM PDT 24
Peak memory 233352 kb
Host smart-a08f8619-7465-4551-a48e-280c257e6aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165630082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1165630082
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2477071213
Short name T523
Test name
Test status
Simulation time 3833156396 ps
CPU time 13.05 seconds
Started Mar 19 01:19:43 PM PDT 24
Finished Mar 19 01:19:56 PM PDT 24
Peak memory 228656 kb
Host smart-edc96f07-9841-439d-bdbd-ec9384f4f75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477071213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2477071213
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.352990899
Short name T369
Test name
Test status
Simulation time 3730286956 ps
CPU time 5.35 seconds
Started Mar 19 01:19:45 PM PDT 24
Finished Mar 19 01:19:51 PM PDT 24
Peak memory 218608 kb
Host smart-107e2cb1-7388-4973-a57b-e77a1d808107
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=352990899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dire
ct.352990899
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2404067493
Short name T161
Test name
Test status
Simulation time 36661216631 ps
CPU time 78.84 seconds
Started Mar 19 01:19:55 PM PDT 24
Finished Mar 19 01:21:14 PM PDT 24
Peak memory 264164 kb
Host smart-a83958b9-269f-49bc-90e4-343ad032e00b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404067493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2404067493
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3570799731
Short name T454
Test name
Test status
Simulation time 10226925917 ps
CPU time 25.31 seconds
Started Mar 19 01:19:43 PM PDT 24
Finished Mar 19 01:20:08 PM PDT 24
Peak memory 215868 kb
Host smart-6e4bc2bd-6e7d-4cda-83d6-1a9d6f451047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570799731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3570799731
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2921488688
Short name T580
Test name
Test status
Simulation time 880308727 ps
CPU time 2.7 seconds
Started Mar 19 01:19:51 PM PDT 24
Finished Mar 19 01:19:54 PM PDT 24
Peak memory 215576 kb
Host smart-b6b927d9-a6ac-473f-9612-d63d07004819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921488688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2921488688
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2585536229
Short name T80
Test name
Test status
Simulation time 664608989 ps
CPU time 8.38 seconds
Started Mar 19 01:19:44 PM PDT 24
Finished Mar 19 01:19:53 PM PDT 24
Peak memory 215832 kb
Host smart-dcfc6c67-817f-4475-8df0-8c034c976817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585536229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2585536229
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2407022536
Short name T397
Test name
Test status
Simulation time 84396998 ps
CPU time 0.9 seconds
Started Mar 19 01:19:53 PM PDT 24
Finished Mar 19 01:19:55 PM PDT 24
Peak memory 206304 kb
Host smart-9736c3cc-dd80-4f48-9cbe-12dd0307c189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407022536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2407022536
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.198566182
Short name T867
Test name
Test status
Simulation time 2993207818 ps
CPU time 6.27 seconds
Started Mar 19 01:19:42 PM PDT 24
Finished Mar 19 01:19:48 PM PDT 24
Peak memory 234072 kb
Host smart-ee574ba3-895d-4ded-b2bd-03d4a91bc9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198566182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.198566182
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.358534293
Short name T425
Test name
Test status
Simulation time 31619669 ps
CPU time 0.73 seconds
Started Mar 19 01:19:54 PM PDT 24
Finished Mar 19 01:19:55 PM PDT 24
Peak memory 204900 kb
Host smart-c25c3011-4527-44fc-8e2a-70a881ca656e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358534293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.358534293
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3963295813
Short name T758
Test name
Test status
Simulation time 148272358 ps
CPU time 2.68 seconds
Started Mar 19 01:19:49 PM PDT 24
Finished Mar 19 01:19:52 PM PDT 24
Peak memory 233816 kb
Host smart-9d06c652-0a25-4054-98ff-73d6fa1df732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963295813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3963295813
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.911139855
Short name T538
Test name
Test status
Simulation time 17185226 ps
CPU time 0.78 seconds
Started Mar 19 01:19:53 PM PDT 24
Finished Mar 19 01:19:53 PM PDT 24
Peak memory 205956 kb
Host smart-fc2c2cce-c745-404e-b548-0b835b556f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911139855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.911139855
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.4046620248
Short name T26
Test name
Test status
Simulation time 82228786353 ps
CPU time 92.58 seconds
Started Mar 19 01:19:49 PM PDT 24
Finished Mar 19 01:21:22 PM PDT 24
Peak memory 240416 kb
Host smart-6babae47-eb69-44fc-be0a-1a0f6aa94ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046620248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.4046620248
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1417280696
Short name T136
Test name
Test status
Simulation time 40916755353 ps
CPU time 86.87 seconds
Started Mar 19 01:19:52 PM PDT 24
Finished Mar 19 01:21:19 PM PDT 24
Peak memory 250044 kb
Host smart-6a286355-e5eb-4570-bf47-e08158029e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417280696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1417280696
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3214783181
Short name T586
Test name
Test status
Simulation time 194275070566 ps
CPU time 110.83 seconds
Started Mar 19 01:19:55 PM PDT 24
Finished Mar 19 01:21:46 PM PDT 24
Peak memory 240648 kb
Host smart-0d4de8e4-af62-44aa-bb42-797e7a3c61cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214783181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3214783181
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1565336894
Short name T943
Test name
Test status
Simulation time 9639488402 ps
CPU time 30.21 seconds
Started Mar 19 01:19:55 PM PDT 24
Finished Mar 19 01:20:25 PM PDT 24
Peak memory 231684 kb
Host smart-732bc0b3-98df-411b-9907-31b27efdbae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565336894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1565336894
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3485062286
Short name T5
Test name
Test status
Simulation time 990639565 ps
CPU time 3.04 seconds
Started Mar 19 01:19:55 PM PDT 24
Finished Mar 19 01:19:58 PM PDT 24
Peak memory 232868 kb
Host smart-b9670a5a-d4e8-417c-8a5a-ab26999d9c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485062286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3485062286
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.96493237
Short name T808
Test name
Test status
Simulation time 17406860903 ps
CPU time 17.16 seconds
Started Mar 19 01:19:54 PM PDT 24
Finished Mar 19 01:20:11 PM PDT 24
Peak memory 230088 kb
Host smart-b0fe178c-9559-449d-a49e-13e535f6c963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96493237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.96493237
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2996044134
Short name T58
Test name
Test status
Simulation time 8263876405 ps
CPU time 10.05 seconds
Started Mar 19 01:19:54 PM PDT 24
Finished Mar 19 01:20:04 PM PDT 24
Peak memory 240308 kb
Host smart-16fab685-35f4-4a19-84fc-5806b788868a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996044134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2996044134
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3556831085
Short name T365
Test name
Test status
Simulation time 12797788193 ps
CPU time 27.4 seconds
Started Mar 19 01:19:53 PM PDT 24
Finished Mar 19 01:20:21 PM PDT 24
Peak memory 234248 kb
Host smart-df254224-4bd4-4819-8f41-d4724db87210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556831085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3556831085
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.4000815934
Short name T665
Test name
Test status
Simulation time 442339736 ps
CPU time 4.21 seconds
Started Mar 19 01:19:55 PM PDT 24
Finished Mar 19 01:19:59 PM PDT 24
Peak memory 218644 kb
Host smart-fff7657e-06e2-4f53-a3f7-af8911511ed0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4000815934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.4000815934
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1528276319
Short name T789
Test name
Test status
Simulation time 66169950488 ps
CPU time 161.35 seconds
Started Mar 19 01:19:53 PM PDT 24
Finished Mar 19 01:22:34 PM PDT 24
Peak memory 273320 kb
Host smart-de7de4a5-60a2-456c-8354-ef1aba27600a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528276319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1528276319
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2886692318
Short name T277
Test name
Test status
Simulation time 7055574295 ps
CPU time 47.53 seconds
Started Mar 19 01:19:52 PM PDT 24
Finished Mar 19 01:20:40 PM PDT 24
Peak memory 215836 kb
Host smart-398999d7-9274-46dd-8949-d8ac9923d4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886692318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2886692318
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2766639584
Short name T841
Test name
Test status
Simulation time 1322608051 ps
CPU time 2.96 seconds
Started Mar 19 01:19:49 PM PDT 24
Finished Mar 19 01:19:52 PM PDT 24
Peak memory 207400 kb
Host smart-729aca73-f4c5-4c7f-8b52-8d240a48b39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766639584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2766639584
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.617946838
Short name T528
Test name
Test status
Simulation time 52714313 ps
CPU time 1.23 seconds
Started Mar 19 01:19:55 PM PDT 24
Finished Mar 19 01:19:57 PM PDT 24
Peak memory 207368 kb
Host smart-4b080206-27ab-4ebe-8a44-2bdcfeb45e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617946838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.617946838
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1271375083
Short name T370
Test name
Test status
Simulation time 151047791 ps
CPU time 0.8 seconds
Started Mar 19 01:19:47 PM PDT 24
Finished Mar 19 01:19:48 PM PDT 24
Peak memory 205256 kb
Host smart-45904441-5720-4047-ace4-d2f396a566a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271375083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1271375083
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.4177589071
Short name T173
Test name
Test status
Simulation time 2717996180 ps
CPU time 3.5 seconds
Started Mar 19 01:19:48 PM PDT 24
Finished Mar 19 01:19:52 PM PDT 24
Peak memory 216936 kb
Host smart-9316a648-760c-4648-b5d9-67732e638a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177589071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.4177589071
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2145132697
Short name T558
Test name
Test status
Simulation time 42667969 ps
CPU time 0.71 seconds
Started Mar 19 01:13:55 PM PDT 24
Finished Mar 19 01:13:56 PM PDT 24
Peak memory 204320 kb
Host smart-43eb7385-069d-469e-aca7-729778109896
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145132697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
145132697
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.4189938904
Short name T486
Test name
Test status
Simulation time 1043978463 ps
CPU time 5.03 seconds
Started Mar 19 01:13:46 PM PDT 24
Finished Mar 19 01:13:51 PM PDT 24
Peak memory 234024 kb
Host smart-75fa7946-e5b0-486c-92cc-6548ce967eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189938904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.4189938904
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2274953365
Short name T717
Test name
Test status
Simulation time 18778978 ps
CPU time 0.77 seconds
Started Mar 19 01:13:49 PM PDT 24
Finished Mar 19 01:13:49 PM PDT 24
Peak memory 206008 kb
Host smart-ff743a5d-8add-4081-a56c-669343305067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274953365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2274953365
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2585026867
Short name T255
Test name
Test status
Simulation time 182195697140 ps
CPU time 141.66 seconds
Started Mar 19 01:13:57 PM PDT 24
Finished Mar 19 01:16:19 PM PDT 24
Peak memory 240528 kb
Host smart-735c09a3-4274-4fc5-993a-d1efcef3410a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585026867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2585026867
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2885088865
Short name T573
Test name
Test status
Simulation time 2984194846 ps
CPU time 43.73 seconds
Started Mar 19 01:13:53 PM PDT 24
Finished Mar 19 01:14:37 PM PDT 24
Peak memory 235476 kb
Host smart-beae31d2-6900-4d95-9063-aedcfaf7e590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885088865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2885088865
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2102781246
Short name T915
Test name
Test status
Simulation time 62852437563 ps
CPU time 279.36 seconds
Started Mar 19 01:14:04 PM PDT 24
Finished Mar 19 01:18:44 PM PDT 24
Peak memory 260708 kb
Host smart-1b65fddd-b6be-4a71-9ecf-00327396cccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102781246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2102781246
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2715561209
Short name T480
Test name
Test status
Simulation time 5324424373 ps
CPU time 33.8 seconds
Started Mar 19 01:13:47 PM PDT 24
Finished Mar 19 01:14:20 PM PDT 24
Peak memory 239424 kb
Host smart-5628d4b0-5d0a-48af-8c7b-3d2e8630d9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715561209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2715561209
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.888366763
Short name T53
Test name
Test status
Simulation time 3662891621 ps
CPU time 12.96 seconds
Started Mar 19 01:13:48 PM PDT 24
Finished Mar 19 01:14:01 PM PDT 24
Peak memory 233852 kb
Host smart-628336ef-477d-43da-9728-11474c29d03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888366763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.888366763
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.57153815
Short name T887
Test name
Test status
Simulation time 2461841118 ps
CPU time 9.56 seconds
Started Mar 19 01:13:46 PM PDT 24
Finished Mar 19 01:13:56 PM PDT 24
Peak memory 218128 kb
Host smart-c5c52084-7000-4c1a-9ef8-1cdedecc08eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57153815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.57153815
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.231868792
Short name T30
Test name
Test status
Simulation time 602573305 ps
CPU time 5.54 seconds
Started Mar 19 01:13:45 PM PDT 24
Finished Mar 19 01:13:51 PM PDT 24
Peak memory 233168 kb
Host smart-bee1b4e7-4beb-4607-9ff2-a795b2a6b657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231868792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.
231868792
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.941967231
Short name T6
Test name
Test status
Simulation time 8710007667 ps
CPU time 6.04 seconds
Started Mar 19 01:13:45 PM PDT 24
Finished Mar 19 01:13:52 PM PDT 24
Peak memory 218364 kb
Host smart-485d49ae-9a90-4fb9-a666-27c56300457d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941967231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.941967231
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.1443505252
Short name T79
Test name
Test status
Simulation time 17934531 ps
CPU time 0.75 seconds
Started Mar 19 01:13:47 PM PDT 24
Finished Mar 19 01:13:48 PM PDT 24
Peak memory 215808 kb
Host smart-5891978b-40ab-4de3-b6f3-5241f9d6b4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443505252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.1443505252
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.418679783
Short name T545
Test name
Test status
Simulation time 4721979040 ps
CPU time 5.86 seconds
Started Mar 19 01:13:47 PM PDT 24
Finished Mar 19 01:13:53 PM PDT 24
Peak memory 219744 kb
Host smart-68aece47-265c-4d11-b308-25c6072a2ad5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=418679783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.418679783
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1171652954
Short name T622
Test name
Test status
Simulation time 12103350678 ps
CPU time 124.17 seconds
Started Mar 19 01:13:55 PM PDT 24
Finished Mar 19 01:15:59 PM PDT 24
Peak memory 256968 kb
Host smart-fd3c49f6-6fd1-43b2-ad7d-83e5e73fcca0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171652954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1171652954
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2700915017
Short name T484
Test name
Test status
Simulation time 12965087945 ps
CPU time 19.88 seconds
Started Mar 19 01:13:46 PM PDT 24
Finished Mar 19 01:14:06 PM PDT 24
Peak memory 215828 kb
Host smart-ef906004-c598-4ca6-812d-944a99b88a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700915017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2700915017
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2211089143
Short name T862
Test name
Test status
Simulation time 1426035283 ps
CPU time 1.81 seconds
Started Mar 19 01:13:48 PM PDT 24
Finished Mar 19 01:13:49 PM PDT 24
Peak memory 207168 kb
Host smart-403c6f02-65a5-4c91-ab7f-f9f86419de98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211089143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2211089143
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.65352035
Short name T276
Test name
Test status
Simulation time 102650888 ps
CPU time 0.98 seconds
Started Mar 19 01:13:48 PM PDT 24
Finished Mar 19 01:13:49 PM PDT 24
Peak memory 206340 kb
Host smart-963e4cca-3886-418e-87c8-4c896bbdc684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65352035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.65352035
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1612151724
Short name T475
Test name
Test status
Simulation time 23699621 ps
CPU time 0.8 seconds
Started Mar 19 01:13:46 PM PDT 24
Finished Mar 19 01:13:47 PM PDT 24
Peak memory 205256 kb
Host smart-1fdb1ad7-6b3e-4ecb-af64-240de164b096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612151724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1612151724
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3724036898
Short name T416
Test name
Test status
Simulation time 4357668246 ps
CPU time 7.13 seconds
Started Mar 19 01:13:47 PM PDT 24
Finished Mar 19 01:13:55 PM PDT 24
Peak memory 233764 kb
Host smart-a14cd11d-ba16-4e34-937a-fe7f1f8b970b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724036898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3724036898
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1169232130
Short name T672
Test name
Test status
Simulation time 18818349 ps
CPU time 0.74 seconds
Started Mar 19 01:14:14 PM PDT 24
Finished Mar 19 01:14:15 PM PDT 24
Peak memory 205216 kb
Host smart-d2a917a8-8ca0-4d3b-a6f1-19cff3628a45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169232130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
169232130
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.374258142
Short name T399
Test name
Test status
Simulation time 106607753 ps
CPU time 2.75 seconds
Started Mar 19 01:14:03 PM PDT 24
Finished Mar 19 01:14:06 PM PDT 24
Peak memory 233264 kb
Host smart-b58e8005-ddc9-45bd-8186-92817d690d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374258142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.374258142
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3441588305
Short name T906
Test name
Test status
Simulation time 48734643 ps
CPU time 0.76 seconds
Started Mar 19 01:14:04 PM PDT 24
Finished Mar 19 01:14:05 PM PDT 24
Peak memory 205316 kb
Host smart-c4d4cfdc-6834-4c74-9678-9291c9c4dd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441588305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3441588305
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.2629140889
Short name T60
Test name
Test status
Simulation time 12816525569 ps
CPU time 61.45 seconds
Started Mar 19 01:14:03 PM PDT 24
Finished Mar 19 01:15:04 PM PDT 24
Peak memory 240408 kb
Host smart-d0a0ea1e-37b6-4654-864f-743f11753dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629140889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2629140889
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2486711839
Short name T22
Test name
Test status
Simulation time 56194845697 ps
CPU time 441.32 seconds
Started Mar 19 01:14:04 PM PDT 24
Finished Mar 19 01:21:25 PM PDT 24
Peak memory 266092 kb
Host smart-5b54afa5-524d-486d-ab23-7519cc4098ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486711839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2486711839
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2660283473
Short name T810
Test name
Test status
Simulation time 11003638077 ps
CPU time 53.68 seconds
Started Mar 19 01:14:04 PM PDT 24
Finished Mar 19 01:14:58 PM PDT 24
Peak memory 240336 kb
Host smart-d59667e0-4f12-439a-b006-2d3d938d013f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660283473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2660283473
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.4266245326
Short name T666
Test name
Test status
Simulation time 7892133847 ps
CPU time 10.98 seconds
Started Mar 19 01:14:04 PM PDT 24
Finished Mar 19 01:14:15 PM PDT 24
Peak memory 220664 kb
Host smart-6d4dc2d9-4e06-4551-8fcb-c2b36737cdb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266245326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.4266245326
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1942145926
Short name T656
Test name
Test status
Simulation time 10010385855 ps
CPU time 18.22 seconds
Started Mar 19 01:14:03 PM PDT 24
Finished Mar 19 01:14:21 PM PDT 24
Peak memory 233292 kb
Host smart-269f7f33-92a3-40d6-85c5-784fbdbe4ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942145926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1942145926
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1719933073
Short name T163
Test name
Test status
Simulation time 9463814241 ps
CPU time 8.1 seconds
Started Mar 19 01:13:53 PM PDT 24
Finished Mar 19 01:14:01 PM PDT 24
Peak memory 234072 kb
Host smart-be9cffd4-130d-4fd1-b040-a2c3bbfd0b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719933073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1719933073
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.4056668263
Short name T649
Test name
Test status
Simulation time 30723793 ps
CPU time 0.75 seconds
Started Mar 19 01:13:55 PM PDT 24
Finished Mar 19 01:13:56 PM PDT 24
Peak memory 215764 kb
Host smart-d079873f-c8a5-490b-adec-cf77d1e76a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056668263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.4056668263
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3315321885
Short name T362
Test name
Test status
Simulation time 746316706 ps
CPU time 5.14 seconds
Started Mar 19 01:14:13 PM PDT 24
Finished Mar 19 01:14:18 PM PDT 24
Peak memory 218748 kb
Host smart-9a8163ef-3c7a-4f07-a2b7-9d62de4c166f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3315321885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3315321885
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.102926333
Short name T155
Test name
Test status
Simulation time 179535246095 ps
CPU time 284.66 seconds
Started Mar 19 01:14:13 PM PDT 24
Finished Mar 19 01:18:57 PM PDT 24
Peak memory 248784 kb
Host smart-21e1f265-cb13-4bd1-af73-e6eaece0da32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102926333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.102926333
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2735382177
Short name T889
Test name
Test status
Simulation time 60446135609 ps
CPU time 48.65 seconds
Started Mar 19 01:14:03 PM PDT 24
Finished Mar 19 01:14:52 PM PDT 24
Peak memory 215856 kb
Host smart-3fde7060-a6e3-4d34-99be-586569185236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735382177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2735382177
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2368777466
Short name T304
Test name
Test status
Simulation time 4207306389 ps
CPU time 18.79 seconds
Started Mar 19 01:14:04 PM PDT 24
Finished Mar 19 01:14:23 PM PDT 24
Peak memory 215808 kb
Host smart-7322e0e3-fee5-43a4-ba34-5b5dcabc8521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368777466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2368777466
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3281164882
Short name T931
Test name
Test status
Simulation time 18345579 ps
CPU time 1.15 seconds
Started Mar 19 01:14:04 PM PDT 24
Finished Mar 19 01:14:06 PM PDT 24
Peak memory 215652 kb
Host smart-a66deb6c-e386-4d16-b184-afa1fa1b261f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281164882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3281164882
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.422613591
Short name T515
Test name
Test status
Simulation time 208069304 ps
CPU time 0.74 seconds
Started Mar 19 01:14:06 PM PDT 24
Finished Mar 19 01:14:07 PM PDT 24
Peak memory 205264 kb
Host smart-e1b0054e-3151-4085-a99b-8c64bb615c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422613591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.422613591
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3216205144
Short name T447
Test name
Test status
Simulation time 15722853858 ps
CPU time 11.11 seconds
Started Mar 19 01:14:02 PM PDT 24
Finished Mar 19 01:14:13 PM PDT 24
Peak memory 233316 kb
Host smart-a2fdea59-5a39-45d2-a774-550bde3a6dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216205144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3216205144
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1175869802
Short name T722
Test name
Test status
Simulation time 16399364 ps
CPU time 0.71 seconds
Started Mar 19 01:14:25 PM PDT 24
Finished Mar 19 01:14:26 PM PDT 24
Peak memory 204876 kb
Host smart-fd08a4f4-60f4-4f5f-a245-f2856232146c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175869802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
175869802
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2556543995
Short name T563
Test name
Test status
Simulation time 2047420823 ps
CPU time 6.09 seconds
Started Mar 19 01:14:13 PM PDT 24
Finished Mar 19 01:14:19 PM PDT 24
Peak memory 232996 kb
Host smart-c2381584-b9d2-4fe7-8ea1-9f7565220ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556543995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2556543995
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1640611374
Short name T746
Test name
Test status
Simulation time 36752501 ps
CPU time 0.79 seconds
Started Mar 19 01:14:12 PM PDT 24
Finished Mar 19 01:14:13 PM PDT 24
Peak memory 204956 kb
Host smart-3ffb0401-64d8-4480-8e3c-4449b46d9467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640611374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1640611374
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3331888897
Short name T873
Test name
Test status
Simulation time 13125900084 ps
CPU time 72.48 seconds
Started Mar 19 01:14:11 PM PDT 24
Finished Mar 19 01:15:24 PM PDT 24
Peak memory 252148 kb
Host smart-5d437bbc-448a-4e01-adb2-c4dc77d534bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331888897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3331888897
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.122418324
Short name T471
Test name
Test status
Simulation time 100331043348 ps
CPU time 270.02 seconds
Started Mar 19 01:14:13 PM PDT 24
Finished Mar 19 01:18:43 PM PDT 24
Peak memory 265836 kb
Host smart-aad29cab-e476-433e-ae9a-20f4d235d7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122418324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.122418324
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1765924687
Short name T762
Test name
Test status
Simulation time 18866067414 ps
CPU time 151.32 seconds
Started Mar 19 01:14:25 PM PDT 24
Finished Mar 19 01:16:56 PM PDT 24
Peak memory 266192 kb
Host smart-6ea11f61-1f2a-4755-a461-cbf8533790d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765924687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1765924687
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.560894296
Short name T898
Test name
Test status
Simulation time 487685341 ps
CPU time 7.77 seconds
Started Mar 19 01:14:13 PM PDT 24
Finished Mar 19 01:14:20 PM PDT 24
Peak memory 232256 kb
Host smart-5e986ff3-4354-4366-84e9-b4b4972881d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560894296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.560894296
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3409034675
Short name T195
Test name
Test status
Simulation time 1947581237 ps
CPU time 3.85 seconds
Started Mar 19 01:14:12 PM PDT 24
Finished Mar 19 01:14:16 PM PDT 24
Peak memory 233276 kb
Host smart-44380bd2-bb1c-4a66-84c2-b9838b743e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409034675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3409034675
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.283570604
Short name T442
Test name
Test status
Simulation time 381375863 ps
CPU time 3.58 seconds
Started Mar 19 01:14:13 PM PDT 24
Finished Mar 19 01:14:17 PM PDT 24
Peak memory 224008 kb
Host smart-69b00752-62e6-4ad9-9365-1e723894714e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283570604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.283570604
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.158673530
Short name T525
Test name
Test status
Simulation time 4759585164 ps
CPU time 16.43 seconds
Started Mar 19 01:14:13 PM PDT 24
Finished Mar 19 01:14:29 PM PDT 24
Peak memory 224088 kb
Host smart-a9fc4c00-cb43-493d-861c-46d6f68991ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158673530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
158673530
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1357724946
Short name T658
Test name
Test status
Simulation time 668112465 ps
CPU time 6.2 seconds
Started Mar 19 01:14:14 PM PDT 24
Finished Mar 19 01:14:20 PM PDT 24
Peak memory 233092 kb
Host smart-65d5428a-ef36-4de0-a3d2-cf03b4ed3548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357724946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1357724946
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.1183077211
Short name T684
Test name
Test status
Simulation time 16463148 ps
CPU time 0.73 seconds
Started Mar 19 01:14:14 PM PDT 24
Finished Mar 19 01:14:15 PM PDT 24
Peak memory 215776 kb
Host smart-a5ed1b01-863a-474b-9530-21de8e7430f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183077211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.1183077211
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.650302477
Short name T142
Test name
Test status
Simulation time 805310378 ps
CPU time 3.24 seconds
Started Mar 19 01:14:22 PM PDT 24
Finished Mar 19 01:14:25 PM PDT 24
Peak memory 218500 kb
Host smart-a40c9cca-de88-47bd-983b-d1cea57d64f5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=650302477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.650302477
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.986693016
Short name T911
Test name
Test status
Simulation time 5222236269 ps
CPU time 102.27 seconds
Started Mar 19 01:14:23 PM PDT 24
Finished Mar 19 01:16:05 PM PDT 24
Peak memory 265200 kb
Host smart-21d23c59-5951-400f-a723-e8ab508fae29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986693016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.986693016
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2206444481
Short name T385
Test name
Test status
Simulation time 3346876639 ps
CPU time 33.57 seconds
Started Mar 19 01:14:14 PM PDT 24
Finished Mar 19 01:14:48 PM PDT 24
Peak memory 215884 kb
Host smart-e66642ad-0ac9-4469-aab1-a58775b64ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206444481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2206444481
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1954946677
Short name T895
Test name
Test status
Simulation time 73679595 ps
CPU time 1.16 seconds
Started Mar 19 01:14:12 PM PDT 24
Finished Mar 19 01:14:14 PM PDT 24
Peak memory 207264 kb
Host smart-4dfb0c33-9b57-4bda-9ad9-84726cb13dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954946677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1954946677
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1971816789
Short name T942
Test name
Test status
Simulation time 28153011 ps
CPU time 1 seconds
Started Mar 19 01:14:12 PM PDT 24
Finished Mar 19 01:14:13 PM PDT 24
Peak memory 207476 kb
Host smart-df5f8fe0-fa4a-4b1c-bbc6-ee162e90db79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971816789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1971816789
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3399293929
Short name T813
Test name
Test status
Simulation time 60800526 ps
CPU time 0.9 seconds
Started Mar 19 01:14:13 PM PDT 24
Finished Mar 19 01:14:14 PM PDT 24
Peak memory 205284 kb
Host smart-76006e2a-d722-4d98-8dc6-bc48e189c1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399293929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3399293929
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2779247559
Short name T637
Test name
Test status
Simulation time 227469195 ps
CPU time 3.05 seconds
Started Mar 19 01:14:12 PM PDT 24
Finished Mar 19 01:14:16 PM PDT 24
Peak memory 232224 kb
Host smart-9afac725-87d9-4a23-8e91-d0d18b8bef20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779247559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2779247559
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1096643622
Short name T903
Test name
Test status
Simulation time 61383022 ps
CPU time 0.71 seconds
Started Mar 19 01:14:47 PM PDT 24
Finished Mar 19 01:14:47 PM PDT 24
Peak memory 204556 kb
Host smart-ebc167f8-2a2b-4f1d-aec1-54b3a8cd1ee9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096643622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
096643622
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2605946356
Short name T323
Test name
Test status
Simulation time 574918272 ps
CPU time 2.67 seconds
Started Mar 19 01:14:24 PM PDT 24
Finished Mar 19 01:14:27 PM PDT 24
Peak memory 218388 kb
Host smart-d9ad5abd-41a8-418d-aac8-9be92c099fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605946356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2605946356
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2371700367
Short name T383
Test name
Test status
Simulation time 47817183 ps
CPU time 0.75 seconds
Started Mar 19 01:14:23 PM PDT 24
Finished Mar 19 01:14:24 PM PDT 24
Peak memory 204956 kb
Host smart-c0d7bcfb-3d9b-454c-8b3e-1898b9a8bcef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371700367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2371700367
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.419444370
Short name T816
Test name
Test status
Simulation time 6927223169 ps
CPU time 22.99 seconds
Started Mar 19 01:14:30 PM PDT 24
Finished Mar 19 01:14:54 PM PDT 24
Peak memory 234976 kb
Host smart-5f0e6d4e-6cd6-4e09-a607-e9077097dc0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419444370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.419444370
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2005398865
Short name T685
Test name
Test status
Simulation time 42030517891 ps
CPU time 132.77 seconds
Started Mar 19 01:14:46 PM PDT 24
Finished Mar 19 01:16:59 PM PDT 24
Peak memory 250436 kb
Host smart-d06518a6-79f7-46a8-b527-ecb1d29393a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005398865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2005398865
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1846541592
Short name T969
Test name
Test status
Simulation time 13772234923 ps
CPU time 19.11 seconds
Started Mar 19 01:14:33 PM PDT 24
Finished Mar 19 01:14:52 PM PDT 24
Peak memory 237976 kb
Host smart-9c17e740-d7cb-477a-9b1b-35e3161c5669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846541592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1846541592
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.4044135195
Short name T256
Test name
Test status
Simulation time 54988057 ps
CPU time 2.48 seconds
Started Mar 19 01:14:26 PM PDT 24
Finished Mar 19 01:14:28 PM PDT 24
Peak memory 232256 kb
Host smart-2969bc11-5eda-49d6-be21-ed8a0d318fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044135195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.4044135195
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.158418339
Short name T603
Test name
Test status
Simulation time 1968808826 ps
CPU time 14.91 seconds
Started Mar 19 01:14:22 PM PDT 24
Finished Mar 19 01:14:37 PM PDT 24
Peak memory 248556 kb
Host smart-f71dca7a-f0ff-4682-a360-216c7ed1dc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158418339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.158418339
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1841146778
Short name T8
Test name
Test status
Simulation time 7301204663 ps
CPU time 21.29 seconds
Started Mar 19 01:14:24 PM PDT 24
Finished Mar 19 01:14:45 PM PDT 24
Peak memory 224080 kb
Host smart-4e0421fd-f717-404c-b8a4-d12c0db062ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841146778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1841146778
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.702086444
Short name T363
Test name
Test status
Simulation time 12859112375 ps
CPU time 4.98 seconds
Started Mar 19 01:14:24 PM PDT 24
Finished Mar 19 01:14:29 PM PDT 24
Peak memory 232268 kb
Host smart-06ea6a29-d73b-44d1-a24b-2a9508486bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702086444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.702086444
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.799179180
Short name T292
Test name
Test status
Simulation time 18529112 ps
CPU time 0.75 seconds
Started Mar 19 01:14:25 PM PDT 24
Finished Mar 19 01:14:26 PM PDT 24
Peak memory 215712 kb
Host smart-24bf2f3f-b5c3-4533-8eb9-71d07733cf49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799179180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.799179180
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2633461452
Short name T952
Test name
Test status
Simulation time 2935251553 ps
CPU time 4.49 seconds
Started Mar 19 01:14:47 PM PDT 24
Finished Mar 19 01:14:51 PM PDT 24
Peak memory 219708 kb
Host smart-566f7ab2-49ac-4138-940f-d4b7158e9dd0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2633461452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2633461452
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2880520169
Short name T50
Test name
Test status
Simulation time 1213437642026 ps
CPU time 778.21 seconds
Started Mar 19 01:14:46 PM PDT 24
Finished Mar 19 01:27:45 PM PDT 24
Peak memory 273040 kb
Host smart-9fad586d-c96b-4d62-916d-e9419c6f785f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880520169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2880520169
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3974677293
Short name T517
Test name
Test status
Simulation time 375238843 ps
CPU time 4.53 seconds
Started Mar 19 01:14:22 PM PDT 24
Finished Mar 19 01:14:27 PM PDT 24
Peak memory 215752 kb
Host smart-e21e626c-c58d-4c43-89a1-edfd717f0c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974677293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3974677293
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3071045037
Short name T448
Test name
Test status
Simulation time 13244171529 ps
CPU time 33.93 seconds
Started Mar 19 01:14:25 PM PDT 24
Finished Mar 19 01:14:59 PM PDT 24
Peak memory 215900 kb
Host smart-b18edad9-4707-4f2c-ba22-caef3274bbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071045037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3071045037
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2203380799
Short name T417
Test name
Test status
Simulation time 249373310 ps
CPU time 1.95 seconds
Started Mar 19 01:14:22 PM PDT 24
Finished Mar 19 01:14:24 PM PDT 24
Peak memory 215824 kb
Host smart-12dcd617-c427-4c44-9008-1476628f8b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203380799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2203380799
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2490918335
Short name T324
Test name
Test status
Simulation time 121357578 ps
CPU time 0.93 seconds
Started Mar 19 01:14:24 PM PDT 24
Finished Mar 19 01:14:25 PM PDT 24
Peak memory 206216 kb
Host smart-16252b89-dd12-499d-9fb3-25ce3df3df84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490918335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2490918335
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1407926772
Short name T831
Test name
Test status
Simulation time 1471782778 ps
CPU time 8.71 seconds
Started Mar 19 01:14:23 PM PDT 24
Finished Mar 19 01:14:32 PM PDT 24
Peak memory 233336 kb
Host smart-b7a14ec1-b655-44c1-a86e-39592f817f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407926772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1407926772
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2691939228
Short name T513
Test name
Test status
Simulation time 128172551 ps
CPU time 0.7 seconds
Started Mar 19 01:14:41 PM PDT 24
Finished Mar 19 01:14:42 PM PDT 24
Peak memory 204896 kb
Host smart-355922cf-e335-4d5b-9303-69a0ab26774c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691939228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
691939228
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.4236048848
Short name T587
Test name
Test status
Simulation time 6511524903 ps
CPU time 6.18 seconds
Started Mar 19 01:14:47 PM PDT 24
Finished Mar 19 01:14:53 PM PDT 24
Peak memory 218112 kb
Host smart-0570d167-3137-4ef6-9f32-be8343599b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236048848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.4236048848
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2108946181
Short name T470
Test name
Test status
Simulation time 20392875 ps
CPU time 0.77 seconds
Started Mar 19 01:14:30 PM PDT 24
Finished Mar 19 01:14:31 PM PDT 24
Peak memory 204940 kb
Host smart-ea5012e2-3a68-4fe0-b36e-d3a7ea579e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108946181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2108946181
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3880135505
Short name T166
Test name
Test status
Simulation time 3612394689 ps
CPU time 30.42 seconds
Started Mar 19 01:14:40 PM PDT 24
Finished Mar 19 01:15:10 PM PDT 24
Peak memory 240516 kb
Host smart-b9728579-2cd7-425f-948d-6b93bd6c177e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880135505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3880135505
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3325900845
Short name T572
Test name
Test status
Simulation time 17777676360 ps
CPU time 145.6 seconds
Started Mar 19 01:14:41 PM PDT 24
Finished Mar 19 01:17:06 PM PDT 24
Peak memory 249828 kb
Host smart-e41b91e9-49f7-4c94-839f-cfc3eca36dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325900845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3325900845
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.720567975
Short name T547
Test name
Test status
Simulation time 51691814428 ps
CPU time 351.16 seconds
Started Mar 19 01:14:41 PM PDT 24
Finished Mar 19 01:20:32 PM PDT 24
Peak memory 256964 kb
Host smart-141a4d57-5d6b-40cf-9d78-db78dded5d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720567975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
720567975
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3590329974
Short name T438
Test name
Test status
Simulation time 2968864306 ps
CPU time 15.15 seconds
Started Mar 19 01:14:47 PM PDT 24
Finished Mar 19 01:15:02 PM PDT 24
Peak memory 239476 kb
Host smart-4edae4b0-ed1a-4bfd-a31e-680e96061797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590329974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3590329974
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2352119208
Short name T732
Test name
Test status
Simulation time 244459407 ps
CPU time 3.73 seconds
Started Mar 19 01:14:32 PM PDT 24
Finished Mar 19 01:14:36 PM PDT 24
Peak memory 217968 kb
Host smart-3a7d25e6-2443-4f26-8ec2-2661136ece05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352119208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2352119208
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1391996788
Short name T459
Test name
Test status
Simulation time 1020796224 ps
CPU time 4.39 seconds
Started Mar 19 01:14:45 PM PDT 24
Finished Mar 19 01:14:50 PM PDT 24
Peak memory 234540 kb
Host smart-106b8b1b-aca2-47da-a3e2-9084192dd9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391996788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1391996788
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1473824119
Short name T612
Test name
Test status
Simulation time 4486634356 ps
CPU time 4.24 seconds
Started Mar 19 01:14:31 PM PDT 24
Finished Mar 19 01:14:36 PM PDT 24
Peak memory 218024 kb
Host smart-5694ef75-8f50-4a60-88df-0e00c505f1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473824119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1473824119
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2609674766
Short name T857
Test name
Test status
Simulation time 1775159121 ps
CPU time 7.2 seconds
Started Mar 19 01:14:47 PM PDT 24
Finished Mar 19 01:14:54 PM PDT 24
Peak memory 232856 kb
Host smart-2fb40203-b514-4b42-b833-016fbbfda980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609674766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2609674766
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.1041393372
Short name T476
Test name
Test status
Simulation time 15647487 ps
CPU time 0.76 seconds
Started Mar 19 01:14:31 PM PDT 24
Finished Mar 19 01:14:32 PM PDT 24
Peak memory 215780 kb
Host smart-a2d37539-a467-4700-bdd9-0434188825ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041393372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.1041393372
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3059197972
Short name T961
Test name
Test status
Simulation time 206825898 ps
CPU time 4.33 seconds
Started Mar 19 01:14:40 PM PDT 24
Finished Mar 19 01:14:44 PM PDT 24
Peak memory 221600 kb
Host smart-fa90c5d1-8d84-4cf7-92a5-03161a05b1a8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3059197972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3059197972
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1676316552
Short name T69
Test name
Test status
Simulation time 90945936 ps
CPU time 1 seconds
Started Mar 19 01:14:39 PM PDT 24
Finished Mar 19 01:14:40 PM PDT 24
Peak memory 205072 kb
Host smart-03d80501-7552-4f47-9081-a09507da304c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676316552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1676316552
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3545195690
Short name T94
Test name
Test status
Simulation time 1802788153 ps
CPU time 17.58 seconds
Started Mar 19 01:14:33 PM PDT 24
Finished Mar 19 01:14:52 PM PDT 24
Peak memory 215784 kb
Host smart-067d66ad-6877-4241-96ff-9d98ba9d59d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545195690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3545195690
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.610484631
Short name T602
Test name
Test status
Simulation time 35269144954 ps
CPU time 22.61 seconds
Started Mar 19 01:14:47 PM PDT 24
Finished Mar 19 01:15:09 PM PDT 24
Peak memory 215524 kb
Host smart-d3950481-af42-4d1b-b4e8-92010ca4edff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610484631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.610484631
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2106605159
Short name T614
Test name
Test status
Simulation time 119204896 ps
CPU time 6.36 seconds
Started Mar 19 01:14:29 PM PDT 24
Finished Mar 19 01:14:36 PM PDT 24
Peak memory 215900 kb
Host smart-857a04d4-a114-4b51-a22d-21c35590f110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106605159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2106605159
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.6482693
Short name T14
Test name
Test status
Simulation time 86358065 ps
CPU time 0.75 seconds
Started Mar 19 01:14:33 PM PDT 24
Finished Mar 19 01:14:33 PM PDT 24
Peak memory 205308 kb
Host smart-b254dca7-4082-47bd-8bdb-cf3fab0bffc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6482693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.6482693
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.1016972223
Short name T302
Test name
Test status
Simulation time 185859101 ps
CPU time 2.67 seconds
Started Mar 19 01:14:31 PM PDT 24
Finished Mar 19 01:14:34 PM PDT 24
Peak memory 215916 kb
Host smart-59e8732a-d053-4000-8c2c-3a4e26d9faae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016972223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1016972223
Directory /workspace/9.spi_device_upload/latest
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