SPI_DEVICE/1R1W Simulation Results

Tuesday March 19 2024 19:02:40 UTC

GitHub Revision: `f7fc348358`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 93166527750821992054916907919379261408154533955814283538537589225972237641118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	11.845m	453.377ms	49	50	98.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.560s	220.955us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.880s	1.452ms	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	36.770s	1.907ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	24.880s	2.164ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.940s	160.670us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.880s	1.452ms	20	20	100.00
		spi_device_csr_aliasing	24.880s	2.164ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.710s	12.899us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.210s	71.424us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	csb_read	spi_device_csb_read	0.870s	15.419us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.740s	2.519us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.810s	17.962us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	12.690s	778.533us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	12.690s	778.533us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	33.930s	13.244ms	50	50	100.00
		spi_device_tpm_sts_read	1.150s	143.692us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.334m	29.112ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	1.030m	217.452ms	50	50	100.00
		spi_device_flash_all	8.288m	99.818ms	45	50	90.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	41.130s	53.129ms	50	50	100.00
		spi_device_flash_all	8.288m	99.818ms	45	50	90.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	41.130s	53.129ms	50	50	100.00
		spi_device_flash_all	8.288m	99.818ms	45	50	90.00
V2	cmd_info_slots	spi_device_flash_all	8.288m	99.818ms	45	50	90.00
V2	cmd_read_status	spi_device_intercept	15.520s	35.194ms	50	50	100.00
		spi_device_flash_all	8.288m	99.818ms	45	50	90.00
V2	cmd_read_jedec	spi_device_intercept	15.520s	35.194ms	50	50	100.00
		spi_device_flash_all	8.288m	99.818ms	45	50	90.00
V2	cmd_read_sfdp	spi_device_intercept	15.520s	35.194ms	50	50	100.00
		spi_device_flash_all	8.288m	99.818ms	45	50	90.00
V2	cmd_fast_read	spi_device_intercept	15.520s	35.194ms	50	50	100.00
		spi_device_flash_all	8.288m	99.818ms	45	50	90.00
V2	cmd_read_pipeline	spi_device_intercept	15.520s	35.194ms	50	50	100.00
		spi_device_flash_all	8.288m	99.818ms	45	50	90.00
V2	flash_cmd_upload	spi_device_upload	47.140s	28.701ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	43.520s	17.153ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	43.520s	17.153ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	43.520s	17.153ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.091m	12.887ms	49	50	98.00
		spi_device_read_buffer_direct	7.790s	3.387ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	43.520s	17.153ms	50	50	100.00
		spi_device_flash_all	8.288m	99.818ms	45	50	90.00
V2	quad_spi	spi_device_flash_all	8.288m	99.818ms	45	50	90.00
V2	dual_spi	spi_device_flash_all	8.288m	99.818ms	45	50	90.00
V2	4b_3b_feature	spi_device_cfg_cmd	8.560s	8.741ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	8.560s	8.741ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.845m	453.377ms	49	50	98.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.403m	72.828ms	50	50	100.00
V2	stress_all	spi_device_stress_all	14.369m	1.966s	49	50	98.00
V2	alert_test	spi_device_alert_test	0.770s	37.011us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.880s	14.888us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.830s	238.484us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.830s	238.484us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.560s	220.955us	5	5	100.00
		spi_device_csr_rw	2.880s	1.452ms	20	20	100.00
		spi_device_csr_aliasing	24.880s	2.164ms	5	5	100.00
		spi_device_same_csr_outstanding	5.020s	688.041us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.560s	220.955us	5	5	100.00
		spi_device_csr_rw	2.880s	1.452ms	20	20	100.00
		spi_device_csr_aliasing	24.880s	2.164ms	5	5	100.00
		spi_device_same_csr_outstanding	5.020s	688.041us	20	20	100.00
V2		TOTAL			953	980	97.24
V2S	tl_intg_err	spi_device_sec_cm	1.280s	677.322us	5	5	100.00
		spi_device_tl_intg_err	22.200s	11.291ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.200s	11.291ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1092	1120	97.50

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	22	22	18	81.82
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.95	98.32	94.35	98.61	89.36	97.00	95.84	98.17

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.87299694789743658642422985186305633583830160846064900998766551307571952528702
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1209887 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[7])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1209887 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1209887 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[903])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.3571448899083289085494770174492015593944153879731848850753094344824315248278
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   2725195 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[37])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   2725195 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   2725195 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[933])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (spi_device_pass_base_vseq.sv:643) [spi_device_flash_all_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 4 failures:

Test spi_device_flash_all has 4 failures.

15.spi_device_flash_all.27307197747171761701432981371151373402238879237754804175828181286267823501734
Line 263, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/15.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 5172004975 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 5174902729 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 14/16
  UVM_INFO @ 5879790844 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 15/16
  UVM_INFO @ 6354756964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.spi_device_flash_all.66538706159253358122147054563311261153105644692647311338729067183444506761249
Line 265, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/18.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 5156830158 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 5285324260 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 16/18
  UVM_INFO @ 5500650158 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 17/18
  UVM_INFO @ 6003750158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (spi_device_scoreboard.sv:1070) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}} has 2 failures:

Test spi_device_stress_all has 1 failures.

14.spi_device_stress_all.79369075500424927499145509190595141856544133006951575928015862047685019745516
Line 254, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/14.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 9444346666 ps: (spi_device_scoreboard.sv:1070) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x84a29c) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_INFO @ 75329709352 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 1/10
  UVM_INFO @ 97437115816 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 2/13
  UVM_INFO @ 104062028221 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 2/10
  UVM_INFO @ 163748049505 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 3/13

Test spi_device_flash_all has 1 failures.

21.spi_device_flash_all.45356252680767578265674273259356333782876267996757853128113151367893780279975
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/21.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 1000887138 ps: (spi_device_scoreboard.sv:1070) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x9eee5c) != exp '{'{other_status:'h27bb97, wel:'h0, busy:'h1}}
  UVM_INFO @ 3675605569 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 1/18
  UVM_INFO @ 6565107015 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 2/18
  UVM_INFO @ 9769363659 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 3/18
  UVM_INFO @ 13184297691 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 4/18

UVM_ERROR (spi_device_scoreboard.sv:492) scoreboard [scoreboard] flash_status mismatch, backdoor value: *, exp: * has 1 failures:

Test spi_device_flash_and_tpm has 1 failures.

27.spi_device_flash_and_tpm.66015820101051993095877223517553627940533254039327582610820261308903734778232
Line 255, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/27.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 4134970837 ps: (spi_device_scoreboard.sv:492) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] flash_status mismatch, backdoor value: 0x3bfd6d, exp: 0x3bfd6c
  UVM_ERROR @ 4135209966 ps: (spi_device_scoreboard.sv:1070) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x3bfd6d) != exp '{'{other_status:'heff5b, wel:'h0, busy:'h0}}
  UVM_ERROR @ 4135209966 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 5137943080 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 4/7
  UVM_INFO @ 5898503734 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 5/7

UVM_FATAL (spi_device_scoreboard.sv:921) [scoreboard] timeout occurred! has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 28.spi_device_flash_mode.73978016331461312363108371532872400429668403847591380849382465469987174407139
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/28.spi_device_flash_mode/latest/run.log
```
  UVM_FATAL @ 37016199217 ps: (spi_device_scoreboard.sv:921) [uvm_test_top.env.scoreboard] timeout occurred!
  UVM_INFO @ 37016199217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Past Results

Latest