SPI_DEVICE/1R1W Simulation Results

Saturday February 08 2025 05:05:54 UTC

GitHub Revision: 9f20940d49

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88344288495849993302635329522992994622996067932062874150778031027723701018040

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	10.899m	258.145ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.200s	51.961us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.620s	108.458us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	45.700s	749.839us	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	20.770s	2.508ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.120s	75.299us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.620s	108.458us	20	20	100.00
		spi_device_csr_aliasing	20.770s	2.508ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.050s	14.000us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.760s	45.229us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.230s	99.355us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.110s	4.717us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.740s	34.974us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	12.950s	1.214ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	12.950s	1.214ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	39.950s	11.046ms	50	50	100.00
		spi_device_tpm_sts_read	1.840s	137.159us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.207m	17.746ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	1.114m	13.442ms	50	50	100.00
		spi_device_flash_all	10.840m	350.653ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	1.048m	11.040ms	50	50	100.00
		spi_device_flash_all	10.840m	350.653ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	1.048m	11.040ms	50	50	100.00
		spi_device_flash_all	10.840m	350.653ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	10.840m	350.653ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	36.800s	2.260ms	50	50	100.00
		spi_device_flash_all	10.840m	350.653ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	36.800s	2.260ms	50	50	100.00
		spi_device_flash_all	10.840m	350.653ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	36.800s	2.260ms	50	50	100.00
		spi_device_flash_all	10.840m	350.653ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	36.800s	2.260ms	50	50	100.00
		spi_device_flash_all	10.840m	350.653ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	36.800s	2.260ms	50	50	100.00
		spi_device_flash_all	10.840m	350.653ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	1.054m	14.507ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.353m	257.941ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.353m	257.941ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.353m	257.941ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.272m	12.537ms	50	50	100.00
		spi_device_read_buffer_direct	28.490s	2.293ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.353m	257.941ms	50	50	100.00
		spi_device_flash_all	10.840m	350.653ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	10.840m	350.653ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	10.840m	350.653ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	37.550s	2.851ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	37.550s	2.851ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	10.899m	258.145ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.665m	261.235ms	50	50	100.00
V2	stress_all	spi_device_stress_all	17.491m	83.842ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.170s	15.034us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.190s	62.440us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	9.030s	1.156ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	9.030s	1.156ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.200s	51.961us	5	5	100.00
		spi_device_csr_rw	3.620s	108.458us	20	20	100.00
		spi_device_csr_aliasing	20.770s	2.508ms	5	5	100.00
		spi_device_same_csr_outstanding	5.360s	147.676us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.200s	51.961us	5	5	100.00
		spi_device_csr_rw	3.620s	108.458us	20	20	100.00
		spi_device_csr_aliasing	20.770s	2.508ms	5	5	100.00
		spi_device_same_csr_outstanding	5.360s	147.676us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.750s	251.293us	5	5	100.00
		spi_device_tl_intg_err	27.320s	796.896us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	27.320s	796.896us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	9.224m	216.106ms	50	50	100.00
		TOTAL			1131	1151	98.26

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	98.38	93.99	98.62	89.36	97.19	95.45	99.26

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:
  • Test spi_device_mem_parity has 20 failures.

    • 0.spi_device_mem_parity.13093105492684671407440547997748381316783783712766883794061540570416369588138
      Line 63, in log /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1780430 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[19])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1780430 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1780430 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[915])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • 1.spi_device_mem_parity.56535044244814010253735376673270084277706970793221327927435869943814156293767
      Line 63, in log /workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1252141 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[107])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1252141 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1252141 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[1003])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • ... and 18 more failures.

Past Results

• Latest
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• 2024.10.13_03.42.12
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