SPI_DEVICE/1R1W Simulation Results

Monday October 14 2024 17:26:15 UTC

GitHub Revision: 12e3b8572e

Branch: os_regression_2024_10_14

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85025606402499621082521464627961092918263397067038954055071960501195381950243

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	12.325m	121.754ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.020s	83.802us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	4.030s	391.563us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	37.090s	7.210ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	24.530s	913.208us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	6.220s	103.545us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	4.030s	391.563us	20	20	100.00
		spi_device_csr_aliasing	24.530s	913.208us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.060s	18.929us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.640s	73.060us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.290s	40.898us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.110s	6.909us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	1.180s	72.033us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	10.300s	688.180us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.300s	688.180us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	50.280s	8.948ms	50	50	100.00
		spi_device_tpm_sts_read	1.630s	87.503us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.032m	5.181ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	57.000s	14.950ms	50	50	100.00
		spi_device_flash_all	10.004m	320.983ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	40.880s	14.810ms	50	50	100.00
		spi_device_flash_all	10.004m	320.983ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	40.880s	14.810ms	50	50	100.00
		spi_device_flash_all	10.004m	320.983ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	10.004m	320.983ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	47.480s	3.981ms	50	50	100.00
		spi_device_flash_all	10.004m	320.983ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	47.480s	3.981ms	50	50	100.00
		spi_device_flash_all	10.004m	320.983ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	47.480s	3.981ms	50	50	100.00
		spi_device_flash_all	10.004m	320.983ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	47.480s	3.981ms	50	50	100.00
		spi_device_flash_all	10.004m	320.983ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	47.480s	3.981ms	50	50	100.00
		spi_device_flash_all	10.004m	320.983ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	43.170s	7.451ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	3.134m	77.867ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	3.134m	77.867ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	3.134m	77.867ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.332m	11.109ms	50	50	100.00
		spi_device_read_buffer_direct	29.310s	3.845ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	3.134m	77.867ms	50	50	100.00
		spi_device_flash_all	10.004m	320.983ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	10.004m	320.983ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	10.004m	320.983ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	23.500s	7.307ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	23.500s	7.307ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.325m	121.754ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	12.185m	58.921ms	50	50	100.00
V2	stress_all	spi_device_stress_all	19.695m	175.907ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.160s	24.050us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.200s	12.485us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	9.000s	1.022ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	9.000s	1.022ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.020s	83.802us	5	5	100.00
		spi_device_csr_rw	4.030s	391.563us	20	20	100.00
		spi_device_csr_aliasing	24.530s	913.208us	5	5	100.00
		spi_device_same_csr_outstanding	6.400s	205.480us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.020s	83.802us	5	5	100.00
		spi_device_csr_rw	4.030s	391.563us	20	20	100.00
		spi_device_csr_aliasing	24.530s	913.208us	5	5	100.00
		spi_device_same_csr_outstanding	6.400s	205.480us	20	20	100.00
V2		TOTAL			941	961	97.92
V2S	tl_intg_err	spi_device_sec_cm	1.960s	328.679us	5	5	100.00
		spi_device_tl_intg_err	24.330s	1.924ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	24.330s	1.924ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	8.092m	49.719ms	50	50	100.00
		TOTAL			1131	1151	98.26

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	21	95.45
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.74	98.65	96.80	99.01	89.36	98.51	95.57	99.26

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:
  • Test spi_device_mem_parity has 20 failures.

    • 0.spi_device_mem_parity.80297505961858528928420933749144917190641161205286549761717056728113719172113
      Line 63, in log /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   4648372 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[15])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4648372 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   4648372 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[911])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • 1.spi_device_mem_parity.5926414933140750786570465958845489040875301775247313324736216087567731320700
      Line 63, in log /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   3091576 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[53])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   3091576 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   3091576 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[949])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • ... and 18 more failures.

Past Results

• Latest
• 2024.10.13_03.42.12
• 2024.10.10_10.18.32
• 2024.10.04_00.45.23
• 2024.09.25_11.04.25
• 2024.09.19_09.08.05
• 2024.09.12_10.19.43
• 2024.09.10_08.14.27