Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7693065	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7696780

1

T1

16338

T2

4107

T3

4508

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	10158033	1			T1	8134		T2	9173		T3	4137
values[0x0]	2614537	1			T1	7415		T2	1962		T3	1243
values[0x1]	2617275	1			T1	7323		T2	1970		T3	1191

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5564891	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9824954

1

T1

18056

T2

6898

T3

4933

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	59354	1			T1	79		T2	86		T3	31
valid_sources[0x01]	60434	1			T1	23		T3	21		T8	1321
valid_sources[0x02]	60772	1			T1	26		T3	36		T6	2
valid_sources[0x03]	57612	1			T1	11		T3	35		T6	1
valid_sources[0x04]	62449	1			T1	16		T3	29		T6	6
valid_sources[0x05]	66896	1			T1	93		T3	21		T6	2
valid_sources[0x06]	57095	1			T1	70		T3	7		T6	2
valid_sources[0x07]	57896	1			T1	53		T2	75		T3	35
valid_sources[0x08]	63144	1			T1	3		T3	52		T6	4
valid_sources[0x09]	59196	1			T1	8		T3	22		T6	9
valid_sources[0x0a]	62558	1			T1	9		T3	42		T6	4
valid_sources[0x0b]	60251	1			T1	127		T3	12		T6	1
valid_sources[0x0c]	59591	1			T1	9		T3	18		T6	4
valid_sources[0x0d]	57400	1			T1	7		T3	23		T6	4
valid_sources[0x0e]	60986	1			T1	104		T2	1034		T3	14
valid_sources[0x0f]	62283	1			T1	1		T3	41		T6	4
valid_sources[0x10]	62419	1			T1	222		T3	23		T6	3
valid_sources[0x11]	58556	1			T1	3		T3	27		T6	4
valid_sources[0x12]	59969	1			T1	468		T3	28		T6	1
valid_sources[0x13]	57542	1			T1	9		T3	12		T6	2
valid_sources[0x14]	59232	1			T3	16		T6	2		T8	2
valid_sources[0x15]	60024	1			T1	124		T3	33		T8	31
valid_sources[0x16]	59935	1			T1	77		T2	728		T3	36
valid_sources[0x17]	72245	1			T1	2		T3	29		T6	12
valid_sources[0x18]	56575	1			T1	176		T3	32		T6	5
valid_sources[0x19]	65822	1			T1	5		T2	1220		T3	36
valid_sources[0x1a]	61177	1			T1	82		T3	37		T6	3
valid_sources[0x1b]	61011	1			T1	512		T3	19		T6	4
valid_sources[0x1c]	56930	1			T1	173		T3	45		T6	5
valid_sources[0x1d]	62567	1			T1	6		T3	20		T6	7
valid_sources[0x1e]	63246	1			T1	15		T3	21		T6	2
valid_sources[0x1f]	57465	1			T1	80		T3	36		T6	2
valid_sources[0x20]	59014	1			T1	67		T3	33		T6	2
valid_sources[0x21]	68303	1			T1	76		T2	884		T3	26
valid_sources[0x22]	60464	1			T1	27		T3	23		T6	3
valid_sources[0x23]	60937	1			T1	2		T3	32		T6	3
valid_sources[0x24]	60765	1			T1	464		T3	10		T6	7
valid_sources[0x25]	57691	1			T1	35		T3	43		T6	1
valid_sources[0x26]	60458	1			T1	5		T2	46		T3	18
valid_sources[0x27]	57586	1			T1	74		T3	26		T6	6
valid_sources[0x28]	59047	1			T1	43		T3	21		T6	3
valid_sources[0x29]	61290	1			T1	18		T3	34		T5	914
valid_sources[0x2a]	65882	1			T1	124		T3	7		T6	10
valid_sources[0x2b]	60479	1			T1	54		T2	237		T3	30
valid_sources[0x2c]	67853	1			T1	64		T3	29		T6	1
valid_sources[0x2d]	59102	1			T1	60		T3	4		T9	2
valid_sources[0x2e]	62492	1			T1	55		T3	29		T6	6
valid_sources[0x2f]	57629	1			T1	61		T2	5		T3	18
valid_sources[0x30]	64778	1			T1	4		T3	32		T9	6
valid_sources[0x31]	58811	1			T1	112		T3	31		T6	3
valid_sources[0x32]	62326	1			T1	126		T3	35		T6	3
valid_sources[0x33]	59260	1			T3	26		T6	3		T8	83
valid_sources[0x34]	58556	1			T1	16		T3	11		T6	7
valid_sources[0x35]	60775	1			T1	10		T3	18		T6	1
valid_sources[0x36]	59709	1			T1	2		T3	18		T8	2
valid_sources[0x37]	64864	1			T1	35		T3	20		T8	1
valid_sources[0x38]	57518	1			T1	75		T2	203		T3	32
valid_sources[0x39]	61694	1			T1	2		T3	38		T6	1
valid_sources[0x3a]	60805	1			T1	190		T2	1		T3	44
valid_sources[0x3b]	62403	1			T1	4		T3	34		T6	4
valid_sources[0x3c]	62654	1			T1	119		T3	11		T6	5
valid_sources[0x3d]	56850	1			T1	10		T3	17		T6	4
valid_sources[0x3e]	61698	1			T1	133		T3	29		T6	3
valid_sources[0x3f]	61509	1			T1	95		T3	33		T6	2
valid_sources[0x40]	57985	1			T1	94		T3	24		T6	2
valid_sources[0x41]	56103	1			T1	3		T3	8		T6	9
valid_sources[0x42]	63308	1			T1	1		T3	13		T6	10
valid_sources[0x43]	56125	1			T1	4		T3	23		T6	5
valid_sources[0x44]	58530	1			T1	1		T3	18		T6	1
valid_sources[0x45]	59681	1			T1	36		T3	32		T6	1
valid_sources[0x46]	59793	1			T1	83		T3	36		T6	8
valid_sources[0x47]	59528	1			T1	58		T3	29		T6	6
valid_sources[0x48]	59396	1			T1	119		T2	99		T3	22
valid_sources[0x49]	61758	1			T1	1		T3	44		T6	5
valid_sources[0x4a]	56559	1			T1	1		T3	24		T6	2
valid_sources[0x4b]	62834	1			T1	5		T3	23		T6	3
valid_sources[0x4c]	55791	1			T1	8		T3	21		T6	5
valid_sources[0x4d]	58736	1			T1	49		T3	17		T6	3
valid_sources[0x4e]	61945	1			T1	59		T3	13		T6	1
valid_sources[0x4f]	58021	1			T1	143		T2	181		T3	39
valid_sources[0x50]	63816	1			T1	55		T3	12		T6	1
valid_sources[0x51]	57841	1			T1	167		T3	29		T6	1
valid_sources[0x52]	62714	1			T1	24		T3	46		T6	1
valid_sources[0x53]	59875	1			T1	7		T3	20		T6	3
valid_sources[0x54]	59199	1			T1	4		T3	29		T6	5
valid_sources[0x55]	58554	1			T1	26		T2	940		T3	19
valid_sources[0x56]	65371	1			T1	27		T3	29		T6	8
valid_sources[0x57]	65283	1			T1	56		T3	17		T6	2
valid_sources[0x58]	57009	1			T1	26		T3	12		T6	2
valid_sources[0x59]	61032	1			T1	4		T3	20		T6	3
valid_sources[0x5a]	57496	1			T1	91		T3	18		T6	3
valid_sources[0x5b]	58751	1			T1	125		T3	22		T6	4
valid_sources[0x5c]	59048	1			T1	23		T3	14		T9	3
valid_sources[0x5d]	61308	1			T1	143		T3	16		T4	906
valid_sources[0x5e]	56461	1			T1	82		T3	14		T6	3
valid_sources[0x5f]	56657	1			T1	36		T3	37		T6	1
valid_sources[0x60]	57734	1			T1	482		T3	34		T6	5
valid_sources[0x61]	62686	1			T1	3		T3	16		T6	7
valid_sources[0x62]	60590	1			T1	4		T2	776		T3	21
valid_sources[0x63]	59503	1			T1	62		T3	50		T8	1
valid_sources[0x64]	60054	1			T1	230		T2	1		T3	28
valid_sources[0x65]	59311	1			T1	565		T3	18		T6	7
valid_sources[0x66]	56973	1			T1	40		T2	29		T3	18
valid_sources[0x67]	62364	1			T1	27		T3	38		T6	9
valid_sources[0x68]	61960	1			T1	59		T2	475		T3	42
valid_sources[0x69]	60266	1			T1	60		T2	1065		T3	29
valid_sources[0x6a]	59496	1			T1	53		T3	21		T6	3
valid_sources[0x6b]	58535	1			T1	107		T3	46		T6	1
valid_sources[0x6c]	60594	1			T1	18		T3	59		T6	5
valid_sources[0x6d]	57075	1			T1	92		T2	1		T3	20
valid_sources[0x6e]	57890	1			T1	1		T3	14		T6	3
valid_sources[0x6f]	61256	1			T1	444		T3	30		T6	2
valid_sources[0x70]	60090	1			T1	10		T3	36		T8	2
valid_sources[0x71]	62000	1			T1	451		T3	28		T6	4
valid_sources[0x72]	58240	1			T1	8		T2	203		T3	19
valid_sources[0x73]	59121	1			T1	12		T3	47		T6	2
valid_sources[0x74]	62599	1			T3	9		T6	4		T8	3
valid_sources[0x75]	61863	1			T1	570		T2	188		T3	15
valid_sources[0x76]	57965	1			T1	22		T2	2		T3	16
valid_sources[0x77]	58221	1			T1	179		T3	27		T6	2
valid_sources[0x78]	60685	1			T1	25		T2	1		T3	13
valid_sources[0x79]	56762	1			T1	32		T3	15		T6	3
valid_sources[0x7a]	60412	1			T3	42		T6	2		T8	1
valid_sources[0x7b]	56639	1			T1	67		T3	14		T6	9
valid_sources[0x7c]	60986	1			T1	25		T3	14		T6	2
valid_sources[0x7d]	57548	1			T1	117		T3	24		T6	6
valid_sources[0x7e]	62443	1			T1	9		T3	8		T6	2
valid_sources[0x7f]	63590	1			T1	10		T2	3		T3	30
valid_sources[0x80]	59218	1			T1	29		T3	20		T6	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3034958

1

T1

2764

T2

1434

T3

2085

values[0x0]

all_enables

biggest_size

2348581

1

T1

6876

T2

1386

T3

1239

values[0x1]

all_enables

biggest_size

2313241

1

T1

6698

T2

1287

T3

1184