Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

7716191

1

T1

6534

T2

8998

T3

2063

full_word

7698063

1

T1

16338

T2

4107

T3

4508

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	15413834	1			T1	22872		T2	13105		T3	6571
auto[TlIntgErrCmd]	150	1			T56	5		T58	9		T89	10
auto[TlIntgErrData]	144	1			T56	9		T58	5		T89	11
auto[TlIntgErrBoth]	126	1			T56	6		T58	6		T89	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10161855

1

T1

8134

T2

9173

T3

4137

auto[1]

5252399

1

T1

14738

T2

3932

T3

2434

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7126385	1			T1	5370		T2	7739		T3	2052
auto[TlIntgErrNone]	partial	auto[1]	589419	1			T1	1164		T2	1259		T3	11
auto[TlIntgErrNone]	full_word	auto[0]	3035269	1			T1	2764		T2	1434		T3	2085
auto[TlIntgErrNone]	full_word	auto[1]	4662761	1			T1	13574		T2	2673		T3	2423
auto[TlIntgErrCmd]	partial	auto[0]	66	1			T56	3		T58	4		T89	4
auto[TlIntgErrCmd]	partial	auto[1]	69	1			T56	2		T58	5		T89	6
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T101	1		T130	1		T147	1
auto[TlIntgErrCmd]	full_word	auto[1]	12	1			T128	1		T129	1		T130	1
auto[TlIntgErrData]	partial	auto[0]	74	1			T56	3		T58	3		T89	3
auto[TlIntgErrData]	partial	auto[1]	59	1			T56	6		T58	2		T89	8
auto[TlIntgErrData]	full_word	auto[0]	6	1			T101	1		T92	1		T148	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T92	1		T148	1		T146	2
auto[TlIntgErrBoth]	partial	auto[0]	49	1			T56	1		T58	1		T89	4
auto[TlIntgErrBoth]	partial	auto[1]	70	1			T56	4		T58	5		T89	5
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T102	2		T128	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T56	1		T101	1		T92	1