Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	870190170	4124608	0	0
gen_wmask[1].MaskCheckPortA_A	870190170	4124608	0	0
gen_wmask[2].MaskCheckPortA_A	870190170	4124608	0	0
gen_wmask[3].MaskCheckPortA_A	870190170	4124608	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	870190170	4124608	0	0
T1	1366839	16328	0	0
T2	748579	5970	0	0
T3	551625	2368	0	0
T4	236679	832	0	0
T5	225566	832	0	0
T6	109011	832	0	0
T7	22093	832	0	0
T8	595497	4918	0	0
T9	704305	832	0	0
T10	1081769	17555	0	0
T11	0	10044	0	0
T13	0	65	0	0
T17	0	10362	0	0
T18	0	4990	0	0
T22	0	5275	0	0
T23	0	1241	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	870190170	4124608	0	0
T1	1366839	16328	0	0
T2	748579	5970	0	0
T3	551625	2368	0	0
T4	236679	832	0	0
T5	225566	832	0	0
T6	109011	832	0	0
T7	22093	832	0	0
T8	595497	4918	0	0
T9	704305	832	0	0
T10	1081769	17555	0	0
T11	0	10044	0	0
T13	0	65	0	0
T17	0	10362	0	0
T18	0	4990	0	0
T22	0	5275	0	0
T23	0	1241	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	870190170	4124608	0	0
T1	1366839	16328	0	0
T2	748579	5970	0	0
T3	551625	2368	0	0
T4	236679	832	0	0
T5	225566	832	0	0
T6	109011	832	0	0
T7	22093	832	0	0
T8	595497	4918	0	0
T9	704305	832	0	0
T10	1081769	17555	0	0
T11	0	10044	0	0
T13	0	65	0	0
T17	0	10362	0	0
T18	0	4990	0	0
T22	0	5275	0	0
T23	0	1241	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	870190170	4124608	0	0
T1	1366839	16328	0	0
T2	748579	5970	0	0
T3	551625	2368	0	0
T4	236679	832	0	0
T5	225566	832	0	0
T6	109011	832	0	0
T7	22093	832	0	0
T8	595497	4918	0	0
T9	704305	832	0	0
T10	1081769	17555	0	0
T11	0	10044	0	0
T13	0	65	0	0
T17	0	10362	0	0
T18	0	4990	0	0
T22	0	5275	0	0
T23	0	1241	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	672570084	2700485	0	0
gen_wmask[1].MaskCheckPortA_A	672570084	2700485	0	0
gen_wmask[2].MaskCheckPortA_A	672570084	2700485	0	0
gen_wmask[3].MaskCheckPortA_A	672570084	2700485	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672570084	2700485	0	0
T1	375330	11379	0	0
T2	599463	1275	0	0
T3	460614	2368	0	0
T4	124326	832	0	0
T5	201756	832	0	0
T6	97217	832	0	0
T7	12760	832	0	0
T8	516048	3328	0	0
T9	626481	832	0	0
T10	412759	7488	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672570084	2700485	0	0
T1	375330	11379	0	0
T2	599463	1275	0	0
T3	460614	2368	0	0
T4	124326	832	0	0
T5	201756	832	0	0
T6	97217	832	0	0
T7	12760	832	0	0
T8	516048	3328	0	0
T9	626481	832	0	0
T10	412759	7488	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672570084	2700485	0	0
T1	375330	11379	0	0
T2	599463	1275	0	0
T3	460614	2368	0	0
T4	124326	832	0	0
T5	201756	832	0	0
T6	97217	832	0	0
T7	12760	832	0	0
T8	516048	3328	0	0
T9	626481	832	0	0
T10	412759	7488	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672570084	2700485	0	0
T1	375330	11379	0	0
T2	599463	1275	0	0
T3	460614	2368	0	0
T4	124326	832	0	0
T5	201756	832	0	0
T6	97217	832	0	0
T7	12760	832	0	0
T8	516048	3328	0	0
T9	626481	832	0	0
T10	412759	7488	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	197620086	1424123	0	0
gen_wmask[1].MaskCheckPortA_A	197620086	1424123	0	0
gen_wmask[2].MaskCheckPortA_A	197620086	1424123	0	0
gen_wmask[3].MaskCheckPortA_A	197620086	1424123	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197620086	1424123	0	0
T1	991509	4949	0	0
T2	149116	4695	0	0
T3	91011	0	0	0
T4	112353	0	0	0
T5	23810	0	0	0
T6	11794	0	0	0
T7	9333	0	0	0
T8	79449	1590	0	0
T9	77824	0	0	0
T10	669010	10067	0	0
T11	0	10044	0	0
T13	0	65	0	0
T17	0	10362	0	0
T18	0	4990	0	0
T22	0	5275	0	0
T23	0	1241	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197620086	1424123	0	0
T1	991509	4949	0	0
T2	149116	4695	0	0
T3	91011	0	0	0
T4	112353	0	0	0
T5	23810	0	0	0
T6	11794	0	0	0
T7	9333	0	0	0
T8	79449	1590	0	0
T9	77824	0	0	0
T10	669010	10067	0	0
T11	0	10044	0	0
T13	0	65	0	0
T17	0	10362	0	0
T18	0	4990	0	0
T22	0	5275	0	0
T23	0	1241	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197620086	1424123	0	0
T1	991509	4949	0	0
T2	149116	4695	0	0
T3	91011	0	0	0
T4	112353	0	0	0
T5	23810	0	0	0
T6	11794	0	0	0
T7	9333	0	0	0
T8	79449	1590	0	0
T9	77824	0	0	0
T10	669010	10067	0	0
T11	0	10044	0	0
T13	0	65	0	0
T17	0	10362	0	0
T18	0	4990	0	0
T22	0	5275	0	0
T23	0	1241	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197620086	1424123	0	0
T1	991509	4949	0	0
T2	149116	4695	0	0
T3	91011	0	0	0
T4	112353	0	0	0
T5	23810	0	0	0
T6	11794	0	0	0
T7	9333	0	0	0
T8	79449	1590	0	0
T9	77824	0	0	0
T10	669010	10067	0	0
T11	0	10044	0	0
T13	0	65	0	0
T17	0	10362	0	0
T18	0	4990	0	0
T22	0	5275	0	0
T23	0	1241	0	0