Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.fifo_h.reqfifo

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	675073030	17911866	0	0
DepthKnown_A	675073030	674942163	0	0
RvalidKnown_A	675073030	674942163	0	0
WreadyKnown_A	675073030	674942163	0	0
gen_passthru_fifo.paramCheckPass	1095	1095	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675073030	17911866	0	0
T1	375330	33497	0	0
T2	599463	13187	0	0
T3	460614	8110	0	0
T4	124326	906	0	0
T5	201756	914	0	0
T6	97217	1711	0	0
T7	12760	1711	0	0
T8	516048	11183	0	0
T9	626481	1721	0	0
T10	412759	18293	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675073030	674942163	0	0
T1	375330	375196	0	0
T2	599463	599409	0	0
T3	460614	460534	0	0
T4	124326	124246	0	0
T5	201756	201689	0	0
T6	97217	97165	0	0
T7	12760	12680	0	0
T8	516048	515985	0	0
T9	626481	626409	0	0
T10	412759	412679	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675073030	674942163	0	0
T1	375330	375196	0	0
T2	599463	599409	0	0
T3	460614	460534	0	0
T4	124326	124246	0	0
T5	201756	201689	0	0
T6	97217	97165	0	0
T7	12760	12680	0	0
T8	516048	515985	0	0
T9	626481	626409	0	0
T10	412759	412679	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675073030	674942163	0	0
T1	375330	375196	0	0
T2	599463	599409	0	0
T3	460614	460534	0	0
T4	124326	124246	0	0
T5	201756	201689	0	0
T6	97217	97165	0	0
T7	12760	12680	0	0
T8	516048	515985	0	0
T9	626481	626409	0	0
T10	412759	412679	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095	1095	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	675073030	35877517	0	0
DepthKnown_A	675073030	674942163	0	0
RvalidKnown_A	675073030	674942163	0	0
WreadyKnown_A	675073030	674942163	0	0
gen_passthru_fifo.paramCheckPass	1095	1095	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675073030	35877517	0	0
T1	375330	56335	0	0
T2	599463	13105	0	0
T3	460614	6571	0	0
T4	124326	906	0	0
T5	201756	4175	0	0
T6	97217	880	0	0
T7	12760	917	0	0
T8	516048	25023	0	0
T9	626481	890	0	0
T10	412759	38502	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675073030	674942163	0	0
T1	375330	375196	0	0
T2	599463	599409	0	0
T3	460614	460534	0	0
T4	124326	124246	0	0
T5	201756	201689	0	0
T6	97217	97165	0	0
T7	12760	12680	0	0
T8	516048	515985	0	0
T9	626481	626409	0	0
T10	412759	412679	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675073030	674942163	0	0
T1	375330	375196	0	0
T2	599463	599409	0	0
T3	460614	460534	0	0
T4	124326	124246	0	0
T5	201756	201689	0	0
T6	97217	97165	0	0
T7	12760	12680	0	0
T8	516048	515985	0	0
T9	626481	626409	0	0
T10	412759	412679	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675073030	674942163	0	0
T1	375330	375196	0	0
T2	599463	599409	0	0
T3	460614	460534	0	0
T4	124326	124246	0	0
T5	201756	201689	0	0
T6	97217	97165	0	0
T7	12760	12680	0	0
T8	516048	515985	0	0
T9	626481	626409	0	0
T10	412759	412679	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095	1095	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	675073030	3732606	0	0
DepthKnown_A	675073030	674942163	0	0
RvalidKnown_A	675073030	674942163	0	0
WreadyKnown_A	675073030	674942163	0	0
gen_passthru_fifo.paramCheckPass	1095	1095	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675073030	3732606	0	0
T1	375330	16650	0	0
T2	599463	0	0	0
T3	460614	3898	0	0
T4	124326	832	0	0
T5	201756	832	0	0
T6	97217	1663	0	0
T7	12760	1663	0	0
T8	516048	4996	0	0
T9	626481	1663	0	0
T10	412759	12480	0	0
T11	0	25815	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675073030	674942163	0	0
T1	375330	375196	0	0
T2	599463	599409	0	0
T3	460614	460534	0	0
T4	124326	124246	0	0
T5	201756	201689	0	0
T6	97217	97165	0	0
T7	12760	12680	0	0
T8	516048	515985	0	0
T9	626481	626409	0	0
T10	412759	412679	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675073030	674942163	0	0
T1	375330	375196	0	0
T2	599463	599409	0	0
T3	460614	460534	0	0
T4	124326	124246	0	0
T5	201756	201689	0	0
T6	97217	97165	0	0
T7	12760	12680	0	0
T8	516048	515985	0	0
T9	626481	626409	0	0
T10	412759	412679	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675073030	674942163	0	0
T1	375330	375196	0	0
T2	599463	599409	0	0
T3	460614	460534	0	0
T4	124326	124246	0	0
T5	201756	201689	0	0
T6	97217	97165	0	0
T7	12760	12680	0	0
T8	516048	515985	0	0
T9	626481	626409	0	0
T10	412759	412679	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095	1095	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	675073030	3924096	0	0
DepthKnown_A	675073030	674942163	0	0
RvalidKnown_A	675073030	674942163	0	0
WreadyKnown_A	675073030	674942163	0	0
gen_passthru_fifo.paramCheckPass	1095	1095	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675073030	3924096	0	0
T1	375330	16956	0	0
T2	599463	0	0	0
T3	460614	2368	0	0
T4	124326	832	0	0
T5	201756	3795	0	0
T6	97217	832	0	0
T7	12760	832	0	0
T8	516048	6944	0	0
T9	626481	832	0	0
T10	412759	16269	0	0
T11	0	44383	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675073030	674942163	0	0
T1	375330	375196	0	0
T2	599463	599409	0	0
T3	460614	460534	0	0
T4	124326	124246	0	0
T5	201756	201689	0	0
T6	97217	97165	0	0
T7	12760	12680	0	0
T8	516048	515985	0	0
T9	626481	626409	0	0
T10	412759	412679	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675073030	674942163	0	0
T1	375330	375196	0	0
T2	599463	599409	0	0
T3	460614	460534	0	0
T4	124326	124246	0	0
T5	201756	201689	0	0
T6	97217	97165	0	0
T7	12760	12680	0	0
T8	516048	515985	0	0
T9	626481	626409	0	0
T10	412759	412679	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675073030	674942163	0	0
T1	375330	375196	0	0
T2	599463	599409	0	0
T3	460614	460534	0	0
T4	124326	124246	0	0
T5	201756	201689	0	0
T6	97217	97165	0	0
T7	12760	12680	0	0
T8	516048	515985	0	0
T9	626481	626409	0	0
T10	412759	412679	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095	1095	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	675073030	238380	0	0
DepthKnown_A	675073030	674942163	0	0
RvalidKnown_A	675073030	674942163	0	0
WreadyKnown_A	675073030	674942163	0	0
gen_passthru_fifo.paramCheckPass	1095	1095	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675073030	238380	0	0
T1	375330	829	0	0
T2	599463	1215	0	0
T3	460614	0	0	0
T4	124326	0	0	0
T5	201756	0	0	0
T6	97217	0	0	0
T7	12760	0	0	0
T8	516048	324	0	0
T9	626481	0	0	0
T10	412759	353	0	0
T11	0	1855	0	0
T13	0	17	0	0
T17	0	684	0	0
T18	0	1290	0	0
T22	0	289	0	0
T23	0	256	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675073030	674942163	0	0
T1	375330	375196	0	0
T2	599463	599409	0	0
T3	460614	460534	0	0
T4	124326	124246	0	0
T5	201756	201689	0	0
T6	97217	97165	0	0
T7	12760	12680	0	0
T8	516048	515985	0	0
T9	626481	626409	0	0
T10	412759	412679	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675073030	674942163	0	0
T1	375330	375196	0	0
T2	599463	599409	0	0
T3	460614	460534	0	0
T4	124326	124246	0	0
T5	201756	201689	0	0
T6	97217	97165	0	0
T7	12760	12680	0	0
T8	516048	515985	0	0
T9	626481	626409	0	0
T10	412759	412679	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675073030	674942163	0	0
T1	375330	375196	0	0
T2	599463	599409	0	0
T3	460614	460534	0	0
T4	124326	124246	0	0
T5	201756	201689	0	0
T6	97217	97165	0	0
T7	12760	12680	0	0
T8	516048	515985	0	0
T9	626481	626409	0	0
T10	412759	412679	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095	1095	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	675073030	581981	0	0
DepthKnown_A	675073030	674942163	0	0
RvalidKnown_A	675073030	674942163	0	0
WreadyKnown_A	675073030	674942163	0	0
gen_passthru_fifo.paramCheckPass	1095	1095	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675073030	581981	0	0
T1	375330	2504	0	0
T2	599463	1215	0	0
T3	460614	0	0	0
T4	124326	0	0	0
T5	201756	0	0	0
T6	97217	0	0	0
T7	12760	0	0	0
T8	516048	1006	0	0
T9	626481	0	0	0
T10	412759	1621	0	0
T11	0	8836	0	0
T13	0	17	0	0
T17	0	684	0	0
T18	0	1290	0	0
T22	0	289	0	0
T23	0	256	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675073030	674942163	0	0
T1	375330	375196	0	0
T2	599463	599409	0	0
T3	460614	460534	0	0
T4	124326	124246	0	0
T5	201756	201689	0	0
T6	97217	97165	0	0
T7	12760	12680	0	0
T8	516048	515985	0	0
T9	626481	626409	0	0
T10	412759	412679	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675073030	674942163	0	0
T1	375330	375196	0	0
T2	599463	599409	0	0
T3	460614	460534	0	0
T4	124326	124246	0	0
T5	201756	201689	0	0
T6	97217	97165	0	0
T7	12760	12680	0	0
T8	516048	515985	0	0
T9	626481	626409	0	0
T10	412759	412679	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675073030	674942163	0	0
T1	375330	375196	0	0
T2	599463	599409	0	0
T3	460614	460534	0	0
T4	124326	124246	0	0
T5	201756	201689	0	0
T6	97217	97165	0	0
T7	12760	12680	0	0
T8	516048	515985	0	0
T9	626481	626409	0	0
T10	412759	412679	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095	1095	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0