Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	675073030	13603145	0	0
DepthKnown_A	675073030	674942163	0	0
RvalidKnown_A	675073030	674942163	0	0
WreadyKnown_A	675073030	674942163	0	0
gen_passthru_fifo.paramCheckPass	1095	1095	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675073030	13603145	0	0
T1	375330	13631	0	0
T2	599463	11952	0	0
T3	460614	4207	0	0
T4	124326	74	0	0
T5	201756	82	0	0
T6	97217	48	0	0
T7	12760	48	0	0
T8	516048	5625	0	0
T9	626481	58	0	0
T10	412759	4815	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675073030	674942163	0	0
T1	375330	375196	0	0
T2	599463	599409	0	0
T3	460614	460534	0	0
T4	124326	124246	0	0
T5	201756	201689	0	0
T6	97217	97165	0	0
T7	12760	12680	0	0
T8	516048	515985	0	0
T9	626481	626409	0	0
T10	412759	412679	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675073030	674942163	0	0
T1	375330	375196	0	0
T2	599463	599409	0	0
T3	460614	460534	0	0
T4	124326	124246	0	0
T5	201756	201689	0	0
T6	97217	97165	0	0
T7	12760	12680	0	0
T8	516048	515985	0	0
T9	626481	626409	0	0
T10	412759	412679	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675073030	674942163	0	0
T1	375330	375196	0	0
T2	599463	599409	0	0
T3	460614	460534	0	0
T4	124326	124246	0	0
T5	201756	201689	0	0
T6	97217	97165	0	0
T7	12760	12680	0	0
T8	516048	515985	0	0
T9	626481	626409	0	0
T10	412759	412679	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095	1095	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	675073030	31371440	0	0
DepthKnown_A	675073030	674942163	0	0
RvalidKnown_A	675073030	674942163	0	0
WreadyKnown_A	675073030	674942163	0	0
gen_passthru_fifo.paramCheckPass	1095	1095	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675073030	31371440	0	0
T1	375330	36875	0	0
T2	599463	11890	0	0
T3	460614	4203	0	0
T4	124326	74	0	0
T5	201756	380	0	0
T6	97217	48	0	0
T7	12760	85	0	0
T8	516048	17073	0	0
T9	626481	58	0	0
T10	412759	20612	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675073030	674942163	0	0
T1	375330	375196	0	0
T2	599463	599409	0	0
T3	460614	460534	0	0
T4	124326	124246	0	0
T5	201756	201689	0	0
T6	97217	97165	0	0
T7	12760	12680	0	0
T8	516048	515985	0	0
T9	626481	626409	0	0
T10	412759	412679	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675073030	674942163	0	0
T1	375330	375196	0	0
T2	599463	599409	0	0
T3	460614	460534	0	0
T4	124326	124246	0	0
T5	201756	201689	0	0
T6	97217	97165	0	0
T7	12760	12680	0	0
T8	516048	515985	0	0
T9	626481	626409	0	0
T10	412759	412679	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	675073030	674942163	0	0
T1	375330	375196	0	0
T2	599463	599409	0	0
T3	460614	460534	0	0
T4	124326	124246	0	0
T5	201756	201689	0	0
T6	97217	97165	0	0
T7	12760	12680	0	0
T8	516048	515985	0	0
T9	626481	626409	0	0
T10	412759	412679	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1095	1095	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0