Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T12
1	0	Unreachable
1	1	Covered	T1,T2,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T8,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T10
1	0	Covered	T1,T8,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T1,T8,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1067810256	868169761	0	0
CheckNGreaterZero_A	2760	2760	0	0
GntImpliesReady_A	1067810256	4676189	0	0
GntImpliesValid_A	1067810256	4676189	0	0
GrantKnown_A	1067810256	868169761	0	0
IdxKnown_A	1067810256	868169761	0	0
IndexIsCorrect_A	1067810256	4676189	0	0
LockArbDecision_A	1067810256	0	0	0
NoReadyValidNoGrant_A	1067810256	0	0	0
ReadyAndValidImplyGrant_A	1067810256	4676189	0	0
ReqAndReadyImplyGrant_A	1067810256	4676189	0	0
ReqImpliesValid_A	1067810256	4676189	0	0
ReqStaysHighUntilGranted0_M	1067810256	0	0	0
RoundRobin_A	1067810256	14	0	920
ValidKnown_A	1067810256	868169761	0	0
gen_data_port_assertion.DataFlow_A	1067810256	4676189	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067810256	868169761	0	0
T1	2358348	1361752	0	0
T2	897695	743889	0	0
T3	642636	550724	0	0
T4	349032	235264	0	0
T5	249376	225475	0	0
T6	120805	108959	0	0
T7	31426	21832	0	0
T8	674946	594933	0	0
T9	782129	703929	0	0
T10	1750779	1079203	0	0
T11	0	1026980	0	0
T12	0	432	0	0
T13	0	2168	0	0
T14	0	88416	0	0
T17	0	8984	0	0
T18	0	776304	0	0
T38	0	61888	0	0
T39	0	230056	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2760	2760	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067810256	4676189	0	0
T1	2358348	18685	0	0
T2	897695	8587	0	0
T3	642636	2368	0	0
T4	349032	832	0	0
T5	249376	832	0	0
T6	120805	832	0	0
T7	31426	832	0	0
T8	674946	5274	0	0
T9	782129	832	0	0
T10	1750779	17934	0	0
T11	0	12514	0	0
T13	0	103	0	0
T17	0	10449	0	0
T18	0	8127	0	0
T22	0	5275	0	0
T23	0	1241	0	0
T26	0	14662	0	0
T39	0	5570	0	0
T40	0	2446	0	0
T41	0	6213	0	0
T42	0	5871	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067810256	4676189	0	0
T1	2358348	18685	0	0
T2	897695	8587	0	0
T3	642636	2368	0	0
T4	349032	832	0	0
T5	249376	832	0	0
T6	120805	832	0	0
T7	31426	832	0	0
T8	674946	5274	0	0
T9	782129	832	0	0
T10	1750779	17934	0	0
T11	0	12514	0	0
T13	0	103	0	0
T17	0	10449	0	0
T18	0	8127	0	0
T22	0	5275	0	0
T23	0	1241	0	0
T26	0	14662	0	0
T39	0	5570	0	0
T40	0	2446	0	0
T41	0	6213	0	0
T42	0	5871	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067810256	868169761	0	0
T1	2358348	1361752	0	0
T2	897695	743889	0	0
T3	642636	550724	0	0
T4	349032	235264	0	0
T5	249376	225475	0	0
T6	120805	108959	0	0
T7	31426	21832	0	0
T8	674946	594933	0	0
T9	782129	703929	0	0
T10	1750779	1079203	0	0
T11	0	1026980	0	0
T12	0	432	0	0
T13	0	2168	0	0
T14	0	88416	0	0
T17	0	8984	0	0
T18	0	776304	0	0
T38	0	61888	0	0
T39	0	230056	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067810256	868169761	0	0
T1	2358348	1361752	0	0
T2	897695	743889	0	0
T3	642636	550724	0	0
T4	349032	235264	0	0
T5	249376	225475	0	0
T6	120805	108959	0	0
T7	31426	21832	0	0
T8	674946	594933	0	0
T9	782129	703929	0	0
T10	1750779	1079203	0	0
T11	0	1026980	0	0
T12	0	432	0	0
T13	0	2168	0	0
T14	0	88416	0	0
T17	0	8984	0	0
T18	0	776304	0	0
T38	0	61888	0	0
T39	0	230056	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067810256	4676189	0	0
T1	2358348	18685	0	0
T2	897695	8587	0	0
T3	642636	2368	0	0
T4	349032	832	0	0
T5	249376	832	0	0
T6	120805	832	0	0
T7	31426	832	0	0
T8	674946	5274	0	0
T9	782129	832	0	0
T10	1750779	17934	0	0
T11	0	12514	0	0
T13	0	103	0	0
T17	0	10449	0	0
T18	0	8127	0	0
T22	0	5275	0	0
T23	0	1241	0	0
T26	0	14662	0	0
T39	0	5570	0	0
T40	0	2446	0	0
T41	0	6213	0	0
T42	0	5871	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067810256	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067810256	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067810256	4676189	0	0
T1	2358348	18685	0	0
T2	897695	8587	0	0
T3	642636	2368	0	0
T4	349032	832	0	0
T5	249376	832	0	0
T6	120805	832	0	0
T7	31426	832	0	0
T8	674946	5274	0	0
T9	782129	832	0	0
T10	1750779	17934	0	0
T11	0	12514	0	0
T13	0	103	0	0
T17	0	10449	0	0
T18	0	8127	0	0
T22	0	5275	0	0
T23	0	1241	0	0
T26	0	14662	0	0
T39	0	5570	0	0
T40	0	2446	0	0
T41	0	6213	0	0
T42	0	5871	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067810256	4676189	0	0
T1	2358348	18685	0	0
T2	897695	8587	0	0
T3	642636	2368	0	0
T4	349032	832	0	0
T5	249376	832	0	0
T6	120805	832	0	0
T7	31426	832	0	0
T8	674946	5274	0	0
T9	782129	832	0	0
T10	1750779	17934	0	0
T11	0	12514	0	0
T13	0	103	0	0
T17	0	10449	0	0
T18	0	8127	0	0
T22	0	5275	0	0
T23	0	1241	0	0
T26	0	14662	0	0
T39	0	5570	0	0
T40	0	2446	0	0
T41	0	6213	0	0
T42	0	5871	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067810256	4676189	0	0
T1	2358348	18685	0	0
T2	897695	8587	0	0
T3	642636	2368	0	0
T4	349032	832	0	0
T5	249376	832	0	0
T6	120805	832	0	0
T7	31426	832	0	0
T8	674946	5274	0	0
T9	782129	832	0	0
T10	1750779	17934	0	0
T11	0	12514	0	0
T13	0	103	0	0
T17	0	10449	0	0
T18	0	8127	0	0
T22	0	5275	0	0
T23	0	1241	0	0
T26	0	14662	0	0
T39	0	5570	0	0
T40	0	2446	0	0
T41	0	6213	0	0
T42	0	5871	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067810256	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067810256	14	0	920
T11	110432	1	0	1
T14	693730	0	0	1
T15	1941	0	0	1
T16	1904	0	0	1
T22	144367	0	0	1
T25	574813	0	0	1
T32	103179	0	0	1
T33	147044	0	0	1
T34	33150	0	0	1
T35	60354	0	0	1
T43	0	2	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067810256	868169761	0	0
T1	2358348	1361752	0	0
T2	897695	743889	0	0
T3	642636	550724	0	0
T4	349032	235264	0	0
T5	249376	225475	0	0
T6	120805	108959	0	0
T7	31426	21832	0	0
T8	674946	594933	0	0
T9	782129	703929	0	0
T10	1750779	1079203	0	0
T11	0	1026980	0	0
T12	0	432	0	0
T13	0	2168	0	0
T14	0	88416	0	0
T17	0	8984	0	0
T18	0	776304	0	0
T38	0	61888	0	0
T39	0	230056	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1067810256	4676189	0	0
T1	2358348	18685	0	0
T2	897695	8587	0	0
T3	642636	2368	0	0
T4	349032	832	0	0
T5	249376	832	0	0
T6	120805	832	0	0
T7	31426	832	0	0
T8	674946	5274	0	0
T9	782129	832	0	0
T10	1750779	17934	0	0
T11	0	12514	0	0
T13	0	103	0	0
T17	0	10449	0	0
T18	0	8127	0	0
T22	0	5275	0	0
T23	0	1241	0	0
T26	0	14662	0	0
T39	0	5570	0	0
T40	0	2446	0	0
T41	0	6213	0	0
T42	0	5871	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T12
1	0	Unreachable
1	1	Covered	T1,T2,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T13
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T12

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T13
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	197620086	39867475	0	0
CheckNGreaterZero_A	920	920	0	0
GntImpliesReady_A	197620086	957057	0	0
GntImpliesValid_A	197620086	957057	0	0
GrantKnown_A	197620086	39867475	0	0
IdxKnown_A	197620086	39867475	0	0
IndexIsCorrect_A	197620086	957057	0	0
LockArbDecision_A	197620086	0	0	0
NoReadyValidNoGrant_A	197620086	0	0	0
ReadyAndValidImplyGrant_A	197620086	957057	0	0
ReqAndReadyImplyGrant_A	197620086	957057	0	0
ReqImpliesValid_A	197620086	957057	0	0
ReqStaysHighUntilGranted0_M	197620086	0	0	0
RoundRobin_A	197620086	0	0	0
ValidKnown_A	197620086	39867475	0	0
gen_data_port_assertion.DataFlow_A	197620086	957057	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197620086	39867475	0	0
T1	991509	371768	0	0
T2	149116	144480	0	0
T3	91011	0	0	0
T4	112353	0	0	0
T5	23810	0	0	0
T6	11794	0	0	0
T7	9333	0	0	0
T8	79449	0	0	0
T9	77824	0	0	0
T10	669010	0	0	0
T11	0	282336	0	0
T12	0	432	0	0
T13	0	2168	0	0
T14	0	88416	0	0
T17	0	8984	0	0
T18	0	776304	0	0
T38	0	61888	0	0
T39	0	230056	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	920	920	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197620086	957057	0	0
T1	991509	4450	0	0
T2	149116	6097	0	0
T3	91011	0	0	0
T4	112353	0	0	0
T5	23810	0	0	0
T6	11794	0	0	0
T7	9333	0	0	0
T8	79449	0	0	0
T9	77824	0	0	0
T10	669010	0	0	0
T11	0	6897	0	0
T13	0	103	0	0
T17	0	251	0	0
T18	0	8125	0	0
T26	0	8656	0	0
T39	0	5570	0	0
T41	0	6213	0	0
T42	0	5871	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197620086	957057	0	0
T1	991509	4450	0	0
T2	149116	6097	0	0
T3	91011	0	0	0
T4	112353	0	0	0
T5	23810	0	0	0
T6	11794	0	0	0
T7	9333	0	0	0
T8	79449	0	0	0
T9	77824	0	0	0
T10	669010	0	0	0
T11	0	6897	0	0
T13	0	103	0	0
T17	0	251	0	0
T18	0	8125	0	0
T26	0	8656	0	0
T39	0	5570	0	0
T41	0	6213	0	0
T42	0	5871	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197620086	39867475	0	0
T1	991509	371768	0	0
T2	149116	144480	0	0
T3	91011	0	0	0
T4	112353	0	0	0
T5	23810	0	0	0
T6	11794	0	0	0
T7	9333	0	0	0
T8	79449	0	0	0
T9	77824	0	0	0
T10	669010	0	0	0
T11	0	282336	0	0
T12	0	432	0	0
T13	0	2168	0	0
T14	0	88416	0	0
T17	0	8984	0	0
T18	0	776304	0	0
T38	0	61888	0	0
T39	0	230056	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197620086	39867475	0	0
T1	991509	371768	0	0
T2	149116	144480	0	0
T3	91011	0	0	0
T4	112353	0	0	0
T5	23810	0	0	0
T6	11794	0	0	0
T7	9333	0	0	0
T8	79449	0	0	0
T9	77824	0	0	0
T10	669010	0	0	0
T11	0	282336	0	0
T12	0	432	0	0
T13	0	2168	0	0
T14	0	88416	0	0
T17	0	8984	0	0
T18	0	776304	0	0
T38	0	61888	0	0
T39	0	230056	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197620086	957057	0	0
T1	991509	4450	0	0
T2	149116	6097	0	0
T3	91011	0	0	0
T4	112353	0	0	0
T5	23810	0	0	0
T6	11794	0	0	0
T7	9333	0	0	0
T8	79449	0	0	0
T9	77824	0	0	0
T10	669010	0	0	0
T11	0	6897	0	0
T13	0	103	0	0
T17	0	251	0	0
T18	0	8125	0	0
T26	0	8656	0	0
T39	0	5570	0	0
T41	0	6213	0	0
T42	0	5871	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197620086	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197620086	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197620086	957057	0	0
T1	991509	4450	0	0
T2	149116	6097	0	0
T3	91011	0	0	0
T4	112353	0	0	0
T5	23810	0	0	0
T6	11794	0	0	0
T7	9333	0	0	0
T8	79449	0	0	0
T9	77824	0	0	0
T10	669010	0	0	0
T11	0	6897	0	0
T13	0	103	0	0
T17	0	251	0	0
T18	0	8125	0	0
T26	0	8656	0	0
T39	0	5570	0	0
T41	0	6213	0	0
T42	0	5871	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197620086	957057	0	0
T1	991509	4450	0	0
T2	149116	6097	0	0
T3	91011	0	0	0
T4	112353	0	0	0
T5	23810	0	0	0
T6	11794	0	0	0
T7	9333	0	0	0
T8	79449	0	0	0
T9	77824	0	0	0
T10	669010	0	0	0
T11	0	6897	0	0
T13	0	103	0	0
T17	0	251	0	0
T18	0	8125	0	0
T26	0	8656	0	0
T39	0	5570	0	0
T41	0	6213	0	0
T42	0	5871	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197620086	957057	0	0
T1	991509	4450	0	0
T2	149116	6097	0	0
T3	91011	0	0	0
T4	112353	0	0	0
T5	23810	0	0	0
T6	11794	0	0	0
T7	9333	0	0	0
T8	79449	0	0	0
T9	77824	0	0	0
T10	669010	0	0	0
T11	0	6897	0	0
T13	0	103	0	0
T17	0	251	0	0
T18	0	8125	0	0
T26	0	8656	0	0
T39	0	5570	0	0
T41	0	6213	0	0
T42	0	5871	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	197620086	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197620086	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197620086	39867475	0	0
T1	991509	371768	0	0
T2	149116	144480	0	0
T3	91011	0	0	0
T4	112353	0	0	0
T5	23810	0	0	0
T6	11794	0	0	0
T7	9333	0	0	0
T8	79449	0	0	0
T9	77824	0	0	0
T10	669010	0	0	0
T11	0	282336	0	0
T12	0	432	0	0
T13	0	2168	0	0
T14	0	88416	0	0
T17	0	8984	0	0
T18	0	776304	0	0
T38	0	61888	0	0
T39	0	230056	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197620086	957057	0	0
T1	991509	4450	0	0
T2	149116	6097	0	0
T3	91011	0	0	0
T4	112353	0	0	0
T5	23810	0	0	0
T6	11794	0	0	0
T7	9333	0	0	0
T8	79449	0	0	0
T9	77824	0	0	0
T10	669010	0	0	0
T11	0	6897	0	0
T13	0	103	0	0
T17	0	251	0	0
T18	0	8125	0	0
T26	0	8656	0	0
T39	0	5570	0	0
T41	0	6213	0	0
T42	0	5871	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T8,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T10
1	0	Covered	T1,T8,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T1,T8,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T8,T10
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	197620086	155817311	0	0
CheckNGreaterZero_A	920	920	0	0
GntImpliesReady_A	197620086	783176	0	0
GntImpliesValid_A	197620086	783176	0	0
GrantKnown_A	197620086	155817311	0	0
IdxKnown_A	197620086	155817311	0	0
IndexIsCorrect_A	197620086	783176	0	0
LockArbDecision_A	197620086	0	0	0
NoReadyValidNoGrant_A	197620086	0	0	0
ReadyAndValidImplyGrant_A	197620086	783176	0	0
ReqAndReadyImplyGrant_A	197620086	783176	0	0
ReqImpliesValid_A	197620086	783176	0	0
ReqStaysHighUntilGranted0_M	197620086	0	0	0
RoundRobin_A	197620086	0	0	0
ValidKnown_A	197620086	155817311	0	0
gen_data_port_assertion.DataFlow_A	197620086	783176	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197620086	155817311	0	0
T1	991509	614788	0	0
T2	149116	0	0	0
T3	91011	90190	0	0
T4	112353	111018	0	0
T5	23810	23786	0	0
T6	11794	11794	0	0
T7	9333	9152	0	0
T8	79449	78948	0	0
T9	77824	77520	0	0
T10	669010	666524	0	0
T11	0	744644	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	920	920	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197620086	783176	0	0
T1	991509	2027	0	0
T2	149116	0	0	0
T3	91011	0	0	0
T4	112353	0	0	0
T5	23810	0	0	0
T6	11794	0	0	0
T7	9333	0	0	0
T8	79449	1590	0	0
T9	77824	0	0	0
T10	669010	10067	0	0
T11	0	5617	0	0
T17	0	10198	0	0
T18	0	2	0	0
T22	0	5275	0	0
T23	0	1241	0	0
T26	0	6006	0	0
T40	0	2446	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197620086	783176	0	0
T1	991509	2027	0	0
T2	149116	0	0	0
T3	91011	0	0	0
T4	112353	0	0	0
T5	23810	0	0	0
T6	11794	0	0	0
T7	9333	0	0	0
T8	79449	1590	0	0
T9	77824	0	0	0
T10	669010	10067	0	0
T11	0	5617	0	0
T17	0	10198	0	0
T18	0	2	0	0
T22	0	5275	0	0
T23	0	1241	0	0
T26	0	6006	0	0
T40	0	2446	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197620086	155817311	0	0
T1	991509	614788	0	0
T2	149116	0	0	0
T3	91011	90190	0	0
T4	112353	111018	0	0
T5	23810	23786	0	0
T6	11794	11794	0	0
T7	9333	9152	0	0
T8	79449	78948	0	0
T9	77824	77520	0	0
T10	669010	666524	0	0
T11	0	744644	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197620086	155817311	0	0
T1	991509	614788	0	0
T2	149116	0	0	0
T3	91011	90190	0	0
T4	112353	111018	0	0
T5	23810	23786	0	0
T6	11794	11794	0	0
T7	9333	9152	0	0
T8	79449	78948	0	0
T9	77824	77520	0	0
T10	669010	666524	0	0
T11	0	744644	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197620086	783176	0	0
T1	991509	2027	0	0
T2	149116	0	0	0
T3	91011	0	0	0
T4	112353	0	0	0
T5	23810	0	0	0
T6	11794	0	0	0
T7	9333	0	0	0
T8	79449	1590	0	0
T9	77824	0	0	0
T10	669010	10067	0	0
T11	0	5617	0	0
T17	0	10198	0	0
T18	0	2	0	0
T22	0	5275	0	0
T23	0	1241	0	0
T26	0	6006	0	0
T40	0	2446	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197620086	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197620086	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197620086	783176	0	0
T1	991509	2027	0	0
T2	149116	0	0	0
T3	91011	0	0	0
T4	112353	0	0	0
T5	23810	0	0	0
T6	11794	0	0	0
T7	9333	0	0	0
T8	79449	1590	0	0
T9	77824	0	0	0
T10	669010	10067	0	0
T11	0	5617	0	0
T17	0	10198	0	0
T18	0	2	0	0
T22	0	5275	0	0
T23	0	1241	0	0
T26	0	6006	0	0
T40	0	2446	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197620086	783176	0	0
T1	991509	2027	0	0
T2	149116	0	0	0
T3	91011	0	0	0
T4	112353	0	0	0
T5	23810	0	0	0
T6	11794	0	0	0
T7	9333	0	0	0
T8	79449	1590	0	0
T9	77824	0	0	0
T10	669010	10067	0	0
T11	0	5617	0	0
T17	0	10198	0	0
T18	0	2	0	0
T22	0	5275	0	0
T23	0	1241	0	0
T26	0	6006	0	0
T40	0	2446	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197620086	783176	0	0
T1	991509	2027	0	0
T2	149116	0	0	0
T3	91011	0	0	0
T4	112353	0	0	0
T5	23810	0	0	0
T6	11794	0	0	0
T7	9333	0	0	0
T8	79449	1590	0	0
T9	77824	0	0	0
T10	669010	10067	0	0
T11	0	5617	0	0
T17	0	10198	0	0
T18	0	2	0	0
T22	0	5275	0	0
T23	0	1241	0	0
T26	0	6006	0	0
T40	0	2446	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	197620086	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197620086	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197620086	155817311	0	0
T1	991509	614788	0	0
T2	149116	0	0	0
T3	91011	90190	0	0
T4	112353	111018	0	0
T5	23810	23786	0	0
T6	11794	11794	0	0
T7	9333	9152	0	0
T8	79449	78948	0	0
T9	77824	77520	0	0
T10	669010	666524	0	0
T11	0	744644	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197620086	783176	0	0
T1	991509	2027	0	0
T2	149116	0	0	0
T3	91011	0	0	0
T4	112353	0	0	0
T5	23810	0	0	0
T6	11794	0	0	0
T7	9333	0	0	0
T8	79449	1590	0	0
T9	77824	0	0	0
T10	669010	10067	0	0
T11	0	5617	0	0
T17	0	10198	0	0
T18	0	2	0	0
T22	0	5275	0	0
T23	0	1241	0	0
T26	0	6006	0	0
T40	0	2446	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	672570084	672484975	0	0
CheckNGreaterZero_A	920	920	0	0
GntImpliesReady_A	672570084	2935956	0	0
GntImpliesValid_A	672570084	2935956	0	0
GrantKnown_A	672570084	672484975	0	0
IdxKnown_A	672570084	672484975	0	0
IndexIsCorrect_A	672570084	2935956	0	0
LockArbDecision_A	672570084	0	0	0
NoReadyValidNoGrant_A	672570084	0	0	0
ReadyAndValidImplyGrant_A	672570084	2935956	0	0
ReqAndReadyImplyGrant_A	672570084	2935956	0	0
ReqImpliesValid_A	672570084	2935956	0	0
ReqStaysHighUntilGranted0_M	672570084	0	0	0
RoundRobin_A	672570084	14	0	920
ValidKnown_A	672570084	672484975	0	0
gen_data_port_assertion.DataFlow_A	672570084	2935956	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672570084	672484975	0	0
T1	375330	375196	0	0
T2	599463	599409	0	0
T3	460614	460534	0	0
T4	124326	124246	0	0
T5	201756	201689	0	0
T6	97217	97165	0	0
T7	12760	12680	0	0
T8	516048	515985	0	0
T9	626481	626409	0	0
T10	412759	412679	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	920	920	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672570084	2935956	0	0
T1	375330	12208	0	0
T2	599463	2490	0	0
T3	460614	2368	0	0
T4	124326	832	0	0
T5	201756	832	0	0
T6	97217	832	0	0
T7	12760	832	0	0
T8	516048	3684	0	0
T9	626481	832	0	0
T10	412759	7867	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672570084	2935956	0	0
T1	375330	12208	0	0
T2	599463	2490	0	0
T3	460614	2368	0	0
T4	124326	832	0	0
T5	201756	832	0	0
T6	97217	832	0	0
T7	12760	832	0	0
T8	516048	3684	0	0
T9	626481	832	0	0
T10	412759	7867	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672570084	672484975	0	0
T1	375330	375196	0	0
T2	599463	599409	0	0
T3	460614	460534	0	0
T4	124326	124246	0	0
T5	201756	201689	0	0
T6	97217	97165	0	0
T7	12760	12680	0	0
T8	516048	515985	0	0
T9	626481	626409	0	0
T10	412759	412679	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672570084	672484975	0	0
T1	375330	375196	0	0
T2	599463	599409	0	0
T3	460614	460534	0	0
T4	124326	124246	0	0
T5	201756	201689	0	0
T6	97217	97165	0	0
T7	12760	12680	0	0
T8	516048	515985	0	0
T9	626481	626409	0	0
T10	412759	412679	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672570084	2935956	0	0
T1	375330	12208	0	0
T2	599463	2490	0	0
T3	460614	2368	0	0
T4	124326	832	0	0
T5	201756	832	0	0
T6	97217	832	0	0
T7	12760	832	0	0
T8	516048	3684	0	0
T9	626481	832	0	0
T10	412759	7867	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672570084	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672570084	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672570084	2935956	0	0
T1	375330	12208	0	0
T2	599463	2490	0	0
T3	460614	2368	0	0
T4	124326	832	0	0
T5	201756	832	0	0
T6	97217	832	0	0
T7	12760	832	0	0
T8	516048	3684	0	0
T9	626481	832	0	0
T10	412759	7867	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672570084	2935956	0	0
T1	375330	12208	0	0
T2	599463	2490	0	0
T3	460614	2368	0	0
T4	124326	832	0	0
T5	201756	832	0	0
T6	97217	832	0	0
T7	12760	832	0	0
T8	516048	3684	0	0
T9	626481	832	0	0
T10	412759	7867	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672570084	2935956	0	0
T1	375330	12208	0	0
T2	599463	2490	0	0
T3	460614	2368	0	0
T4	124326	832	0	0
T5	201756	832	0	0
T6	97217	832	0	0
T7	12760	832	0	0
T8	516048	3684	0	0
T9	626481	832	0	0
T10	412759	7867	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	672570084	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672570084	14	0	920
T11	110432	1	0	1
T14	693730	0	0	1
T15	1941	0	0	1
T16	1904	0	0	1
T22	144367	0	0	1
T25	574813	0	0	1
T32	103179	0	0	1
T33	147044	0	0	1
T34	33150	0	0	1
T35	60354	0	0	1
T43	0	2	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672570084	672484975	0	0
T1	375330	375196	0	0
T2	599463	599409	0	0
T3	460614	460534	0	0
T4	124326	124246	0	0
T5	201756	201689	0	0
T6	97217	97165	0	0
T7	12760	12680	0	0
T8	516048	515985	0	0
T9	626481	626409	0	0
T10	412759	412679	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672570084	2935956	0	0
T1	375330	12208	0	0
T2	599463	2490	0	0
T3	460614	2368	0	0
T4	124326	832	0	0
T5	201756	832	0	0
T6	97217	832	0	0
T7	12760	832	0	0
T8	516048	3684	0	0
T9	626481	832	0	0
T10	412759	7867	0	0