Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
3458 |
0 |
0 |
T56 |
19255 |
3 |
0 |
0 |
T57 |
2867 |
135 |
0 |
0 |
T58 |
20091 |
3 |
0 |
0 |
T87 |
7661 |
4 |
0 |
0 |
T88 |
15096 |
4 |
0 |
0 |
T89 |
77657 |
2 |
0 |
0 |
T90 |
4554 |
188 |
0 |
0 |
T92 |
81901 |
5 |
0 |
0 |
T101 |
99075 |
1 |
0 |
0 |
T102 |
79386 |
2 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
2420 |
0 |
0 |
T78 |
3226 |
10 |
0 |
0 |
T88 |
15096 |
21 |
0 |
0 |
T101 |
99075 |
113 |
0 |
0 |
T107 |
5973 |
6 |
0 |
0 |
T113 |
71749 |
454 |
0 |
0 |
T127 |
12616 |
15 |
0 |
0 |
T128 |
34616 |
14 |
0 |
0 |
T129 |
35808 |
44 |
0 |
0 |
T130 |
68306 |
77 |
0 |
0 |
T131 |
16044 |
28 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
2394 |
0 |
0 |
T78 |
3226 |
9 |
0 |
0 |
T88 |
15096 |
38 |
0 |
0 |
T101 |
99075 |
112 |
0 |
0 |
T107 |
5973 |
8 |
0 |
0 |
T113 |
71749 |
459 |
0 |
0 |
T114 |
9766 |
7 |
0 |
0 |
T127 |
12616 |
23 |
0 |
0 |
T128 |
34616 |
16 |
0 |
0 |
T129 |
35808 |
54 |
0 |
0 |
T130 |
68306 |
85 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
2852 |
0 |
0 |
T78 |
3226 |
11 |
0 |
0 |
T88 |
15096 |
36 |
0 |
0 |
T101 |
99075 |
228 |
0 |
0 |
T107 |
5973 |
38 |
0 |
0 |
T113 |
71749 |
438 |
0 |
0 |
T114 |
9766 |
6 |
0 |
0 |
T127 |
12616 |
12 |
0 |
0 |
T128 |
34616 |
31 |
0 |
0 |
T129 |
35808 |
77 |
0 |
0 |
T130 |
68306 |
154 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
10687 |
0 |
0 |
T78 |
3226 |
9 |
0 |
0 |
T88 |
15096 |
262 |
0 |
0 |
T101 |
99075 |
1764 |
0 |
0 |
T107 |
5973 |
3 |
0 |
0 |
T113 |
71749 |
380 |
0 |
0 |
T114 |
9766 |
6 |
0 |
0 |
T127 |
12616 |
19 |
0 |
0 |
T128 |
34616 |
216 |
0 |
0 |
T129 |
35808 |
742 |
0 |
0 |
T130 |
68306 |
1372 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
12199 |
0 |
0 |
T78 |
3226 |
6 |
0 |
0 |
T88 |
15096 |
31 |
0 |
0 |
T101 |
99075 |
2032 |
0 |
0 |
T107 |
5973 |
1 |
0 |
0 |
T113 |
71749 |
452 |
0 |
0 |
T114 |
9766 |
137 |
0 |
0 |
T127 |
12616 |
60 |
0 |
0 |
T128 |
34616 |
439 |
0 |
0 |
T129 |
35808 |
937 |
0 |
0 |
T130 |
68306 |
1495 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
11350 |
0 |
0 |
T78 |
3226 |
7 |
0 |
0 |
T88 |
15096 |
128 |
0 |
0 |
T101 |
99075 |
1870 |
0 |
0 |
T107 |
5973 |
8 |
0 |
0 |
T113 |
71749 |
467 |
0 |
0 |
T114 |
9766 |
133 |
0 |
0 |
T127 |
12616 |
27 |
0 |
0 |
T128 |
34616 |
473 |
0 |
0 |
T129 |
35808 |
541 |
0 |
0 |
T130 |
68306 |
1257 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
12213 |
0 |
0 |
T78 |
3226 |
13 |
0 |
0 |
T88 |
15096 |
161 |
0 |
0 |
T101 |
99075 |
2047 |
0 |
0 |
T107 |
5973 |
8 |
0 |
0 |
T113 |
71749 |
451 |
0 |
0 |
T114 |
9766 |
98 |
0 |
0 |
T127 |
12616 |
83 |
0 |
0 |
T128 |
34616 |
523 |
0 |
0 |
T129 |
35808 |
634 |
0 |
0 |
T130 |
68306 |
2023 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
10652 |
0 |
0 |
T78 |
3226 |
11 |
0 |
0 |
T88 |
15096 |
158 |
0 |
0 |
T101 |
99075 |
1629 |
0 |
0 |
T107 |
5973 |
162 |
0 |
0 |
T113 |
71749 |
455 |
0 |
0 |
T114 |
9766 |
47 |
0 |
0 |
T127 |
12616 |
39 |
0 |
0 |
T128 |
34616 |
457 |
0 |
0 |
T129 |
35808 |
674 |
0 |
0 |
T130 |
68306 |
1336 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
9609 |
0 |
0 |
T78 |
3226 |
5 |
0 |
0 |
T88 |
15096 |
293 |
0 |
0 |
T101 |
99075 |
1660 |
0 |
0 |
T107 |
5973 |
4 |
0 |
0 |
T113 |
71749 |
416 |
0 |
0 |
T114 |
9766 |
142 |
0 |
0 |
T127 |
12616 |
42 |
0 |
0 |
T128 |
34616 |
381 |
0 |
0 |
T129 |
35808 |
620 |
0 |
0 |
T130 |
68306 |
807 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
11223 |
0 |
0 |
T78 |
3226 |
8 |
0 |
0 |
T88 |
15096 |
372 |
0 |
0 |
T101 |
99075 |
2582 |
0 |
0 |
T107 |
5973 |
135 |
0 |
0 |
T113 |
71749 |
444 |
0 |
0 |
T114 |
9766 |
78 |
0 |
0 |
T127 |
12616 |
24 |
0 |
0 |
T128 |
34616 |
339 |
0 |
0 |
T129 |
35808 |
976 |
0 |
0 |
T130 |
68306 |
1202 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
11023 |
0 |
0 |
T78 |
3226 |
4 |
0 |
0 |
T88 |
15096 |
24 |
0 |
0 |
T101 |
99075 |
2091 |
0 |
0 |
T107 |
5973 |
9 |
0 |
0 |
T113 |
71749 |
412 |
0 |
0 |
T114 |
9766 |
189 |
0 |
0 |
T127 |
12616 |
14 |
0 |
0 |
T128 |
34616 |
310 |
0 |
0 |
T129 |
35808 |
636 |
0 |
0 |
T130 |
68306 |
1474 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
5563 |
0 |
0 |
T78 |
3226 |
15 |
0 |
0 |
T88 |
15096 |
82 |
0 |
0 |
T95 |
11670 |
5 |
0 |
0 |
T101 |
99075 |
790 |
0 |
0 |
T107 |
5973 |
14 |
0 |
0 |
T113 |
71749 |
473 |
0 |
0 |
T114 |
9766 |
37 |
0 |
0 |
T127 |
12616 |
34 |
0 |
0 |
T128 |
34616 |
95 |
0 |
0 |
T129 |
35808 |
374 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
5105 |
0 |
0 |
T78 |
3226 |
6 |
0 |
0 |
T88 |
15096 |
22 |
0 |
0 |
T101 |
99075 |
494 |
0 |
0 |
T107 |
5973 |
38 |
0 |
0 |
T113 |
71749 |
437 |
0 |
0 |
T114 |
9766 |
12 |
0 |
0 |
T127 |
12616 |
24 |
0 |
0 |
T128 |
34616 |
173 |
0 |
0 |
T129 |
35808 |
382 |
0 |
0 |
T130 |
68306 |
451 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
6228 |
0 |
0 |
T78 |
3226 |
9 |
0 |
0 |
T88 |
15096 |
94 |
0 |
0 |
T101 |
99075 |
819 |
0 |
0 |
T107 |
5973 |
87 |
0 |
0 |
T113 |
71749 |
442 |
0 |
0 |
T114 |
9766 |
14 |
0 |
0 |
T127 |
12616 |
13 |
0 |
0 |
T128 |
34616 |
91 |
0 |
0 |
T129 |
35808 |
404 |
0 |
0 |
T130 |
68306 |
594 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
5439 |
0 |
0 |
T78 |
3226 |
9 |
0 |
0 |
T88 |
15096 |
93 |
0 |
0 |
T101 |
99075 |
621 |
0 |
0 |
T107 |
5973 |
10 |
0 |
0 |
T113 |
71749 |
476 |
0 |
0 |
T114 |
9766 |
88 |
0 |
0 |
T127 |
12616 |
6 |
0 |
0 |
T128 |
34616 |
227 |
0 |
0 |
T129 |
35808 |
259 |
0 |
0 |
T130 |
68306 |
601 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
5428 |
0 |
0 |
T88 |
15096 |
10 |
0 |
0 |
T101 |
99075 |
687 |
0 |
0 |
T107 |
5973 |
69 |
0 |
0 |
T113 |
71749 |
387 |
0 |
0 |
T114 |
9766 |
45 |
0 |
0 |
T127 |
12616 |
28 |
0 |
0 |
T128 |
34616 |
133 |
0 |
0 |
T129 |
35808 |
369 |
0 |
0 |
T130 |
68306 |
429 |
0 |
0 |
T131 |
16044 |
115 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
5367 |
0 |
0 |
T78 |
3226 |
9 |
0 |
0 |
T88 |
15096 |
57 |
0 |
0 |
T101 |
99075 |
632 |
0 |
0 |
T107 |
5973 |
45 |
0 |
0 |
T113 |
71749 |
404 |
0 |
0 |
T114 |
9766 |
44 |
0 |
0 |
T127 |
12616 |
14 |
0 |
0 |
T128 |
34616 |
162 |
0 |
0 |
T129 |
35808 |
341 |
0 |
0 |
T130 |
68306 |
554 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
5687 |
0 |
0 |
T78 |
3226 |
12 |
0 |
0 |
T88 |
15096 |
124 |
0 |
0 |
T101 |
99075 |
707 |
0 |
0 |
T107 |
5973 |
55 |
0 |
0 |
T113 |
71749 |
403 |
0 |
0 |
T114 |
9766 |
8 |
0 |
0 |
T127 |
12616 |
20 |
0 |
0 |
T128 |
34616 |
114 |
0 |
0 |
T129 |
35808 |
339 |
0 |
0 |
T130 |
68306 |
609 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
5995 |
0 |
0 |
T78 |
3226 |
7 |
0 |
0 |
T88 |
15096 |
203 |
0 |
0 |
T101 |
99075 |
808 |
0 |
0 |
T107 |
5973 |
15 |
0 |
0 |
T113 |
71749 |
421 |
0 |
0 |
T114 |
9766 |
19 |
0 |
0 |
T127 |
12616 |
40 |
0 |
0 |
T128 |
34616 |
247 |
0 |
0 |
T129 |
35808 |
258 |
0 |
0 |
T130 |
68306 |
572 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
5740 |
0 |
0 |
T78 |
3226 |
8 |
0 |
0 |
T88 |
15096 |
75 |
0 |
0 |
T101 |
99075 |
788 |
0 |
0 |
T107 |
5973 |
77 |
0 |
0 |
T113 |
71749 |
478 |
0 |
0 |
T114 |
9766 |
46 |
0 |
0 |
T127 |
12616 |
61 |
0 |
0 |
T128 |
34616 |
152 |
0 |
0 |
T129 |
35808 |
169 |
0 |
0 |
T130 |
68306 |
474 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
5728 |
0 |
0 |
T78 |
3226 |
10 |
0 |
0 |
T88 |
15096 |
11 |
0 |
0 |
T101 |
99075 |
884 |
0 |
0 |
T107 |
5973 |
2 |
0 |
0 |
T113 |
71749 |
433 |
0 |
0 |
T127 |
12616 |
53 |
0 |
0 |
T128 |
34616 |
222 |
0 |
0 |
T129 |
35808 |
310 |
0 |
0 |
T130 |
68306 |
649 |
0 |
0 |
T131 |
16044 |
9 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
6003 |
0 |
0 |
T78 |
3226 |
13 |
0 |
0 |
T88 |
15096 |
164 |
0 |
0 |
T101 |
99075 |
849 |
0 |
0 |
T107 |
5973 |
7 |
0 |
0 |
T113 |
71749 |
447 |
0 |
0 |
T114 |
9766 |
35 |
0 |
0 |
T127 |
12616 |
63 |
0 |
0 |
T128 |
34616 |
120 |
0 |
0 |
T129 |
35808 |
179 |
0 |
0 |
T130 |
68306 |
790 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
5466 |
0 |
0 |
T78 |
3226 |
14 |
0 |
0 |
T88 |
15096 |
62 |
0 |
0 |
T93 |
16277 |
2 |
0 |
0 |
T101 |
99075 |
910 |
0 |
0 |
T107 |
5973 |
4 |
0 |
0 |
T113 |
71749 |
507 |
0 |
0 |
T114 |
9766 |
25 |
0 |
0 |
T127 |
12616 |
43 |
0 |
0 |
T128 |
34616 |
144 |
0 |
0 |
T129 |
35808 |
217 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
5638 |
0 |
0 |
T78 |
3226 |
11 |
0 |
0 |
T88 |
15096 |
72 |
0 |
0 |
T101 |
99075 |
690 |
0 |
0 |
T107 |
5973 |
98 |
0 |
0 |
T113 |
71749 |
409 |
0 |
0 |
T114 |
9766 |
35 |
0 |
0 |
T127 |
12616 |
30 |
0 |
0 |
T128 |
34616 |
191 |
0 |
0 |
T129 |
35808 |
238 |
0 |
0 |
T130 |
68306 |
426 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
6118 |
0 |
0 |
T78 |
3226 |
6 |
0 |
0 |
T88 |
15096 |
55 |
0 |
0 |
T101 |
99075 |
593 |
0 |
0 |
T107 |
5973 |
53 |
0 |
0 |
T113 |
71749 |
483 |
0 |
0 |
T114 |
9766 |
69 |
0 |
0 |
T127 |
12616 |
21 |
0 |
0 |
T128 |
34616 |
35 |
0 |
0 |
T129 |
35808 |
359 |
0 |
0 |
T130 |
68306 |
768 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
5550 |
0 |
0 |
T78 |
3226 |
7 |
0 |
0 |
T88 |
15096 |
111 |
0 |
0 |
T101 |
99075 |
941 |
0 |
0 |
T107 |
5973 |
9 |
0 |
0 |
T113 |
71749 |
441 |
0 |
0 |
T114 |
9766 |
33 |
0 |
0 |
T127 |
12616 |
47 |
0 |
0 |
T128 |
34616 |
79 |
0 |
0 |
T129 |
35808 |
139 |
0 |
0 |
T130 |
68306 |
434 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
5861 |
0 |
0 |
T78 |
3226 |
6 |
0 |
0 |
T88 |
15096 |
71 |
0 |
0 |
T101 |
99075 |
681 |
0 |
0 |
T107 |
5973 |
42 |
0 |
0 |
T113 |
71749 |
498 |
0 |
0 |
T114 |
9766 |
46 |
0 |
0 |
T127 |
12616 |
23 |
0 |
0 |
T128 |
34616 |
119 |
0 |
0 |
T129 |
35808 |
411 |
0 |
0 |
T130 |
68306 |
761 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
5796 |
0 |
0 |
T78 |
3226 |
6 |
0 |
0 |
T88 |
15096 |
80 |
0 |
0 |
T101 |
99075 |
734 |
0 |
0 |
T107 |
5973 |
73 |
0 |
0 |
T113 |
71749 |
405 |
0 |
0 |
T114 |
9766 |
69 |
0 |
0 |
T127 |
12616 |
36 |
0 |
0 |
T128 |
34616 |
106 |
0 |
0 |
T129 |
35808 |
222 |
0 |
0 |
T130 |
68306 |
576 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
5517 |
0 |
0 |
T78 |
3226 |
10 |
0 |
0 |
T88 |
15096 |
103 |
0 |
0 |
T101 |
99075 |
941 |
0 |
0 |
T107 |
5973 |
64 |
0 |
0 |
T113 |
71749 |
458 |
0 |
0 |
T114 |
9766 |
1 |
0 |
0 |
T127 |
12616 |
36 |
0 |
0 |
T128 |
34616 |
176 |
0 |
0 |
T129 |
35808 |
249 |
0 |
0 |
T130 |
68306 |
158 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
5582 |
0 |
0 |
T78 |
3226 |
11 |
0 |
0 |
T88 |
15096 |
87 |
0 |
0 |
T101 |
99075 |
769 |
0 |
0 |
T107 |
5973 |
56 |
0 |
0 |
T113 |
71749 |
439 |
0 |
0 |
T114 |
9766 |
24 |
0 |
0 |
T127 |
12616 |
29 |
0 |
0 |
T128 |
34616 |
251 |
0 |
0 |
T129 |
35808 |
238 |
0 |
0 |
T130 |
68306 |
583 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
5464 |
0 |
0 |
T78 |
3226 |
3 |
0 |
0 |
T88 |
15096 |
25 |
0 |
0 |
T101 |
99075 |
543 |
0 |
0 |
T107 |
5973 |
62 |
0 |
0 |
T113 |
71749 |
516 |
0 |
0 |
T114 |
9766 |
46 |
0 |
0 |
T127 |
12616 |
54 |
0 |
0 |
T128 |
34616 |
163 |
0 |
0 |
T129 |
35808 |
323 |
0 |
0 |
T130 |
68306 |
591 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
5407 |
0 |
0 |
T78 |
3226 |
2 |
0 |
0 |
T88 |
15096 |
134 |
0 |
0 |
T94 |
16784 |
8 |
0 |
0 |
T101 |
99075 |
608 |
0 |
0 |
T107 |
5973 |
135 |
0 |
0 |
T113 |
71749 |
470 |
0 |
0 |
T114 |
9766 |
43 |
0 |
0 |
T127 |
12616 |
7 |
0 |
0 |
T128 |
34616 |
188 |
0 |
0 |
T129 |
35808 |
207 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
5491 |
0 |
0 |
T78 |
3226 |
5 |
0 |
0 |
T88 |
15096 |
85 |
0 |
0 |
T101 |
99075 |
939 |
0 |
0 |
T107 |
5973 |
68 |
0 |
0 |
T113 |
71749 |
490 |
0 |
0 |
T114 |
9766 |
31 |
0 |
0 |
T127 |
12616 |
25 |
0 |
0 |
T128 |
34616 |
84 |
0 |
0 |
T129 |
35808 |
205 |
0 |
0 |
T130 |
68306 |
492 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
5820 |
0 |
0 |
T78 |
3226 |
8 |
0 |
0 |
T88 |
15096 |
24 |
0 |
0 |
T101 |
99075 |
821 |
0 |
0 |
T107 |
5973 |
103 |
0 |
0 |
T113 |
71749 |
471 |
0 |
0 |
T114 |
9766 |
80 |
0 |
0 |
T127 |
12616 |
34 |
0 |
0 |
T128 |
34616 |
124 |
0 |
0 |
T129 |
35808 |
146 |
0 |
0 |
T130 |
68306 |
615 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
5685 |
0 |
0 |
T78 |
3226 |
6 |
0 |
0 |
T88 |
15096 |
78 |
0 |
0 |
T101 |
99075 |
730 |
0 |
0 |
T107 |
5973 |
3 |
0 |
0 |
T113 |
71749 |
490 |
0 |
0 |
T114 |
9766 |
46 |
0 |
0 |
T127 |
12616 |
30 |
0 |
0 |
T128 |
34616 |
92 |
0 |
0 |
T129 |
35808 |
289 |
0 |
0 |
T130 |
68306 |
539 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
2557 |
0 |
0 |
T78 |
3226 |
16 |
0 |
0 |
T88 |
15096 |
9 |
0 |
0 |
T101 |
99075 |
153 |
0 |
0 |
T107 |
5973 |
15 |
0 |
0 |
T113 |
71749 |
473 |
0 |
0 |
T127 |
12616 |
32 |
0 |
0 |
T128 |
34616 |
43 |
0 |
0 |
T129 |
35808 |
67 |
0 |
0 |
T130 |
68306 |
84 |
0 |
0 |
T131 |
16044 |
32 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
2665 |
0 |
0 |
T78 |
3226 |
6 |
0 |
0 |
T88 |
15096 |
26 |
0 |
0 |
T101 |
99075 |
143 |
0 |
0 |
T107 |
5973 |
8 |
0 |
0 |
T113 |
71749 |
413 |
0 |
0 |
T114 |
9766 |
8 |
0 |
0 |
T127 |
12616 |
21 |
0 |
0 |
T128 |
34616 |
17 |
0 |
0 |
T129 |
35808 |
63 |
0 |
0 |
T130 |
68306 |
111 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
2540 |
0 |
0 |
T78 |
3226 |
1 |
0 |
0 |
T88 |
15096 |
34 |
0 |
0 |
T101 |
99075 |
186 |
0 |
0 |
T107 |
5973 |
8 |
0 |
0 |
T113 |
71749 |
437 |
0 |
0 |
T114 |
9766 |
18 |
0 |
0 |
T127 |
12616 |
22 |
0 |
0 |
T128 |
34616 |
28 |
0 |
0 |
T129 |
35808 |
36 |
0 |
0 |
T130 |
68306 |
101 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
2672 |
0 |
0 |
T78 |
3226 |
11 |
0 |
0 |
T88 |
15096 |
29 |
0 |
0 |
T101 |
99075 |
185 |
0 |
0 |
T107 |
5973 |
7 |
0 |
0 |
T113 |
71749 |
403 |
0 |
0 |
T114 |
9766 |
12 |
0 |
0 |
T127 |
12616 |
39 |
0 |
0 |
T128 |
34616 |
52 |
0 |
0 |
T129 |
35808 |
50 |
0 |
0 |
T130 |
68306 |
123 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
3323 |
0 |
0 |
T78 |
3226 |
13 |
0 |
0 |
T88 |
15096 |
36 |
0 |
0 |
T101 |
99075 |
319 |
0 |
0 |
T107 |
5973 |
22 |
0 |
0 |
T113 |
71749 |
457 |
0 |
0 |
T114 |
9766 |
19 |
0 |
0 |
T127 |
12616 |
41 |
0 |
0 |
T128 |
34616 |
66 |
0 |
0 |
T129 |
35808 |
87 |
0 |
0 |
T130 |
68306 |
219 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
4967 |
0 |
0 |
T19 |
411973 |
0 |
0 |
0 |
T26 |
112702 |
44 |
0 |
0 |
T27 |
119031 |
0 |
0 |
0 |
T36 |
113772 |
0 |
0 |
0 |
T41 |
177711 |
0 |
0 |
0 |
T42 |
307083 |
0 |
0 |
0 |
T45 |
0 |
5 |
0 |
0 |
T55 |
5318 |
0 |
0 |
0 |
T59 |
706886 |
0 |
0 |
0 |
T121 |
0 |
14 |
0 |
0 |
T132 |
0 |
62 |
0 |
0 |
T133 |
0 |
10 |
0 |
0 |
T134 |
0 |
6 |
0 |
0 |
T135 |
0 |
24 |
0 |
0 |
T136 |
0 |
5 |
0 |
0 |
T137 |
0 |
58 |
0 |
0 |
T138 |
0 |
70 |
0 |
0 |
T139 |
9238 |
0 |
0 |
0 |
T140 |
24374 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
2602 |
0 |
0 |
T78 |
3226 |
5 |
0 |
0 |
T88 |
15096 |
31 |
0 |
0 |
T101 |
99075 |
167 |
0 |
0 |
T107 |
5973 |
8 |
0 |
0 |
T113 |
71749 |
463 |
0 |
0 |
T127 |
12616 |
61 |
0 |
0 |
T128 |
34616 |
22 |
0 |
0 |
T129 |
35808 |
69 |
0 |
0 |
T130 |
68306 |
146 |
0 |
0 |
T131 |
16044 |
47 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
2783 |
0 |
0 |
T78 |
3226 |
9 |
0 |
0 |
T88 |
15096 |
30 |
0 |
0 |
T101 |
99075 |
211 |
0 |
0 |
T107 |
5973 |
4 |
0 |
0 |
T113 |
71749 |
421 |
0 |
0 |
T114 |
9766 |
12 |
0 |
0 |
T127 |
12616 |
37 |
0 |
0 |
T128 |
34616 |
39 |
0 |
0 |
T129 |
35808 |
75 |
0 |
0 |
T130 |
68306 |
132 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
2459 |
0 |
0 |
T78 |
3226 |
7 |
0 |
0 |
T88 |
15096 |
19 |
0 |
0 |
T101 |
99075 |
117 |
0 |
0 |
T107 |
5973 |
13 |
0 |
0 |
T113 |
71749 |
465 |
0 |
0 |
T114 |
9766 |
7 |
0 |
0 |
T127 |
12616 |
73 |
0 |
0 |
T128 |
34616 |
38 |
0 |
0 |
T129 |
35808 |
33 |
0 |
0 |
T130 |
68306 |
96 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
2474 |
0 |
0 |
T78 |
3226 |
3 |
0 |
0 |
T88 |
15096 |
31 |
0 |
0 |
T101 |
99075 |
137 |
0 |
0 |
T107 |
5973 |
11 |
0 |
0 |
T113 |
71749 |
466 |
0 |
0 |
T114 |
9766 |
6 |
0 |
0 |
T127 |
12616 |
27 |
0 |
0 |
T128 |
34616 |
43 |
0 |
0 |
T129 |
35808 |
39 |
0 |
0 |
T130 |
68306 |
71 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
2393 |
0 |
0 |
T78 |
3226 |
9 |
0 |
0 |
T88 |
15096 |
21 |
0 |
0 |
T101 |
99075 |
110 |
0 |
0 |
T107 |
5973 |
1 |
0 |
0 |
T113 |
71749 |
493 |
0 |
0 |
T114 |
9766 |
7 |
0 |
0 |
T127 |
12616 |
34 |
0 |
0 |
T128 |
34616 |
13 |
0 |
0 |
T129 |
35808 |
44 |
0 |
0 |
T130 |
68306 |
71 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
2402 |
0 |
0 |
T78 |
3226 |
14 |
0 |
0 |
T88 |
15096 |
34 |
0 |
0 |
T101 |
99075 |
120 |
0 |
0 |
T107 |
5973 |
5 |
0 |
0 |
T113 |
71749 |
428 |
0 |
0 |
T114 |
9766 |
15 |
0 |
0 |
T127 |
12616 |
47 |
0 |
0 |
T128 |
34616 |
49 |
0 |
0 |
T129 |
35808 |
58 |
0 |
0 |
T130 |
68306 |
79 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
3420 |
0 |
0 |
T78 |
3226 |
9 |
0 |
0 |
T88 |
15096 |
35 |
0 |
0 |
T101 |
99075 |
248 |
0 |
0 |
T107 |
5973 |
4 |
0 |
0 |
T113 |
71749 |
452 |
0 |
0 |
T114 |
9766 |
32 |
0 |
0 |
T127 |
12616 |
17 |
0 |
0 |
T128 |
34616 |
67 |
0 |
0 |
T129 |
35808 |
149 |
0 |
0 |
T130 |
68306 |
206 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
2459 |
0 |
0 |
T78 |
3226 |
8 |
0 |
0 |
T88 |
15096 |
23 |
0 |
0 |
T101 |
99075 |
117 |
0 |
0 |
T107 |
5973 |
4 |
0 |
0 |
T113 |
71749 |
430 |
0 |
0 |
T114 |
9766 |
1 |
0 |
0 |
T127 |
12616 |
55 |
0 |
0 |
T128 |
34616 |
29 |
0 |
0 |
T129 |
35808 |
32 |
0 |
0 |
T130 |
68306 |
90 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
3430 |
0 |
0 |
T78 |
3226 |
2 |
0 |
0 |
T88 |
15096 |
56 |
0 |
0 |
T101 |
99075 |
373 |
0 |
0 |
T107 |
5973 |
18 |
0 |
0 |
T113 |
71749 |
426 |
0 |
0 |
T114 |
9766 |
4 |
0 |
0 |
T127 |
12616 |
39 |
0 |
0 |
T128 |
34616 |
69 |
0 |
0 |
T129 |
35808 |
122 |
0 |
0 |
T130 |
68306 |
199 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
2702 |
0 |
0 |
T78 |
3226 |
10 |
0 |
0 |
T88 |
15096 |
46 |
0 |
0 |
T101 |
99075 |
184 |
0 |
0 |
T107 |
5973 |
20 |
0 |
0 |
T113 |
71749 |
454 |
0 |
0 |
T114 |
9766 |
13 |
0 |
0 |
T127 |
12616 |
37 |
0 |
0 |
T128 |
34616 |
36 |
0 |
0 |
T129 |
35808 |
43 |
0 |
0 |
T130 |
68306 |
154 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
2328 |
0 |
0 |
T78 |
3226 |
13 |
0 |
0 |
T88 |
15096 |
25 |
0 |
0 |
T94 |
16784 |
6 |
0 |
0 |
T101 |
99075 |
113 |
0 |
0 |
T107 |
5973 |
5 |
0 |
0 |
T113 |
71749 |
456 |
0 |
0 |
T114 |
9766 |
6 |
0 |
0 |
T127 |
12616 |
21 |
0 |
0 |
T128 |
34616 |
20 |
0 |
0 |
T129 |
35808 |
35 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
2354 |
0 |
0 |
T78 |
3226 |
4 |
0 |
0 |
T88 |
15096 |
22 |
0 |
0 |
T101 |
99075 |
105 |
0 |
0 |
T107 |
5973 |
4 |
0 |
0 |
T113 |
71749 |
418 |
0 |
0 |
T114 |
9766 |
11 |
0 |
0 |
T127 |
12616 |
24 |
0 |
0 |
T128 |
34616 |
30 |
0 |
0 |
T129 |
35808 |
29 |
0 |
0 |
T130 |
68306 |
88 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
2452 |
0 |
0 |
T78 |
3226 |
4 |
0 |
0 |
T88 |
15096 |
19 |
0 |
0 |
T95 |
11670 |
4 |
0 |
0 |
T101 |
99075 |
118 |
0 |
0 |
T107 |
5973 |
1 |
0 |
0 |
T113 |
71749 |
423 |
0 |
0 |
T114 |
9766 |
1 |
0 |
0 |
T127 |
12616 |
50 |
0 |
0 |
T128 |
34616 |
12 |
0 |
0 |
T129 |
35808 |
38 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
2433 |
0 |
0 |
T78 |
3226 |
9 |
0 |
0 |
T88 |
15096 |
23 |
0 |
0 |
T101 |
99075 |
140 |
0 |
0 |
T107 |
5973 |
7 |
0 |
0 |
T113 |
71749 |
408 |
0 |
0 |
T114 |
9766 |
8 |
0 |
0 |
T127 |
12616 |
56 |
0 |
0 |
T128 |
34616 |
6 |
0 |
0 |
T129 |
35808 |
52 |
0 |
0 |
T130 |
68306 |
112 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
2458 |
0 |
0 |
T78 |
3226 |
9 |
0 |
0 |
T88 |
15096 |
24 |
0 |
0 |
T101 |
99075 |
124 |
0 |
0 |
T107 |
5973 |
10 |
0 |
0 |
T113 |
71749 |
459 |
0 |
0 |
T127 |
12616 |
71 |
0 |
0 |
T128 |
34616 |
37 |
0 |
0 |
T129 |
35808 |
48 |
0 |
0 |
T130 |
68306 |
79 |
0 |
0 |
T131 |
16044 |
36 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
675073030 |
2432 |
0 |
0 |
T78 |
3226 |
7 |
0 |
0 |
T88 |
15096 |
20 |
0 |
0 |
T101 |
99075 |
121 |
0 |
0 |
T107 |
5973 |
14 |
0 |
0 |
T113 |
71749 |
468 |
0 |
0 |
T114 |
9766 |
3 |
0 |
0 |
T127 |
12616 |
24 |
0 |
0 |
T128 |
34616 |
21 |
0 |
0 |
T129 |
35808 |
50 |
0 |
0 |
T130 |
68306 |
72 |
0 |
0 |